JPH07263573A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH07263573A JPH07263573A JP6053999A JP5399994A JPH07263573A JP H07263573 A JPH07263573 A JP H07263573A JP 6053999 A JP6053999 A JP 6053999A JP 5399994 A JP5399994 A JP 5399994A JP H07263573 A JPH07263573 A JP H07263573A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- polysilicon
- tantalum oxide
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 43
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 118
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 6
- 229910001882 dioxygen Inorganic materials 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- FPCJKVGGYOAWIZ-UHFFFAOYSA-N butan-1-ol;titanium Chemical compound [Ti].CCCCO.CCCCO.CCCCO.CCCCO FPCJKVGGYOAWIZ-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- HSXKFDGTKKAEHL-UHFFFAOYSA-N tantalum(v) ethoxide Chemical compound [Ta+5].CC[O-].CC[O-].CC[O-].CC[O-].CC[O-] HSXKFDGTKKAEHL-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、誘電体膜を用いるキャ
パシタ、ＭＯＳＦＥＴ、ＤＲＡＭ等の半導体装置及びそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a capacitor, a MOSFET and a DRAM which uses a dielectric film, and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、誘電体膜を用いたキャパシタとし
て、２５の高い比誘電率を持つ酸化タンタル膜（Ｔａ2
Ｏ5）を用いたキャパシタが知られているが、上部電極
にポリシリコン（ｐｏｌｙーＳｉ）を用いる場合、８０
０℃程度の高温熱処理を施すとポリシリコンと酸化タン
タル膜が反応、リーク電流が増大してしまうという問題
があった。この反応を防止するため、例えばＨ.Ｓｈｉ
ｎｒｉｋｉ ｅｔ ａｌ、１９８８Ｓｙｍｐ. ＶＬＳ
Ｉ Ｔｅｃｈｎｏｌｏｇｙ（1988）ｐｐ.29〜30には、
上部電極であるポリシリコン膜と誘電体膜である酸化タ
ンタル膜との間に、反応防止膜として酸化シリコン膜ま
たは窒化シリコン膜を用いることにより後の製造工程に
不可欠な高温熱処理を行ってもポリシリコン膜と酸化タ
ンタル膜が反応せずリーク電流の増大がないキャパシタ
が開示されている。2. Description of the Related Art Conventionally, as a capacitor using a dielectric film, a tantalum oxide film (Ta2
A capacitor using O5) is known, but in the case of using polysilicon (poly-Si) for the upper electrode,
When the high temperature heat treatment of about 0 ° C. is performed, there is a problem that the polysilicon and the tantalum oxide film react with each other and the leak current increases. To prevent this reaction, for example, H. Shi
nriki et al, 1988 Symp. VLS
I Technology (1988) pp.29-30,
By using a silicon oxide film or a silicon nitride film as a reaction preventive film between the polysilicon film which is the upper electrode and the tantalum oxide film which is the dielectric film, even if a high temperature heat treatment which is indispensable for the subsequent manufacturing process is performed, A capacitor in which a silicon film and a tantalum oxide film do not react with each other and a leak current does not increase is disclosed.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら上記文献
に開示されるような従来技術では、反応防止膜としての
酸化シリコン膜または窒化シリコン膜の比誘電率が酸化
シリコンは４、窒化シリコンでも７と低く、これらの膜
を用いた場合、キャパシタの容量が大幅に減少してしま
うという問題があった。However, in the prior art disclosed in the above document, the relative dielectric constant of the silicon oxide film or the silicon nitride film as the reaction preventing film is as low as 4 for silicon oxide and 7 for silicon nitride. However, when using these films, there is a problem that the capacitance of the capacitor is significantly reduced.
【０００４】[0004]
【課題を解決する手段】上記の問題を解決するために、
基体上に、誘電体膜として酸化タンタル、この酸化タン
タル上に反応防止膜として酸化チタン、この酸化チタン
上にポリシリコンを備えた構造の半導体装置とする。[Means for Solving the Problems] In order to solve the above problems,
A semiconductor device having a structure in which tantalum oxide as a dielectric film, titanium oxide as a reaction preventing film on this tantalum oxide, and polysilicon on this titanium oxide are provided on a substrate is provided.
【０００５】[0005]
【作用】本発明によれば、約９０と非常に高い比誘電率
を持つ酸化チタンをポリシリコンと酸化タンタルとの間
に設けたので、容量が大きい半導体装置となるだけでな
く、高温熱処理を施してもポリシリコンと酸化タンタル
との反応がこの酸化チタンによって防止され、リーク電
流が減少する。According to the present invention, since titanium oxide having a very high relative dielectric constant of about 90 is provided between polysilicon and tantalum oxide, not only a semiconductor device having a large capacitance but also a high temperature heat treatment is performed. Even if applied, the reaction between polysilicon and tantalum oxide is prevented by this titanium oxide, and the leak current is reduced.
【０００６】[0006]
第１実施例 図１は、本発明によるキャパシタの構造を示す一例であ
る。図１におけるキャパシタは、シリコン基板２１上に
酸化シリコン膜２２、その上に選択的に下部電極として
のポリシリコン膜２３ａが形成され、このポリシリコン
膜２３ａを覆うように酸化シリコン膜２５、酸化タンタ
ル膜２４、酸化チタン膜２６、上部電極としてのポリシ
リコン膜２７が順次形成されている。First Embodiment FIG. 1 is an example showing the structure of a capacitor according to the present invention. In the capacitor shown in FIG. 1, a silicon oxide film 22 is formed on a silicon substrate 21, and a polysilicon film 23a as a lower electrode is selectively formed on the silicon oxide film 22. A silicon oxide film 25 and a tantalum oxide film are formed to cover the polysilicon film 23a. A film 24, a titanium oxide film 26, and a polysilicon film 27 as an upper electrode are sequentially formed.
【０００７】以上のように形成された酸化タンタル膜を
用いたキャパシタ（以下、酸化タンタル膜キャパシタと
いう）においては、誘電体膜の酸化タンタル膜２４と上
部電極のポリシリコン膜２７との間に反応防止膜として
酸化チタン膜２６を設けているので、酸化タンタル膜２
４とポリシリコン膜２７との反応が防止される。In the capacitor using the tantalum oxide film formed as described above (hereinafter referred to as "tantalum oxide film capacitor"), a reaction occurs between the tantalum oxide film 24 of the dielectric film and the polysilicon film 27 of the upper electrode. Since the titanium oxide film 26 is provided as the prevention film, the tantalum oxide film 2
4 and the polysilicon film 27 are prevented from reacting.
【０００８】また、図２（Ａ）〜（Ｄ）に本発明の実施
例によるキャパシタの製造工程の断面図を示し、以下本
発明の実施例について図面を参照しながら詳細に説明す
る。2 (A) to 2 (D) are cross-sectional views showing a process of manufacturing a capacitor according to an embodiment of the present invention, and an embodiment of the present invention will be described in detail below with reference to the drawings.
【０００９】図２（Ａ）に示すように、シリコン基板２
１上に熱酸化法或は化学気相成長（ＣＶＤ）法により酸
化シリコン膜２２を８００ｎｍ程度成長させ、さらに、
下部電極となるポリシリコン膜２３をＣＶＤ法等により
３００ｎｍ程度形成する。このポリシリコン膜２３の低
抵抗化のため、イオン注入法により、または、塩化ホス
ホリルガス雰囲気中における熱拡散により、リンをポリ
シリコン膜２３に導入する。As shown in FIG. 2A, the silicon substrate 2
1. A silicon oxide film 22 is grown to a thickness of about 800 nm on 1 by a thermal oxidation method or a chemical vapor deposition (CVD) method.
The polysilicon film 23 to be the lower electrode is formed to a thickness of about 300 nm by the CVD method or the like. To reduce the resistance of the polysilicon film 23, phosphorus is introduced into the polysilicon film 23 by an ion implantation method or by thermal diffusion in a phosphoryl chloride gas atmosphere.
【００１０】次に、ポリシリコン膜２３上にレジストパ
ターンを形成し（図示せず）、このレジストパターンを
マスクとしてポリシリコン膜２３の不要部分をエッチン
グすることで、ポリシリコン膜２３がパターニングさ
れ、図２（Ｂ）に示すように下部電極のポリシリコン膜
２３ａが形成される。Next, a resist pattern is formed on the polysilicon film 23 (not shown), and unnecessary portions of the polysilicon film 23 are etched by using this resist pattern as a mask to pattern the polysilicon film 23, As shown in FIG. 2B, a lower electrode polysilicon film 23a is formed.
【００１１】図２（Ｃ）に示すように、ポリシリコン膜
２３ａ上にＣＶＤ法により、ペンタエトキシタンタルと
酸素ガスを用い４００℃の基板温度で酸化タンタル膜２
４を１０ｎｍ程度形成する。この酸素ガスを用いて酸化
タンタル膜を形成する際に、下部電極のポリシリコン膜
２３ａの表面が酸化され、ポリシリコン膜２３ａと酸化
タンタル膜２４の間には酸化シリコン膜２５が１ｎｍ程
度形成される。As shown in FIG. 2C, the tantalum oxide film 2 is formed on the polysilicon film 23a by CVD using pentaethoxytantalum and oxygen gas at a substrate temperature of 400.degree.
4 is formed to a thickness of about 10 nm. When the tantalum oxide film is formed using this oxygen gas, the surface of the polysilicon film 23a of the lower electrode is oxidized, and the silicon oxide film 25 is formed between the polysilicon film 23a and the tantalum oxide film 24 to have a thickness of about 1 nm. It
【００１２】さらに図２（Ｄ）に示すように、酸化タン
タル膜２４上にＣＶＤ法により、テトラブトキシチタン
と酸素ガスを用いて４００℃の基板温度で酸化チタン膜
２６を１０〜２０ｎｍ程度形成する。また、酸化タンタ
ル膜２４および酸化チタン膜２６の緻密化及び欠陥密度
の削減のため、それぞれの膜を形成した後に酸素雰囲気
中８００℃で１分間の熱処理を行うことが望ましい。Further, as shown in FIG. 2D, a titanium oxide film 26 of about 10 to 20 nm is formed on the tantalum oxide film 24 by a CVD method using tetrabutoxy titanium and oxygen gas at a substrate temperature of 400 ° C. . Further, in order to make the tantalum oxide film 24 and the titanium oxide film 26 dense and reduce the defect density, it is desirable to perform heat treatment at 800 ° C. for 1 minute in an oxygen atmosphere after forming each film.
【００１３】次に、上部電極としてのポリシリコン膜２
７をＣＶＤ法により３００ｎｍ程度形成する。以下は下
部電極を形成するときと同様、ポリシリコン膜２７の低
抵抗化のため、イオン注入法によりリンを、または、ガ
ス雰囲気中における熱拡散により塩化ホスホリルを、ポ
リシリコン膜２７に導入する。その後ポリシリコン膜２
７上にレジストパターンを形成し（図示せず）、このレ
ジストパターンをマスクとしてポリシリコン膜２７、酸
化チタン膜２６及び酸化タンタル膜２４の不要部分をエ
ッチングすることにより、図１に示した構造の酸化タン
タル膜キャパシタとなる。Next, the polysilicon film 2 as the upper electrode
7 is formed to a thickness of about 300 nm by the CVD method. As in the case of forming the lower electrode, phosphorus is introduced into the polysilicon film 27 by an ion implantation method or phosphoryl chloride by thermal diffusion in a gas atmosphere in order to reduce the resistance of the polysilicon film 27. Then polysilicon film 2
A resist pattern is formed on 7 (not shown), and unnecessary portions of the polysilicon film 27, the titanium oxide film 26, and the tantalum oxide film 24 are etched by using this resist pattern as a mask, so that the structure shown in FIG. It becomes a tantalum oxide film capacitor.
【００１４】また、上記の実施例以外にも本発明のキャ
パシタを製造することができ、その一例を示す。In addition to the above embodiments, the capacitor of the present invention can be manufactured, and one example thereof will be shown.
【００１５】シリコン基板２１上に酸化シリコン膜２
２、下部電極としてのポリシリコン膜２３ａを形成した
後、酸化タンタル膜２４を形成する方法としては、スパ
ッタ法によることもできる。高周波スパッタ法では、Ｔ
ａターゲットを用い、酸素ガス雰囲気中でスパッタする
ことにより酸化タンタル膜２４を形成する。The silicon oxide film 2 is formed on the silicon substrate 21.
2. As a method of forming the tantalum oxide film 24 after forming the polysilicon film 23a as the lower electrode, a sputtering method can also be used. In the high frequency sputtering method, T
Using a target, the tantalum oxide film 24 is formed by sputtering in an oxygen gas atmosphere.
【００１６】酸化チタン膜２６を形成する際にも同様
に、Ｔｉターゲットを用い、酸素ガス雰囲気中でスパッ
タすることにより、または、スパッタ法によりＴｉを形
成した後、酸素ガス雰囲気中、５００℃で１分間の熱処
理を行うことにより、酸化チタン膜２６を形成し、その
後同様の方法で上部電極を形成、不要部分の除去により
キャパシタを作製する。Similarly, when forming the titanium oxide film 26, a Ti target is used and sputtering is performed in an oxygen gas atmosphere, or after Ti is formed by a sputtering method, at 500 ° C. in an oxygen gas atmosphere. By performing heat treatment for 1 minute, a titanium oxide film 26 is formed, then an upper electrode is formed by the same method, and unnecessary portions are removed to produce a capacitor.
【００１７】ここで、酸化チタン膜の形成方法について
は種々のものが考えられるが、ＣＶＤ法またはスパッタ
法等の堆積法を使用することにより、容易に酸化チタン
膜を形成することができる。Various methods can be considered for forming the titanium oxide film, but the titanium oxide film can be easily formed by using a deposition method such as a CVD method or a sputtering method.
【００１８】第２実施例 本発明をＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅ
ｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ
Ｔｒａｎｓｉｓｔｏｒ）のゲート酸化膜に適用した例を
図３に示す。Second Embodiment The present invention is applied to a MOSFET (Metal Oxide Se).
miconductor Field Effect
An example applied to a gate oxide film of a transistor is shown in FIG.
【００１９】半導体基板３１の表面領域にチャネル領域
３３が形成され、チャネル領域３３の両側に不純物を拡
散したソース・ドレイン領域３２とが対向して配置さ
れ、チャネル領域の表面上にゲート酸化膜として酸化タ
ンタル膜３４と酸化チタン膜３５とが積層され、このゲ
ート酸化膜の表面上にゲート電極としてポリシリコン膜
３６が形成されている。A channel region 33 is formed in the surface region of the semiconductor substrate 31, and the source / drain regions 32 in which impurities are diffused are arranged on opposite sides of the channel region 33 so as to face each other, and serve as a gate oxide film on the surface of the channel region. A tantalum oxide film 34 and a titanium oxide film 35 are laminated, and a polysilicon film 36 is formed as a gate electrode on the surface of this gate oxide film.
【００２０】ＭＯＳＦＥＴを微細化する場合、比例縮小
則に従いゲート酸化膜厚も薄膜化しなければならない。
微細化の指標である０．１５μｍ程度のゲート電極寸法
では、酸化シリコンに換算した膜厚で３ｎｍ程度のゲー
ト酸化膜にする必要がある。しかし酸化シリコン膜厚で
３ｎｍ以下ではトンネリングによりリーク電流が増大し
てしまい、ＭＯＳＦＥＴとして動作しなくなってしま
う。このため、本発明をＭＯＳＦＥＴのゲート酸化膜に
適用することによって微細化によりゲート酸化膜を薄膜
化してもリーク電流増大のないＭＯＳＦＥＴとなる。ま
た、０．１５μｍ以上のゲート電極寸法のＭＯＳＦＥＴ
においても、ゲート酸化膜の薄膜化によりゲート酸化膜
容量が増加、相互コンダクタンスが大きくなり、スイッ
チングの応答速度が速い高速のＭＯＳＦＥＴを実現でき
る。When miniaturizing the MOSFET, the gate oxide film thickness must be thinned according to the proportional reduction rule.
With a gate electrode size of about 0.15 μm, which is an index of miniaturization, it is necessary to form a gate oxide film with a film thickness converted to silicon oxide of about 3 nm. However, if the thickness of the silicon oxide film is 3 nm or less, the leak current increases due to tunneling, and the MOSFET does not operate. Therefore, when the present invention is applied to the gate oxide film of the MOSFET, the leak current does not increase even if the gate oxide film is thinned by miniaturization. In addition, a MOSFET having a gate electrode size of 0.15 μm or more
Also in the above, the gate oxide film capacitance increases due to the thinning of the gate oxide film, the transconductance increases, and a high-speed MOSFET with a fast switching response speed can be realized.
【００２１】第３実施例 本発明を半導体基板を共通とする１つＭＯＳＦＥＴと１
つのキャパシタにより構成されるＤＲＡＭのメモリセル
部に適用した例を図４に示す。図４でＭＯＳＦＥＴとし
て第２実施例で用いたＭＯＳＦＥＴを使用、同じ符号
（ソース・ドレイン領域３２、チャネル領域３３、酸化
タンタル膜３４、酸化チタン膜３５およびポリシリコン
膜３６）とする。キャパシタとして、半導体基板４１上
に下部電極４３、下部電極４３上に酸化タンタル膜４
４、酸化タンタル膜４４上に酸化チタン膜４５、酸化チ
タン膜４５上に上部電極４６、で構成されている。Third Embodiment The present invention includes one MOSFET having a common semiconductor substrate and one MOSFET.
FIG. 4 shows an example applied to a memory cell portion of a DRAM composed of two capacitors. In FIG. 4, the MOSFET used in the second embodiment is used as the MOSFET and has the same reference numerals (source / drain region 32, channel region 33, tantalum oxide film 34, titanium oxide film 35 and polysilicon film 36). As a capacitor, the lower electrode 43 is formed on the semiconductor substrate 41, and the tantalum oxide film 4 is formed on the lower electrode 43.
4. A titanium oxide film 45 is formed on the tantalum oxide film 44, and an upper electrode 46 is formed on the titanium oxide film 45.
【００２２】以上のように、本発明を適用したキャパシ
タをＤＲＡＭのメモリセル部等に使用することによっ
て、単位面積当りのキャパシタ容量を増大できる。これ
は、ＤＲＡＭ等の高集積化により望まれているメモリセ
ルサイズの小型化という需要に応えるものである。ま
た、ＭＯＳＦＥＴを使用することにより、第２実施例で
述べた効果を享受できる。As described above, by using the capacitor to which the present invention is applied in the memory cell portion of DRAM or the like, the capacitance of the capacitor per unit area can be increased. This meets the demand for miniaturization of the memory cell size, which is desired due to high integration of DRAM and the like. Further, by using the MOSFET, the effect described in the second embodiment can be enjoyed.
【００２３】上記に示した本発明の酸化タンタル膜キャ
パシタにおいて、酸化タンタル膜とポリシリコン膜との
間の酸化チタン膜の存在によって、酸化タンタル膜とポ
リシリコン膜との反応が防止される。このことは、図５
に示す酸化物の標準生成自由エネルギーの温度図を参照
することで理解できる。この図５は、「ＶＬＳＩの薄膜
技術」伊藤隆司他、丸善株式会社（昭和６１年９月３０
日）発行、ｐｐ.１５２に示されるものである。In the tantalum oxide film capacitor of the present invention described above, the presence of the titanium oxide film between the tantalum oxide film and the polysilicon film prevents the reaction between the tantalum oxide film and the polysilicon film. This is shown in FIG.
This can be understood by referring to the temperature diagram of the standard free energy of formation of oxide shown in. FIG. 5 shows “VLSI thin film technology” by Takashi Ito et al., Maruzen Co., Ltd. (September 30, 1986)
Issue), pp.152.
【００２４】Ｔａ2Ｏ5（酸化タンタル膜）のΔＧｆ（酸
化物の標準生成自由エネルギー）はいずれの温度におい
てもＳｉＯ2（酸化シリコン膜）のΔＧｆより大きい。
これは、酸化タンタル膜とポリシリコン膜が接している
ときはシリコンの方が酸化されやすく、タンタルは還元
されやすいことを示している。よってこの場合には、タ
ンタルが還元され、金属としてのＴａが酸化タンタル膜
中に発生することにより、リーク電流が増大することに
なる。これとは逆に、ＴｉＯ2（酸化チタン膜）のΔＧ
ｆはいずれの温度においてもＳｉＯ2（酸化シリコン
膜）のΔＧｆより小さい。よって、酸化チタン膜とポリ
シリコン膜が接していてもポリシリコン、チタン共に反
応せず、リーク電流の増大を防ぐことができる。ΔGf (standard free energy of formation of oxide) of Ta 2 O 5 (tantalum oxide film) is larger than ΔGf of SiO 2 (silicon oxide film) at any temperature.
This indicates that when the tantalum oxide film and the polysilicon film are in contact with each other, silicon is more easily oxidized and tantalum is more easily reduced. Therefore, in this case, tantalum is reduced and Ta as a metal is generated in the tantalum oxide film, so that the leak current is increased. On the contrary, ΔG of TiO2 (titanium oxide film)
f is smaller than ΔGf of SiO2 (silicon oxide film) at any temperature. Therefore, even if the titanium oxide film and the polysilicon film are in contact with each other, neither polysilicon nor titanium reacts with each other, and an increase in leak current can be prevented.
【００２５】また、反応防止膜として例えば窒化チタン
が考えられるが、この窒化チタンを用いた場合には高温
熱処理を行うことによってリーク電流が増加してしま
う、ということが実験結果から得られている。Further, although titanium nitride can be considered as the reaction preventing film, it has been obtained from the experimental results that the leakage current increases when the titanium nitride is used and the high temperature heat treatment is performed. .
【００２６】[0026]
【発明の効果】以上詳細に説明したように本発明の酸化
タンタル膜を用いた半導体装置によれば、酸化タンタル
とポリシリコンとの間に酸化チタンが形成されているた
め、高温熱処理を行っても酸化タンタルとポリシリコン
との反応が起こらなくなり、リーク電流の増加を抑さえ
ることができるだけでなく、酸化チタン膜の比誘電率が
高いため、単位面積当りの容量が大きい半導体装置とな
る。As described in detail above, according to the semiconductor device using the tantalum oxide film of the present invention, since titanium oxide is formed between tantalum oxide and polysilicon, high temperature heat treatment is performed. In addition, the reaction between tantalum oxide and polysilicon does not occur, so that an increase in leak current can be suppressed, and since the titanium oxide film has a high relative dielectric constant, the semiconductor device has a large capacitance per unit area.
【図１】本発明の実施例によるキャパシタの構造を示す
断面図FIG. 1 is a sectional view showing a structure of a capacitor according to an embodiment of the present invention.
【図２】本発明の実施例によるキャパシタの製造工程を
示す断面図FIG. 2 is a cross-sectional view showing a manufacturing process of a capacitor according to an embodiment of the present invention.
【図３】本発明の実施例によるＭＯＳＦＥＴの構造を示
す断面図FIG. 3 is a sectional view showing the structure of a MOSFET according to an embodiment of the present invention.
【図４】本発明の実施例によるＤＲＡＭのメモリセル部
の構造を示す断面図FIG. 4 is a sectional view showing a structure of a memory cell portion of a DRAM according to an embodiment of the present invention.
【図５】酸化物の標準生成自由エネルギーと温度との関
係図FIG. 5 is a relationship diagram between standard free energy of formation of oxide and temperature.
２１：シリコン基板 ２２：酸化シリコン膜 ２３：ポリシリコン膜 ２３ａ：ポリシリコン膜 ２４：酸化タンタル膜 ２５：酸化シリコン膜 ２６：酸化チタン膜 ２７：ポリシリコン膜 21: Silicon substrate 22: Silicon oxide film 23: Polysilicon film 23a: Polysilicon film 24: Tantalum oxide film 25: Silicon oxide film 26: Titanium oxide film 27: Polysilicon film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 29/78 21/336 Ｈ０１Ｌ 29/78 ３０１ Ｇ ３０１ Ｙ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/822 29/78 21/336 H01L 29/78 301 G 301 Y
Claims (4)
たキャパシタの下部電極であることを特徴とする請求項
１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the base is a lower electrode of a capacitor formed on the surface of the semiconductor substrate.
板表面領域に形成されたソース・ドレイン領域間のチャ
ネル領域であることを特徴とする請求項１記載の半導体
装置。3. The semiconductor device according to claim 1, wherein the base body is a semiconductor substrate and is a channel region between the source and drain regions formed in the substrate surface region.
と、 前記酸化タンタル上に酸化チタンを堆積法により形成す
る工程と、 前記酸化チタン上にポリシリコンを形成する工程と、 を備えたことを特徴とする半導体装置の製造方法。4. A step of forming tantalum oxide on a substrate, a step of forming titanium oxide on the tantalum oxide by a deposition method, and a step of forming polysilicon on the titanium oxide. A method for manufacturing a characteristic semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6053999A JPH07263573A (en) | 1994-03-24 | 1994-03-24 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6053999A JPH07263573A (en) | 1994-03-24 | 1994-03-24 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07263573A true JPH07263573A (en) | 1995-10-13 |
Family
ID=12958311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6053999A Pending JPH07263573A (en) | 1994-03-24 | 1994-03-24 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07263573A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001036031A (en) * | 1999-06-25 | 2001-02-09 | Hyundai Electronics Ind Co Ltd | Capacitor for semiconductor memory device and method of manufacturing the same |
| JP2001230386A (en) * | 1999-12-22 | 2001-08-24 | Hynix Semiconductor Inc | Semiconductor device including high dielectric capacitor dielectric and method of manufacturing the same |
| KR20010088207A (en) * | 2000-03-11 | 2001-09-26 | 윤종용 | Method of forming composite dielectric film of tantalum oxide and titanium oxide |
| KR100497142B1 (en) * | 1999-11-09 | 2005-06-29 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
-
1994
- 1994-03-24 JP JP6053999A patent/JPH07263573A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001036031A (en) * | 1999-06-25 | 2001-02-09 | Hyundai Electronics Ind Co Ltd | Capacitor for semiconductor memory device and method of manufacturing the same |
| KR100497142B1 (en) * | 1999-11-09 | 2005-06-29 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| JP2001230386A (en) * | 1999-12-22 | 2001-08-24 | Hynix Semiconductor Inc | Semiconductor device including high dielectric capacitor dielectric and method of manufacturing the same |
| KR20010088207A (en) * | 2000-03-11 | 2001-09-26 | 윤종용 | Method of forming composite dielectric film of tantalum oxide and titanium oxide |
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