JPH07264197A - Cell exchange device - Google Patents

Abstract

(57) [Abstract] [Purpose] In a common buffer type switch for exchanging cells or packets in ATM (asynchronous transfer mode) communication and high-speed packet communication, the cell discard rate is reduced without increasing the cost of an expensive common buffer memory. suppress. [Structure] The congestion determination circuit 20 monitors the number of cells reserved in the common buffer memory 11, and when it detects a congestion state, it congests the cell evacuation circuits 22 _{1 to} 22 _n provided corresponding to the incoming lines 1 ₁ to 1 _n. The state is notified and the cell is restricted from being input to the common buffer type switch 9. [Effect] By installing a large number of inexpensive save buffers without increasing the common buffer memory, it is possible to reduce the cell discard rate that occurs when the capacity of the common buffer memory in the common buffer type switch is exceeded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of information and communication, and is used for data of personal computers and workstations.
ATM (Asynchronous) for dividing various information such as telephone voice and multimedia image information into blocks called cells or packets for high-speed transmission and exchange.
us Transfer Mode, asynchronous transfer mode) or a cell or packet switching device in high-speed packet communication.
The present invention also relates to a device for temporarily storing and exchanging data.

[0002]

[Prior art]

Conventional example 1. FIG. 20 shows, for example, the document International Confer
ence on Communications, 1987, Session 22, Paper No. 2, Jean-Pierre Coudreuse, Michel Servel, ■ PR
ELUDE: An Asynchronous Time-Division Switched Netwo
The high-speed packet switch of rk, ■ is shown in a slightly modified form for explanation. This document relates to a high speed packet switch in an asynchronous transfer mode (ATM) communication system for efficiently multiplexing and transmitting circuit switched data and packet switched data.

In the ATM communication system, continuous signals such as line signals and voice, and burst signals such as data and moving images are all divided into fixed lengths, and destination information and the like are shown. Header is added to form a packet, and information is transferred in the same format packet. This packet is internationally standardized and is called a cell. In the following, this packet is called a cell, but the meaning is the same. Since it is not necessary to synchronize frames and the like between the terminal and the transmission path, and the speeds of the terminal and the transmission path may be independent, it is possible to support any terminal. However, since cells arrive at the fast cell switch randomly, a large number of cells may be flooded to one destination at a certain moment, and it is necessary to wait for cells to prevent loss of information. Occurs.

To solve this problem, for example, the above-mentioned document FIG.
And a fast cell switch is proposed in Fig.6.
FIG. 20 shows a block diagram of an example thereof. 1 ₁ to 1 _n are n (n ≧ 2) incoming lines to which data is input, and cells arriving here have a fixed length. 2 _{1 to} 2 _m are m (m ≧ 2) output lines from which cells are output. Reference numeral 7 is a cell multiplexing circuit that multiplexes input cells. A common buffer memory 11 can write data to a specified address and can read the data by specifying the address regardless of the writing order. Reference numeral 8 is a cell separation circuit for separating the read cells. Reference numeral 15 is a control circuit for controlling the exchange of cells.

A plurality of incoming lines 11 to ₁₁ of this high-speed cell switch
The cells arriving at 1 _n are multiplexed by the cell multiplexing circuit 7,
It is written in the common buffer memory 11. The header including the destination information of the arriving cell is sent to the buffer control circuit 15, the destination outgoing line 2 ₁ to 2 _m is determined. At the same time, a vacant address in the common buffer memory 11 is allocated, and this address is queued to correspond to the destination outgoing lines 2 ₁ to 2 _m . Further, the arrival cell is written at this address in the common buffer memory 11.

On the other hand, in the buffer control circuit 15, if there is an address at the front of the address matrix created for the destination outgoing lines 2 ₁ to 2 _m , the address is taken out. Cells are read from the common buffer memory 11 according to the read addresses, separated by the cell separation circuit 8, and the cells are output to predetermined output lines 2 ₁ to 2 _m . As described above, by the operation of the cell switch, the cells on the incoming lines 1 ₁ to 1 _n are output to the desired outgoing lines 2 ₁ to 2 _m , and the cells are exchanged.

Conventional example 2. FIG. 21 is a diagram showing the structure of an ATM switch capable of efficiently expanding the buffer capacity of a conventional multimedia service. The ATM switch shown in FIG. 21 is "Technical Report of IEICE Technical Report V
ol. 93 No. 11, SSE93-1 to 6) 199
It is a block diagram of the ATM switch shown by "ATM switch: XATOM which can expand buffer capacity" published in p31-p36 on April 23, 3rd. With this configuration,
By combining the advantages of the input buffer system and the output buffer system, accumulating cells in a large capacity low speed buffer and using a small amount of output buffer, scheduling is performed independently at each input port and at low speed. In this system, the input buffer is notified that cells can be accepted when the output buffer has a vacancy of the number of input lines (n) cells or more so that the input buffer can operate independently. In FIG. 21,
1 ₁ and 1 _n are incoming lines and 2 ₁ and 2 _n are outgoing lines. 900 ₁
˜900 _n is an input control unit, 901 _{1 to} 901 _n
Is an input buffer, 910 _{1 to} 910 _n are output control units, 911 _{1 to} 911 _n are output buffers, and 920 is a time division bus.

FIG. 22 is a diagram showing the configuration of the input control unit 900 ₁ . The input control unit 901 manages cells according to cell output destinations and in order of arrival.
31-930n. The control unit for input detects the destination of the packet that has arrived, and the corresponding memory 930 ₁
Allocate to any of the memory of ˜930 _n .

Next, the operation will be described with reference to FIGS. 21 and 22. When each of the output buffers 911 _{1 to} 911 _n is not in a congested state, the input control unit continues to output the cells arriving from the incoming line from the input buffer. If the number of accumulated cells in the output buffer 911 ₁ is increased, the output buffer 911 ₁ becomes congested, the input control unit 900 ₁ to 900 _n
Performs cell accumulation control on the input buffers 901 _{1 to} 901 _n so as not to output cells addressed to the output buffer 911 ₁ . Therefore, the input buffer 90
From 1 ₁ ～901 _n, the cell is not outputted to the output buffer 911 _1, the output buffer 911 ₁ during this time,
It is possible to eliminate congestion.

[0010]

Since the data queuing device shown in the prior art 1 is configured as described above, for example, the traffic in which a plurality of incoming lines are consecutive in cells, that is, the burst type is used. When high traffic is input and they are destined for a single outgoing line, the common buffer memory 11 becomes full and cells are discarded. In order to keep the cell discard rate low, the capacity of this common buffer memory may be expanded. However, the common buffer memory 11 needs to operate after multiplexing cells, and needs to operate at high speed, so it is very expensive, and the capacity cannot be increased technically. Further, since the increase in capacity also increases the scale of the buffer control circuit, there is a limit to the capacity expansion of the common buffer memory.

In the ATM switch shown in the conventional example 2, the capacity can be expanded in the input buffer, and by mounting a large capacity low speed buffer, it is possible to efficiently perform cell exchange with a small amount of output buffer. However, it is necessary for the input control unit to detect the destination of the cell arriving from the incoming line and sort it for each outgoing line. This is because the output buffers are provided corresponding to the respective output lines, so that the congestion state occurs individually in the respective output buffers. For output buffers where congestion has occurred,
In order to stop the supply of cells, it is necessary to judge in advance in which output buffer the cells that arrive on the input buffer side should be stored, which makes the control of the input buffer complicated. there were.

The present invention has been made in order to solve the above-mentioned problems, and the common buffer memory, which is expensive and technically limited in expansion, remains the same and has a newly low operating speed. It is an object of the present invention to provide a cell switching device that can suppress the cell discard due to the input of burst traffic by adding a buffer.

It is another object of the present invention to provide a cell switching device that can easily control a buffer having a low operating speed even when the buffer is added.

[0014]

In the cell exchange apparatus according to the present invention, the congestion determination circuit monitors the number of cells reserved in the common buffer memory, detects the congestion state, and responds to the incoming line. A cell discard rate that occurs when the capacity of the common buffer memory in the common buffer switch is exceeded by notifying the built-in cell evacuation circuit of the congestion status and limiting the input of cells to the common buffer switch. It is designed to lower.

A cell exchange apparatus according to a second aspect of the present invention is a case where the common buffer memory is composed of one buffer memory as a whole.

A cell exchange apparatus according to a third aspect of the present invention is a case where the common buffer memory is composed of a plurality of common buffer memories.

The cell exchange apparatus according to the invention of claim 4 monitors the number of cells held in the common buffer memory, and when the number exceeds a predetermined threshold value, determines that the cell is in a congested state.

A cell exchange apparatus according to a fifth aspect of the present invention includes a save buffer for writing a cell arriving at an incoming line, reading the written cell and outputting the read cell to a switch output line,
When it is determined that the cell is in the congested state, the evacuation buffer continues to hold the cell, and when it is not in the congested state, the evacuation buffer control circuit is provided for controlling the reading of the cell held in the evacuation buffer.

In the cell exchange apparatus according to the invention of claim 6, in the congestion judgment circuit, the threshold value for judging the congestion can be dynamically changed. Therefore, the control corresponding to the fluctuation of the input traffic is performed. Is made possible.

In the cell switching device according to the invention of claim 7, the threshold for judging congestion is when the congestion state is detected from a non-congested state and when the congestion state is detected from a non-congested state. , So that the congestion state has a hysteresis, the number of cells held in the common buffer memory fluctuates near the threshold, and the determination of the congestion state changes frequently,
It is designed to prevent unstable operation.

According to an eighth aspect of the present invention, there is provided a cell exchange apparatus, which stores or updates a past history of the number of cells held in the common buffer memory in the common buffer type switch by a predetermined number, and congests from the history. By making the judgment, the judgment of the sensitive congestion state is prevented from changing due to the instantaneous fluctuation.

A cell exchange apparatus according to a ninth aspect of the present invention comprises a circuit that bypasses the save buffer,
This is to reduce the cell delay time when the cell saving circuit is not in a congested state.

The cell switching apparatus according to the invention of claim 10 detects the priority of the delay of the input cell, divides the processing into a cell sensitive to the delay and a cell insensitive to the delay, and is sensitive to the delay. The cells are designed so that the delay time is reduced.

According to the eleventh aspect of the present invention, when the congestion determination circuit detects a congestion state, a control cell is mixed into the output line, and the cell retraction circuit extracts the control cell from the output line. Therefore, the number of signal lines between the congestion determination circuit and the cell save circuit is reduced in order to detect the congestion state.

[0025]

According to the present invention, the cell switching device detects a congestion state from the cell reservation state in the common buffer memory, notifies the cell evacuation circuit provided corresponding to the incoming line of the congestion state, Input to the common buffer type switch, and it is possible to reduce the cell discard rate caused by exceeding the capacity of the common buffer memory in the common buffer type switch without increasing the expensive common buffer memory. Realize a cell switching device.

In the cell exchanging device according to the second aspect of the present invention, even when one common buffer memory is prepared as a whole, the congestion determining circuit detects the congestion state and the cell saving circuit saves the cells. By doing so, the cell discard rate can be reduced.

In the cell exchanging device according to the third aspect of the present invention, even when a plurality of common buffer memories are prepared, the congestion determining circuit detects the congestion state and the cell saving circuit saves the cells. , The cell discard rate can be reduced.

In the cell exchange apparatus according to the present invention as set forth in claim 4, since the congestion determination circuit detects the congestion state by comparing the number of cells held in the common buffer memory with a predetermined threshold value, Congestion can be determined by a simple circuit.

According to the fifth aspect of the present invention, the cell switching device holds the cell when the cell saving circuit is in the congested state and outputs the reserved cell when the cell saving circuit is not in the congested state. Does not need to use an expensive memory, and the save buffer control circuit can hold cells without requiring special control.

In the cell exchange apparatus according to the invention of claim 6, the threshold value for determining the congestion of the congestion determination circuit can be dynamically changed. Therefore, the control corresponding to the fluctuation of the input traffic can be performed. Realize a possible cell switching device.

According to a seventh aspect of the present invention, there is provided a cell switching apparatus in which a threshold for judging congestion is when a congestion state is detected from a non-congested state and when a congestion state is detected from a non-congested state. Since a different value can be set with, the congestion status can be given a hysteresis, and the number of cells held in the common buffer memory fluctuates near the threshold, and even if the congestion status judgment changes frequently, it becomes unstable. To realize a cell switching device that is prevented from operating.

The cell switching apparatus according to the present invention stores or updates a past history of the number of cells held in the common buffer memory in the common buffer type switch by a predetermined number, and saves from the history. Therefore, a cell switching device is realized which prevents the determination of the sensitive congestion state from changing even if there is an instantaneous change.

Since the cell exchanging device according to the invention of claim 9 comprises a circuit that bypasses the save buffer, when the cell save circuit is not in a congested state, the delay time for writing or reading the cell to the save buffer is reduced. To realize the cell switching device.

The cell switching device according to the invention of claim 10 detects the priority of the delay of the input cell, divides the processing into the delay-sensitive cell and the insensitive cell, and detects the delay-sensitive cell. The cell bypasses the evacuation buffer and realizes a cell switching device in which the delay time is reduced.

According to the eleventh aspect of the present invention, when the congestion determination circuit detects a congestion state, a control cell is mixed into the output line, and the cell retraction circuit extracts the control cell from the output line. In order to detect the congestion state by this, a cell switching device is realized in which the number of signal lines between the congestion determination circuit and the cell saving circuit is reduced.

[0036]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are views showing an embodiment of the present invention. In the figure, the same reference numerals as those in FIG.

In FIG. 1, 1 ₁ to 1 _n are ATMs each consisting of a header portion including an outgoing line number as destination information and a data portion.
The n input lines 2 ₁ to 2 _m input by the cell are _m output lines to which the cell is output according to the destination specified in the header portion thereof, and these are the conventional output lines (FIG. 20). Is equivalent to

[0038] 3 ₁ to 3 _n, the switch input lines for transferring the cell input provided corresponding to the incoming line ₁ 1 to 1 _n the shared buffer switch, 4 ₁ to 4 _m is the output line 2 ₁ to 2 _m The switch output line provided by the cell output from the common buffer type switch, 9 is assigned to the outgoing line 2 ₁ to 2 _m based on the input information of the input cell, and the internal outgoing line 2 ₁ to It is a common buffer type switch that has a buffer memory that is shared by 2 _m and that is used to write cells in the buffer memory that need to wait and exchange cells.

Reference numeral 20 is a congestion determination circuit for determining whether or not the buffer memory of the common buffer type switch 9 is in a busy state, and 21 is a common buffer type switch 9.
Is a switch internal monitor that monitors the buffer memory of and notifies the congestion determination circuit. Reference numeral 31 is a congestion determination output line for notifying the cell saving circuits 22 _{1 to} 22 _n described later of the determination result of the congestion determination circuit.

Further, 22 _{1 to} 22 _n are incoming lines 1 ₁ to 1 _n
Is a cell evacuation circuit which is provided corresponding to the above and stores the cells input to the input lines 1 ₁ to 1 _n when the congestion determination circuit 20 determines the congestion state and suppresses the cell input to the common buffer type switch 9. The cell save circuit 22 includes a save buffer 23 and a save buffer control circuit 24. 23
₁ to 23 _n are evacuation buffers that are provided inside the cell evacuation circuits 22 _{1 to} 22 _n and actually store the input cells, and 24 _{1 to} 24 _n are also cell evacuation circuits 22 ₁ respectively.
To 22 _n , and save buffers 23 ₁ to 23
A save buffer control circuit that controls writing and reading of _n cells.

FIG. 2 shows in detail one embodiment of the common buffer type switch 9 in FIG. In FIG. 2, the subscript a such as 9a indicates that it is one form of the common buffer type switch of this embodiment. 3 _{1 to} 3 _n , 4
₁ to 4 _m , 9a and 21a are respectively 3 ₁ in FIG.
~3 _n, 4 ₁ ~4 _m, indicate the same parts and 9, 21.

10 ₁ to 10 _n are provided corresponding to each of the switch input lines, and the destination output lines 4 ₁ to 4 from the header portion of the cell input from the switch input lines 3 _{1 to} 3 _n.
It is a header processing circuit for detecting _m .

Reference numeral 11 is a common buffer memory which stores the cell at a designated address and can read the stored address by designating the address regardless of the order of writing. One common buffer memory 11 can store a plurality of cells.

Numeral 12 is provided so as to correspond to the common buffer memory 11, and manages an empty address by using, for example, a FIFO type memory, and gives a read address and a write address to the associated common buffer memory 11. This is an address management circuit.

Reference numeral 7 designates the header processing circuits 10 ₁ to 10 _n.
And the common buffer memory 11 are connected to each other, and the input cells are multiplexed in cell units or in predetermined bit units, and the high speed or multi-bit parallelization is performed to write all the cells input in the common buffer memory 11. It is a cell multiplexing circuit that enables it. 8 connects said shared buffer memory 11 and the switch output lines 4 ₁ to 4 _m, a cell read at a high speed or multi-bit parallel from the shared buffer memory,
It is a cell separation circuit that separates cells into cell units or predetermined bit units and distributes the cells to the switch output lines 4 ₁ to 4 _m .

The reference numeral 15a manages the address of the cell stored in the common buffer memory 11 for each destination of each cell and controls the reading of the common buffer memory 11 based on the address managed for each destination. The switch output lines 4 ₁ to 4 designated by the header of the cell
_This is a buffer control circuit that causes _m to output in a predetermined order.

Further, in the buffer control circuit 15a, 16a, when the cell to the switch input lines 3 ₁ to 3 _n arrives, the header processing circuits 10 ₁ ~ associated with the switch input lines 3 ₁ to 3 _n detected by 10 _n the outgoing line 2 ₁ to 2 _m or switch output line of the cell 4 ₁
4 _m number, the write address of the cell to the common buffer memory 11 from the empty address management circuit 12, and whether or not the cell has arrived at each of the switch input lines 3 _{1 to} 3 _n , its destination, It is a write buffer selection circuit that informs an address exchange circuit 17, which will be described later, in combination with a write address to the common buffer memory 11.

Reference numeral 17 denotes the write buffer selection circuit 1
6a of the detected outgoing lines 2 ₁ to 2 _m or switch output line 4
The destination switch output lines 4 ₁ to 4 _{m of} the arriving cells are divided by referring to the numbers ₁ to 4 _m , and the write addresses on the buffer memory 11 in which the cells are written are divided into address queues 18 ₁ to 18 described later. It is an address exchange circuit that writes to _m .

Reference numerals 18 ₁ to 18 _m are address queues thereof, which are constituted by FIFO (first in, first out) type memories, and are provided corresponding to the switch output lines 4 ₁ to 4 _m . This address queue 18
₁ ~ 18 _m, it is the switch output line 4 for each _one to 4 _m correlated, stored write address in the buffer memory 11 of the cell to the switch output lines 4 ₁ to 4 _m destined , The address exchange circuit 1 in the order of arrival
Written by 7.

19a designates this address queue 18 ₁ ...
A cell to be read from the buffer memory 11 is determined by referring to 18 _m , and a read buffer selection to be sent to the vacant address management circuit 12 corresponding to the buffer memory 11 using the addresses read from the address queues 18 ₁ to 18 _m as read addresses. Circuit.

Reference numeral 21a monitors the number of cells stored in the common buffer memory 11 to detect the congestion determination circuit 20.
It is a monitor inside the switch that notifies.

Next, the operation will be described. The cells described here have a fixed length and arrive as random or burst traffic. The cell input phase is adjusted before they are input to the input lines 1 ₁ to 1 _n , and the cell input from all the input lines is the same. Shall be supplied in phase.

First, the common buffer type switch 9 will be described. When the cells arrive at the switch input lines 3 _{1 to} 3 _n , the destination information written inside the header is read by the header processing circuits 10 ₁ to 10 _n and is notified to the write buffer selection circuit 16a inside the buffer control circuit 15a. It

The empty address management circuit 12 stores the unused empty addresses in the common buffer memory 11.
Hold. Although there are _n switch input lines 3 _{1 to} 3 _n , n
Since cells may arrive at all switch input lines of the book, the vacant address management circuit 12 can provide n vacant addresses to the write buffer selection circuit 16a.

The cells input to the switch input lines 3 _{1 to} 3 _n and then passing through the header processing circuits 10 ₁ to 10 _n are
It is input to the cell multiplexing circuit 7. The cell multiplexing circuit 7 performs high-speed processing so that the outputs of the plurality of header processing circuits 10 ₁ to 10 _n can be input to one common buffer memory 11. If the common buffer memory 11 has a low limit operation speed, it may be expanded into multiple bits and processed in parallel. There are various possible methods for multiplexing cells in the cell multiplexing circuit 7. For example, there is a method of arranging them in cell units to increase the speed. There is also a method such as a byte multiplexing method in which the data can be rearranged in a predetermined bit unit.

The cells multiplexed by the cell multiplexing circuit 7 are input to the common buffer memory 11 and written at the address designated by the vacant address management circuit 12. If no free address exists, this input cell is discarded.

The write buffer selection circuit 16a inside the buffer control circuit 15a is provided in the header processing circuit 10.
The presence or absence of cell arrival from ₁ to 10 _n and the number of the destination output line 2 ₁ to 2 _m or the destination switch output line 4 ₁ to 4 _m of the cell are received, and the common buffer memory 11 of the cell is received from the vacant address management circuit 12. Receive write address to. The destination and the write address to the common buffer memory 11 are paired and notified to the address exchange circuit 17 for each arrival cell.

The address exchange circuit 17 refers to the numbers of the destination output lines 2 ₁ to 2 _m or the destination switch output lines 4 ₁ to 4 _m detected by the write buffer selection circuit 16a,
The common buffer memory 11 in which the arrived cells are written
Write the above address to the destination switch output line 4 ₁ ~
Sort by 4 _m . Then, the write address is written to the address queues 18 ₁ to 18 _m .

Address queues 18 ₁ to 18 _m are provided corresponding to the switch output lines 4 ₁ to 4 _m , respectively.
Each is composed of a FIFO type memory. The address queues 18 ₁ to 18 _m are, for each switch output line 4 ₁ to 4 _m associated with the address queue 18 ₁ to 18 _m , the common buffer memory 11 in which cells having the switch output lines 4 ₁ to 4 _m as a destination are stored. You can create a queue of write addresses above.

Here, the address queues 18 ₁ to 18
_m is an example provided corresponding to each of the switch output lines 4 ₁ to 4 _m , but in the case of the common buffer type switch 9 that performs priority control according to the delay request class to be handled, one switch is provided. It is also possible to provide a plurality of address queues for the output lines 4 ₁ to 4 _m .

The write addresses queued in the address queues 18 ₁ to 18 _m wait for their turn.
Read buffer selecting circuit 19a includes, as with reference to the front row to determine the cell to be read out from the buffer memory 11, reads the address read from the address queue 18 ₁ ~ 18 _m addresses of the address queues 18 ₁ ~ 18 _m , To the free address management circuit 12 corresponding to the buffer memory 11.

The free address management circuit 12 receives the next address to be read from the read buffer selection circuit 19. Since the read address exists corresponding to each of the switch output lines 4 ₁ to 4 _m , a maximum of m read addresses are notified in one cell slot. In addition, the free address management circuit 12
Indicates the read address to the common buffer memory 11 and reads the cell. The cells read from the common buffer memory 11 are transmitted to the cell separation circuit 8. Further, the read address used for reading is released, stored in a circuit for accumulating a vacant address inside the vacant address management circuit 12, and circulated and used.

The cell separation circuit 8 includes the common buffer memory 1
A plurality of cells read out from 1 to a high speed to separate the switch output lines 4 ₁ to 4 _m corresponds. If the read signals are arranged in a predetermined bit unit like byte multiplexing, it also has a function of converting into a cell unit or another predetermined bit unit.

As described above, the common buffer type switch 9
a is a common buffer memory 11 that stores the input cells
To the switch output line 4 ₁ to 4 _m
Cells are exchanged by arranging them in units. Further, the used address can be circulated and used.

Next, the operation of the congestion determination circuit 20 will be described. The congestion determination circuit 20 monitors the number of cells accumulated in the common buffer memory 11 inside the common buffer type switch 9a by the switch internal monitor 21 and compares the number of cells with a preset threshold value to determine the congestion state. To judge.

FIG. 3 is a diagram showing a system in which the switch internal monitor 21 monitors the number of cells accumulated in the common buffer memory 11. In FIG. 3, (a), (b),
3C shows three methods. The method (a) shows a case where the switch internal monitor 21a counts the number of accumulated cells by the number of write pulses and the number of read pulses. The vacant address management circuit 12 gives a write pulse and a write address and a read pulse and a read address to the common buffer memory 11 when writing and reading a cell to and from the common buffer memory 11.
The write pulse and the read pulse are pulses indicating the timing of writing and reading, and by monitoring this pulse, the number of cells written in the common buffer memory 11 and the number of read cells can be known. it can. Therefore, it is possible to detect the cell accumulation number accumulated in the common buffer memory 11 by using the formula of cell accumulation number = write pulse number−read pulse number.

Next, the method (b) will be described. The free address management circuit manages free addresses. The cell storage number may be calculated from the number of free addresses. That is, assuming that the number that can be stored in the common buffer memory 11 is the total number of storages and the number of free addresses is the number of storages, the number of cells stored in the common buffer memory 11 is calculated by the formula It is possible to detect the accumulated number of.

Next, the method (c) will be described. In the methods (a) and (b), the case where the number of accumulated cells is directly calculated has been described. However, in the method (c), is there a cell for each address of the common buffer memory? It has a flag indicating whether or not it outputs this flag sequence. The position of this flag may be inside the common buffer memory 11 or inside the free address management circuit 12. In the example shown in FIG. 3, when the common buffer memory 11 can store a total of 12 cells, 6 addresses are already occupied by the cells, and the remaining 6 are empty. ing. This flag is transmitted to the congestion determination circuit 20, and the congestion determination circuit 20 can detect the cell accumulation number by counting the number of times the flag is turned on.

4 and 5 show the procedure of the congestion judgment circuit 20. The threshold value T used for congestion determination is
Set at the initial stage. As shown in FIG. 5, the procedure of the congestion determination circuit 20 shown in FIG. 4 reads the cell accumulation number in the common buffer type switch 9a from the switch internal monitor for each cell slot unit and compares it with the threshold value set previously. By doing so, the congestion state is determined.

Next, the operation of the cell save circuit 22 will be described. The cell save circuit 22 includes a save buffer 23 and a save buffer control circuit 24. Evacuation buffer 2
3 can be constituted by a FIFO (first in first out) type memory, for example. The save buffer control circuit 24 is a circuit that controls writing and reading of the save buffer 23. When the save buffer 23 is a FIFO type memory, the save buffer control circuit 24 generates a write pulse and a read pulse.

Separately, the save buffer 23 is a RAM
In the case of (random access type memory), the save buffer control circuit 24 manages the write address and the read address, and controls the use of the addresses by circulating them. That is, when the cell is written, 1 is added to the write address, and when the cell is read, 1 is added to the read address. In this case, the save buffer control circuit 24 gives the write address and write pulse, and the read address and read pulse to the save buffer 23.

FIG. 6 is a flow chart of the cell save circuit 22, and mainly shows the control procedure of the save buffer control circuit 24. When the cell arrives at the incoming line 1, the save buffer control circuit 24 controls the writing of the cell in the internal save buffer 23. However, if the save buffer 23 is full, the input cell is discarded. On the other hand, the save buffer control circuit 24 monitors the congestion determination circuit 20, and if it is not in a busy state, reads the cells accumulated in the save buffer 23. If it is in a congested state, the cell is not read from the save buffer 23.

FIG. 7 is a diagram showing a specific operation of the save buffer. Figure 7 shows the operation of the save buffer when the cell A, the cell C, the cell E, cell H is input to the input line 1 ₁ shown in FIG. Here, cell slot 1
In the cell slot 4, the congestion determination circuit 20 determines that the congestion state is not in the congestion state, and in the cell slots 2 and 3, the congestion state is detected. First, in cell slot 1, cell A is stored in the save buffer.

Next, in cell slot 2, cell A
Is output from the save buffer and the cell C is accumulated. In the cell slot 1, since the congestion determination circuit detects that the congestion state is not congested, cell A is output from the save buffer.

Next, in the cell slot 3, since the congestion determination circuit 20 detects the congestion state in the cell slot 2, the cell C remains stored in the save buffer. In the cell slot 3, the cell E is input and stored in the save buffer.

Next, in cell slot 4, since congestion determination circuit 20 detects a congestion state in cell slot 3, cells C and E remain stored in the save buffer. Further, the cell H is newly stored in the cell slot 4.

Next, in the cell slot 5, since the case where the congestion determination circuit 20 is not in the congestion state is detected in the cell slot 4, the cell C is output from the save buffer.

As described above, the feature of this embodiment is that the cell evacuation circuit is provided for the common buffer type switch 9 to reduce the cell discard rate of the common buffer memory in the common buffer type switch. That is the point. In particular, the cell evacuation circuit only needs to control the accumulation of cells according to the congestion status report from the congestion judgment circuit, and the cell evacuation circuit can be configured easily.

In the case of the conventional example 2 described in the prior art,
A buffer is provided corresponding to the outgoing line. A circuit for temporarily accumulating cells is provided for each so-called output buffer type switch, and it is determined whether the output buffer corresponding to the output line is in a congested state, and whether or not the cell corresponds to that output buffer. After judging
It was necessary to determine whether or not cells should be accumulated in advance, and a complicated configuration had to be taken. On the other hand, in the case of the common buffer type switch as shown in this embodiment, since one common buffer is provided for the output line, it is simple to determine whether or not the common buffer causes a congestion state. Based on good judgment, and
The cell evacuation circuit controls the accumulation of cells without individually deciding the destination of the arriving cells.

Next, FIG. 8 is a diagram showing an example of a mounting form of the cell exchange apparatus shown in FIG. In FIG. 8, 100
Is a common buffer type switch 9 and a congestion determination circuit 20.
It is a common buffer type switch board equipped with. 200
₁ to 200 _n are interface boards. Each interface board is provided corresponding to one incoming line and one outgoing line, and is equipped with an interface circuit for connecting this pair of incoming line and outgoing line to the common buffer type switch 9. For example, when the incoming line and outgoing line are composed of optical fibers, a photoelectric conversion circuit and an electro-optical conversion circuit are mounted. In addition, an interface circuit is provided for synchronization and error checking. Further, the above-mentioned cell save circuit is provided on the incoming line side. Each interface board and the common buffer type switch board are connected by a switch input line and a switch output line. Further, the congestion determination output line 31 from the congestion determination circuit 20 is connected to each of the interface boards 200 ₁ to 2 2 from the common buffer type switch board 100.
00 _n cell save circuit.

Example 2. Next, another embodiment of the present invention will be described with reference to the drawings. 1 and 9 are block diagrams showing the configuration of a cell exchange apparatus according to an embodiment of the present invention. In the figure, the same or corresponding parts as those of the cell switching apparatus (FIGS. 1 and 2) according to the first embodiment described above are designated by the same reference numerals.

In FIG. 1, 1 ₁ to 1 _n are ATs each consisting of a header section including an outgoing line number as destination information and a data section.
N number of incoming lines which are M cells enter, 2 ₁ to 2 _m, the cell is a m number of outgoing lines is output in accordance with a specified destination by the header portion.

[0083] 3 ₁ to 3 _n, the switch input lines for transferring the cell input provided corresponding to the incoming line ₁ 1 to 1 _n the shared buffer switch, 4 ₁ to 4 _m is the output line 2 ₁ to 2 A switch output line which is provided corresponding to _m and which is output from the cell from the common buffer type switch, 9 is a cell which is distributed to the outgoing lines 2 ₁ to 2 _m based on the input information of the input cell, and is internally output to the outgoing line 2 ₁ It is a common buffer type switch that has a buffer memory that is commonly used for up to 2 _m , and that a cell that needs to wait is written in the buffer memory and the cell is exchanged.

Reference numeral 20 is a congestion determination circuit for determining whether the buffer memory of the common buffer type switch 9 is in a busy state or not, and 21 monitors the buffer memory of the common buffer type switch 9 and notifies the congestion determination circuit. It is a monitor inside the switch. Reference numeral 31 denotes the judgment result of the congestion judgment circuit, which will be described later in cell saving circuits 22 _{1 to} 22 _n.
This is a congestion judgment output line for notifying to.

Further, 22 _{1 to} 22 _n are incoming lines 1 ₁ to 1 _n
Is a cell evacuation circuit which is provided corresponding to the above and stores the cells input to the input lines 1 ₁ to 1 _n when the congestion determination circuit 20 determines the congestion state and suppresses the cell input to the common buffer type switch 9. The cell save circuit 22 includes a save buffer 23 and a save buffer control 24. 23 ₁ ~
23 _n is a save buffer provided inside each of the cell save circuits 22 _{1 to} 22 _n for actually storing the input cells, and 24 _{1 to} 24 _n are also provided to the cell save circuits 22 ₁ to 22 _n, respectively.
22 _n provided inside the save buffers 23 ₁ to 23 _n
Is a save buffer control circuit for controlling writing and reading of the cell.

FIG. 9 is a diagram showing in detail one embodiment of the common buffer type switch 9 in FIG. In FIG. 9, the subscript b such as 9b indicates that it is one form of the common buffer type switch of this embodiment. 3 _{1 to} 3 _n , 4
₁ to 4 _m , 9b and 21b are respectively 3 ₁ in FIG.
~3 _n, 4 ₁ ~4 _m, indicate the same parts and 9, 21.

10 ₁ to 10 _n are provided corresponding to each of the switch input lines, and the destination output lines 4 ₁ to 4 from the header portion of the cell input from the switch input lines 3 _{1 to} 3 _n.
It is a header processing circuit for detecting _m .

Further, 11 _{1 to} 11 _p are _p cells capable of reading the stored addresses regardless of the order of writing by designating the addresses by accumulating the cells at the designated addresses. In this common buffer memory, even _{one of the} common buffer memories 11 _{1 to} 11 _p can store a plurality of cells.

12 _{1 to} 12 _p are provided corresponding to each of the common buffer memories 11 _{1 to} 11 _p , for example, F
This is a free address management circuit which manages free addresses using an IFO type memory and gives read addresses and write addresses to the associated buffer memories 11 _{1 to} 11 _p .

Reference numeral 13 denotes the header processing circuits 10 ₁ to 10
_An input line side crosspoint switch for selectively connecting _n to predetermined common buffer memories 11 _{1 to} 11 _p . 14
Is an output line side cross point switch for selectively connecting the common buffer memories 11 _{1 to} 11 _p to predetermined switch output lines 4 ₁ to 4 _m .

Numeral 15b controls the switching of the input side cross point switch to select the common buffer memories 11 _{1 to} 11 _p in which cells are accumulated, and the accumulation is performed in the common buffer memories 11 _{1 to} 11 _p . The cell address is managed for each cell destination, and the common buffer memory 11 ₁ is based on the address managed for each destination.
It is a buffer control circuit that controls reading of ˜11 _p and outputs the cells to the switch output lines 4 ₁ to 4 _m designated by the header part thereof in a predetermined order.

Further, in the buffer control circuit 15b, when the cells arrive at the switch input lines 3 _{1 to} 3 _n , the 16b receives the header processing circuits 10 ₁ to 10 ₁ ~ associated with the switch input lines 3 _{1 to} 3 _n. Outgoing lines 2 ₁ to 2 _{m of} the cell detected by 10 _n or switch output line 4 ₁
Receiving a number of to 4 _m, the shared buffer memory 11 ₁ to 11 for it by selecting the _p connecting to the header processing circuit 10 ₁ to 10 _n to the previous entry line side cross-point switch 13 for storing the cell Is a write buffer selection circuit for controlling the switching of the. In addition, the write buffer selection circuit 16b includes free address management circuits 12 ₁ to ₁ 1.
Receiving a write address for the shared buffer memory 11 ₁ to 11 _p than 2 _p. And each switch input line 3 ₁ ~
The presence / absence of a cell at 3 _n , its destination, the numbers of the common buffer memories 11 _{1 to} 11 _p and its write address are combined to notify the address exchange circuit 17 described later.

Reference numeral 17 denotes the write buffer selection circuit 1
6b of the detected outgoing lines 2 ₁ to 2 _m or switch output line 4
_The cell output destinations of the arriving cells are referred to by the numbers ₁ to 4 _{m and} are divided by the switch output lines 4 ₁ to 4 _m , and the numbers of the buffer memories 11 _{1 to} 11 _{p in} which the cells are written and the write addresses are described later. This is an address exchange circuit for writing in the queues 18 ₁ to 18 _m .

Numerals 18 ₁ to 18 _m are address queues thereof, which are constituted by FIFO (first in, first out) type memories and are provided corresponding to the respective switch output lines 4 ₁ to 4 _m . This address queue 18
_1-18 The _m, it to the switch output line 4 for each _one to 4 _m correlated, stored the buffer memory 11 ₁ to 11 _p of cells the switch output lines 4 ₁ to 4 _m and destination
And the write addresses thereof are written by the address exchange circuit 17 in the order of arrival.

19b indicates the address queues 18 ₁ ...
18 _m , the cells to be read from the buffer memories 11 _{1 to} 11 _p are determined, and their address queues 18 ₁ to ₁ 1 are determined.
The address read from 8 _m is sent as a read address to the empty address management circuits 12 _{1 to} 12 _p associated with the corresponding buffer memories 11 _{1 to} 11 _p, and the switching of the output side crosspoint switch 14 is controlled. The common buffer memories 11 _{1 to} 11 _p
The a read buffer selection circuit connected to the switch output line 4 ₁ to 4 _m to be appropriate.

Reference numeral 21b is a common buffer memory 11 ₁ to ₁ 1.
It is a switch internal monitor that monitors the total number of accumulated cells of 1 _p and notifies the congestion determination circuit 20.

Next, the operation will be described. The cells described here have a fixed length and arrive as random or burst traffic. The cell input phase is adjusted before they are input to the input lines 1 ₁ to 1 _n , and the cell input from all the input lines is the same. Shall be supplied in phase.

First, the common buffer type switch 9 will be described. When the cells arrive at the switch input lines 3 _{1 to} 3 _n , the destination information written in the header of the cells is read by the header processing circuits 10 ₁ to 10 _n and notified to the write buffer selection circuit 16b in the buffer control circuit 15b. It

The empty address management circuits 12 _{1 to} 12 _p are
Stores and holds unused free addresses in the common buffer memories 11 _{1 to} 11 _p . Switch input line 3 ₁ ~
Although there are 3 _n in 3 _n , cells may arrive at all n switch input lines.
_{1 to} 12 _p can provide a total of n free addresses to the write buffer selection circuit 16b.

The cells input to the switch input lines 3 _{1 to} 3 _n and then passing through the header processing circuits 10 ₁ to 10 _n are
It is input to the incoming line side cross point switch 13. The input side cross point switch 13 changes the switching in cell slot units according to the instruction of the write buffer selection circuit 16b, and the header processing circuit 10 in cell units.
₁ to 10 _n are assigned to a predetermined common buffer memory 11 _{1 to} 11 _p
Selectively connect to.

[0102] The connected cells in the shared buffer memory 11 ₁ to 11 _p by the entering line side cross-point switch 13 are input to a common buffer memory 11 ₁ to 11 _p, a free address management circuit 12 ₁ to 12 _p It is written to the specified address. If no free address exists, this input cell is discarded.

The write buffer selection circuit 16b in the buffer control circuit 15b is provided in the header processing circuit 10.
_{From 1} to 10 _n, the presence or absence of cell arrival and the number of the destination outgoing line 2 ₁ to 2 _m or the destination switch output line 4 ₁ to 4 _m of the relevant cell are received, and the vacant address management circuits 12 _{1 to} 12 _p receive the number of the relevant cell. It receives write addresses to the common buffer memories 11 _{1 to} 11 _p . The destination and the common buffer memory 11 are delivered to the address exchange circuit 17 in units of arrival cells.
The number of _{1 to} 11 _p and its write address are combined and notified.

The buffer control circuit 15b also controls the switching of the incoming line side cross point switch 13,
The header processing circuits 10 ₁ to 10 _n where the cells have arrived and the common buffer memories 11 ₁ to ₁ 1 selected to store the cells
Instruct to connect 1 _p individually.

Here, the input side cross point switch 1
There are various conceivable ways of connecting the cells 3, but when the cells are stored in the common buffer memories 11 _{1 to} 11 _p and read later, it is possible that there are two or more cells to be read in the same buffer memory 11 _{1 to} 11 _p . Since it is not desirable, a large number of common buffer memories 11 ₁ to 11
It is preferable to disperse into 11 _p .

To this end, the buffer memories 11 ₁ to ₁ 1
It is not enough for 1 _{p to} have the same number as the switch input lines 3 _{1 to} 3 _n, and in order to solve the above problem, it is easier to control if there are as many common buffer memories 11 _{1 to} 11 _p as possible. .

Alternatively, as a method of distributing cells to a large number of common buffer memories 11 _{1 to} 11 _p , there is a method of selecting cells in order. N in a cell slot
If x cells of the switch input lines 3 _{1 to} 3 _n of the book arrive at the same time, the common buffer memories 11 _{1 to} 11
_{If x} is selected and y cells arrive in the next cell slot, the common buffer memories 11 _{x + 1 to} 11 _{x + y} are selected.

Further, as still another method, the remaining cell retention amount in each of the common buffer memories 11 _{1 to} 11 _p is recorded,
Common buffer memory 11 ₁ ~
A method of writing cells by selecting 11 _p is also conceivable. That is, when x cells arrive at a certain cell slot at the same time, the x common buffer memories 11 _{1 to} 11 _p with the smallest cell reservation remaining amount are selected. Thereby, the plurality of common buffer memories 11 _{1 to} 11 _p can be regarded as one large common buffer memory.

The address exchange circuit 17 refers to the number of the destination output lines 2 ₁ to 2 _m or the destination switch output lines 4 ₁ to 4 _m detected by the write buffer selection circuit 16b,
Buffer memory 11 _{1 in} which the arrived cells are written
The number and the write address of 11 _p, distributes separately switch output lines 4 ₁ to 4 _m of the destination. Then, they are written in the address queues 18 ₁ to 18 _m .

Address queues 18 ₁ to 18 _m are provided corresponding to the switch output lines 4 ₁ to 4 _m , respectively.
Each is composed of a FIFO type memory. The address queue 18 ₁ ~ 18 _m, it is the switch output line 4 for each _one to 4 _m associated buffer memories 11 ₁ stored in the cell to the switch output lines 4 ₁ to 4 _m and destination ~11 _p and the queue of the write address can be made.

Here, the address queues 18 ₁ to 18
_m is an example provided corresponding to each of the switch output lines 4 ₁ to 4 _m , but in the case of the common buffer type switch 9 that performs priority control according to the delay request class to be handled, one switch is provided. It is also possible to provide a plurality of address queues for the output lines 4 ₁ to 4 _m .

The write addresses queued in the address queues 18 ₁ to 18 _m wait for their turn.
Read buffer selecting circuit 19b refers to the front row to determine the cell to be read out from the buffer memory 11 ₁ to 11 _p, read from the address queue 18 ₁ ~ 18 _m addresses of the address queues 18 ₁ ~ 18 _m As a read address, the buffer memories 11 _{1 to} 11 _p
Sent to the empty address management circuit 12 ₁ to 12 _p corresponding to.

Further, the read buffer selection circuit 19b
Outputs the cross-point switch 14 on the output line side so that the cells read from the common buffer memories 11 _{1 to} 11 _p are output to the switch output lines 4 ₁ to 4 _m , which are predetermined destinations.
Control the switching of. This switching indicates the individual connection form of the common buffer memories 11 _{1 to} 11 _p and the switch output lines 4 ₁ to 4 _m in cell slot units.

The empty address management circuits 12 _{1 to} 12 _p are
The address to be read next is received from the read buffer selection circuit 19. The read address is the switch output line 4
_Since each cell exists corresponding to ₁ to 4 _m, a maximum of m notifications is made in one cell slot. The free address management circuits 12 _{1 to} 12 _p are connected to the common buffer memory 11
_The read address is designated to _{1 to} 11 _p to read the cell. The cells read from the common buffer memories 11 _{1 to} 11 _p are the output side cross point switch 14
Sent to. In addition, the read address used for reading is released, and the empty address management circuits 12 ₁ to 12 ₁
Stored in the circuit for storing the 2 _p vacant addresses of the internal, it is used circulating.

As described above, the common buffer type switch 9
b is the number of common buffer memories 11 ₁
Write to to 11 _p, the switch output line 4 the address
Cells are exchanged by arranging them in units of ₁ to 4 _m .
Further, the used address can be circulated and used.

Next, the operation of the congestion determination circuit 20 will be described. The congestion determination circuit 20 monitors the number of cells accumulated in the common buffer memory 11 inside the common buffer type switch 9b by the switch internal monitor 21, and compares the number of cells with a preset threshold value. Determine the state.

4 and 5 show the procedure of the congestion determination circuit 20. The threshold value T used for congestion determination is
Set at the initial stage. For each cell slot, the number of cells accumulated in the common buffer type switch 9b is read from the switch internal monitor, and the congestion state is determined by comparing with the previously set threshold value.

Here, the difference from the above-described first embodiment is that
The common buffer memory is composed of a plurality of memories. Therefore, the number of cells accumulated in each common buffer memory is given to the switch internal monitor 21b. The cell saving circuit detects the total cell accumulation number by adding the cell accumulation numbers sent from the respective common buffer memories. As a method of detecting the number of cells accumulated in each common buffer memory, the method shown in FIG. 3 can be considered. Alternatively, the buffer control circuit 1
The cell storage number may be calculated using the buffer selection times of the write buffer selection circuit 16b and the read buffer selection circuit 19b within 5b. That is, the write buffer selection circuit 16b selects a common buffer memory for accumulating cells, and a cell is recorded in any one of the common buffer memories every time the common buffer memory is selected. Therefore, it is possible to know the number of cells input to the common buffer by counting the number of times the write buffer selection circuit selects the common buffer memory. Similarly, the read buffer selection circuit 19b
The number of cells output from the common buffer memory can be detected by counting the number of times the common buffer memory is selected. Therefore, the cell accumulation number may be calculated and given to the switch internal monitor 21b by a calculation formula of cell accumulation number = common buffer memory selection number of write buffer selection circuit−common buffer memory selection number of read buffer selection circuit. Absent.

Next, the operation of the cell save circuit 22 will be described. The cell save circuit 22 includes a save buffer 23 and a save buffer control 24. Evacuation buffer 23
Can be constituted by, for example, a FIFO (first in first out) type memory. The save buffer control 24 is a circuit that controls writing and reading of the save buffer 23. When the save buffer 23 is a FIFO type memory, the save buffer control circuit 24 generates a write pulse and a read pulse.

Separately, the save buffer 23 is a RAM
In the case of (random access type memory), the save buffer control circuit 24 manages the write address and the read address, and controls the use of the addresses by circulating them. That is, when the cell is written, 1 is added to the write address, and when the cell is read, 1 is added to the read address. In this case, the save buffer control circuit 24 gives the write address and write pulse, and the read address and read pulse to the save buffer 23.

Here, FIG. 6 is a flow chart of the cell save circuit 22, and mainly shows the control procedure of the save buffer control circuit 24. When the cell arrives at the incoming line 1, the save buffer control circuit 24 controls the writing of the cell in the internal save buffer 23. However, if the save buffer 23 is full, the input cell is discarded. On the other hand, the save buffer control 24 monitors the congestion determination circuit 20, and reads the cells accumulated in the save buffer 23 if not in the congestion state. If it is in a congested state, the cell is not read from the save buffer 23.

As described above, in this embodiment, even when the common buffer memory is composed of a plurality of memories, the cell save circuit is provided as in the first embodiment.
The cell discard rate in the common buffer memory can be reduced. Although there are a plurality of common buffer memories, they do not correspond to the outgoing lines, and the cell saving circuit does not need to perform complicated control of saving the arriving cells for each outgoing line. That is, even if the common buffer memory is composed of a plurality of memories, the congestion determination circuit determines whether or not a congestion state has occurred in the plurality of common buffer memories as a whole, and the cell evacuation circuit based on the determination result. It is possible to adopt a simple configuration in which the storage control is performed on the cells that have arrived.

Example 3. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a flow chart showing the procedure of the congestion determination circuit 20 of the cell switching apparatus according to the embodiment of the present invention. The cell exchange apparatus according to the first embodiment described above (FIGS. 1, 2, 2 and 4), and the second embodiment described above.
The same or corresponding parts as those of the cell switching device (FIGS. 1, 4, 4, 6 and 9) according to FIG.

FIG. 10 illustrates the operation of the congestion determination circuit 20. The congestion determination circuit 20 monitors the number of cells accumulated in the common buffer memory 11 inside the common buffer type switch 9 by the switch internal monitor 21, and compares the number of cells with a preset threshold value. Determine the state.

In the figure, it is shown that the threshold value T is reset for each cell slot. As a result, it is possible to quickly respond to a change in congestion determination conditions in response to changes in call settings and system conditions. For example, if a line fails and a route cannot be used,
A method of transferring cells using another line is generally used, but in such a case, cells may be concentrated on a line to be bypassed as compared with the normal case. In such a case, by setting the threshold value T to a large value, even if it is determined that the congestion state is normally caused,
Congestion may be deliberately not considered as congestion. Alternatively, as another example, when inspecting a specific line or inspecting the capability of a specific switching device, there is a case in which it is desired to perform an inspection or an investigation without intentionally evacuating cells. In such a case, it is possible to reduce the chances of determining a congested state by setting the threshold value T large or setting it to the maximum value. By setting the threshold value T to the maximum value, that is, by setting the threshold value T to the maximum storage number that can be stored in the common buffer memory, the cell is not saved until the common buffer memory becomes full. be able to.

Example 4. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a flow chart showing the procedure of the congestion determination circuit 20 of the cell exchange apparatus according to the embodiment of the present invention. The cell exchange apparatus according to the first embodiment described above (FIGS. 1, 2, 2 and 4), and the second embodiment described above.
The same or corresponding parts as those of the cell switching device (FIGS. 1, 4, 4, 6 and 9) according to FIG.

FIG. 11 illustrates the operation of the congestion determination circuit 20. The congestion determination circuit 20 monitors the number of cells accumulated in the common buffer memory 11 inside the common buffer type switch 9 by the switch internal monitor 21, and compares the number of cells with a preset threshold value. Determine the state.

If the accumulated number frequently fluctuates near the set threshold, the congestion state determination becomes unstable. Therefore, the threshold for determining the congestion state and the threshold for determining the non-congestion state are set. To provide. At this time, 2
By setting three threshold values and providing hysteresis, stable congestion judgment can be obtained.

Example 5. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a detailed block diagram of the congestion judgment circuit 20 of the cell exchange apparatus according to one embodiment of the present invention, and FIG. 13 is a flow chart showing its operation procedure. Same as or equivalent to the cell switching apparatus according to the first embodiment (FIGS. 1, 2, 2, 4 and 6) and the cell switching apparatus according to the second embodiment (FIGS. 1, 4, 6, and 9) described above. The same reference numerals are given to the parts, and the description will be omitted.

In FIG. 12, 20 is a congestion determination circuit, 21 is a switch internal monitor for notifying the number of cells stored therein from the common buffer type switch 9, and 31 is for notifying the cell saving circuit 22 of the congestion state. Congestion judgment output line. Reference numerals 32 to 34 are blocks inside the congestion determination circuit 20, 32 is a history storage pool capable of storing the number of past cell accumulations up to k cell slots before, 33
Performs a predetermined operation from the information of the history storage pool,
A history calculation circuit for calculating a cell accumulation index, and 34 is a comparison circuit for comparing the cell accumulation index output from the history calculation circuit with a preset threshold value.

FIG. 13 illustrates the operation of the congestion determination circuit 20. For more stable and reliable determination, the feature is that the past few slots of history are retained and the congestion state is determined when the specified standard is exceeded. The congestion determination circuit 20 includes a switch internal monitor 21.
The number of cells accumulated in the common buffer memory 11 inside the common buffer type switch 9 is monitored by. In the initial state, the congestion judgment threshold value T and the history storage slot number k are set.

The history storage pool 32 holds the number of accumulated cells in the past k cell slots. This is F
It can be realized with an IFO-based memory. Past k
The history calculation circuit 33 calculates the cell accumulation index using the information for the cell slots.

Various methods can be considered for the history calculation circuit 33 to calculate the cell accumulation index. For example, there is a method of simply averaging the past k cell slots. The larger the value of k, the more stable the determination. It is also possible to consider that the number of accumulated cells rapidly increases, that is, a method of weighting the rate of increase in the number of accumulated cells. Further, the congestion state may be determined by another method when the increase pattern of the number of cells accumulated in the past several cell slots matches the preset pattern.
Alternatively, there is also a method of comparing the cell accumulation number of the k cell slot with a preset reference value of the cell accumulation number and calculating the cell accumulation index depending on how many of k exceed the reference value.

The calculated cell accumulation index is compared with the comparison circuit 34.
Thus, the size is compared with a preset threshold value T, and the congestion state is determined. The congestion state is notified to the cell saving circuit 22 through the congestion determination output line 31.

Example 6. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 14 is a block diagram of a cell exchange apparatus according to an embodiment of the present invention, and FIG. 15 is a flow chart showing an operation procedure of the cell save circuit 22. The cell exchange device according to the first embodiment (FIGS. 1, 2, 2 and 4),
Also, the same or corresponding parts as those of the cell exchange apparatus according to the second embodiment (FIG. 1, FIG. 4, FIG. 6, FIG. 9) described above are designated by the same reference numerals, and description thereof will be omitted.

[0135] In FIG. 14, 25 ₁ to 25 _n is retracted according to switching instruction buffer control circuit 24 ₁ to 24 _n, the incoming line ₁ 1 to 1 _n below the cell inputted from the bypass link 27 ₁ ~ 27 _n or retracted buffer 23 _1-23
It is an evacuation input selector that distributes to _n . 26 ₁ ~ 2
6 _n according switching instruction saving buffer control circuit 24 ₁ to 24 _n, the bypass link 27 ₁ ~ 27 _n below
Or select either of the save buffer 23 ₁ ~ 23 _n, a retraction output selector connected to the switch input lines 3 ₁ to 3 _n.

Next, the operation will be described. Here, FIG. 15 illustrates the operation of the cell save circuits 22 _{1 to} 22 _n using a flowchart. Cell saving circuit 22 _{1 to} 22
_n monitors the presence / absence of congestion determination of the congestion determination circuit 20 through the congestion determination output line 31. If it is congested, the save input selector 25 ₁
To 25 _n are incoming lines ₁ 1 to 1 _n the save buffer 23 ₁ ~ 23 _n in accordance with an instruction of the save buffer control circuit 24 ₁ to 24 _n
To the save buffers 23 ₁ to 23 _n.
To hold.

On the other hand, when not in the congested state, the cell saving circuits 22 _{1 to} 22 _n can output the cells to the common buffer type switch 9. Therefore, the FIFO rule, that is, the cell that arrives earliest in time is output. If cells have been accumulated in the save buffers 23 ₁ to 23 _n , the save input selectors 25 _{1 to} 25 _n input the lines according to the instructions of the save buffer control circuits 24 _{1 to} 24 _n in order to output from the cells. 1 ₁ to 1 _n and the connection to the saving buffer 23 ₁ ~ 23 _n, and at the same time held the inputted cell to the save buffer 23 ₁ ~ 23 _n, output selector 26 ₁ ~ 26 _n for saving, like saving buffer control circuit The save buffers 23 ₁ to 23 in accordance with the instructions of 24 _{1 to} 24 _n
n is connected to the switch input lines 3 _{1 to} 3 _n , and the cells are output from the save buffers 23 ₁ to 23 _n . If no cells are stored in the save buffers 23 ₁ to 23 _n , the save input selectors 25 _{1 to} 25 _n and the save output selectors 26 _{1 to} 26 _n are connected in the reverse connection form to the above. That is, it is connected to the bypass links 27 _{1 to} 27 _n side and outputs the input cells directly to the switch input lines 3 _{1 to} 3 _n .

Example 7. Next, another embodiment of the present invention will be described with reference to the drawings. 16 is a block diagram of a cell exchange apparatus according to an embodiment of the present invention, and FIG. 17 is a flow chart showing an operation procedure of the cell save circuit 22. The cell exchange device according to the first embodiment (FIGS. 1, 2, 2 and 4),
Also, the same or corresponding parts as those of the cell exchange apparatus according to the second embodiment (FIG. 1, FIG. 4, FIG. 6, FIG. 9) described above are designated by the same reference numerals, and description thereof will be omitted.

[0139] In FIG. 16, 25 ₁ to 25 _n is retracted according to switching instruction buffer control circuit 24 ₁ to 24 _n, the incoming line ₁ 1 to 1 _n below the cell inputted from the bypass link 27 ₁ ~ 27 _n or retracted buffer 23 _1-23
It is an evacuation input selector that distributes to _n . 26 ₁ ~ 2
6 _n according switching instruction saving buffer control circuit 24 ₁ to 24 _n, the bypass link 27 ₁ ~ 27 _n below
Or select either of the save buffer 23 ₁ ~ 23 _n, a retraction output selector connected to the switch input lines 3 ₁ to 3 _n. Numerals 28 _{1 to} 28 _n are priority cell discrimination circuits which read a code or the like indicating the priority such as delay in the header of the input cell and notify the save buffer control circuits 24 _{1 to} 24 _n of the priority. .

Next, the operation will be described. Here, FIG. 17 illustrates the operation of the cell save circuits 22 _{1 to} 22 _n using a flowchart. In the present embodiment, the priority of cell delay is two classes, and will be referred to as a delay sensitive cell and a delay insensitive cell hereinafter. However, this priority may be two or more classes.

The priority cell discriminating circuits 28 _{1 to} 28 _n monitor the headers of the arriving cells and detect the priorities relating to delays and the like added to the headers of the cells. The priority may be directly given in the bit format in the header or may be determined by VPI / VCI (channel identifier etc.), but one cell always belongs to one of the priority classes. .

When the arriving cells identified by the priority cell discriminating circuits 28 _{1 to} 28 _n are delay sensitive cells, the cell evacuation circuits 22 _{1 to} 22 _n are detected even if the congestion determining circuit 20 detects the congestion state. Outputs the arrival cell as it is.

On the contrary, when the priority cell discrimination circuits 28 _{1 to} 28 _n detect delay insensitive cells, the cell saving circuits 22 ₁ to 22 ₁ to
22 _n is processed differently depending on the presence / absence of congestion determination by the congestion determination circuit 20. If it is in a congested state, the evacuation input selectors 25 _{1 to} 25 _n follow the instructions of the evacuation buffer control circuits 24 _{1 to} 24 _{n to} input lines 1 ₁ to 1 respectively.
_n is connected to the save buffers 23 ₁ to 23 _n , and the input cells are held in the save buffers 23 ₁ to 23 _n .

On the other hand, when not in the congested state, the cell saving circuits 22 _{1 to} 22 _n can output the cells to the common buffer type switch 9. Therefore, the FIFO rule, that is, the cell that arrives earliest in time is output. If cells have been accumulated in the save buffers 23 ₁ to 23 _n , the save input selectors 25 _{1 to} 25 _n input the lines according to the instructions of the save buffer control circuits 24 _{1 to} 24 _n in order to output from the cells. 1 ₁ to 1 _n and the connection to the saving buffer 23 ₁ ~ 23 _n, and at the same time held the inputted cell to the save buffer 23 ₁ ~ 23 _n, output selector 26 ₁ ~ 26 _n for saving, like saving buffer control circuit The save buffers 23 ₁ to 2 according to the instructions of 24 _{1 to} 24 _n
3 _n are connected to the switch input lines 3 _{1 to} 3 _n to output the cells from the save buffers 23 ₁ to 23 _n . If no cells are stored in the save buffers 23 ₁ to 23 _n , the save input selectors 25 _{1 to} 25 _n and the save output selectors 26 _{1 to} 26 _n are connected in the reverse connection form to the above. That is, it is connected to the bypass links 27 _{1 to} 27 _n side and outputs the input cells directly to the switch input lines 3 _{1 to} 3 _n .

Example 8. Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 18 is a block diagram of a cell exchange apparatus according to an embodiment of the present invention. The cell exchange device according to the first embodiment (FIGS. 1, 2, 2 and 4),
Also, the same or corresponding parts as those of the cell exchange apparatus according to the second embodiment (FIG. 1, FIG. 4, FIG. 6, FIG. 9) described above are designated by the same reference numerals, and description thereof will be omitted.

In FIG. 18, 29 _{1 to} 29 _n multiplex cells which notify congestion when a congestion state is detected, that is, control cells, to the switch output lines 4 ₁ to 4 _n according to the instruction of the congestion determination circuit 20. It is a control cell multiplex circuit. 30 ₁ to 30 _n are cell save circuits 22 _{1 to} 22.
_n corresponding to the control cell multiplexing circuit 29 ₁
The control cell separation circuit separates the control cell from the output of 29 _n and notifies the cell save circuits 22 _{1 to} 22 _n of the control information.

Next, the operation will be described. When the congestion detection circuit 20 detects the congestion state of the common buffer type switch 9, the congestion detection circuit 20 notifies the control cell multiplexing circuits 29 _{1 to} 29 _n , and control cells of a predetermined format are generated here. The control cells are multiplexed on the switch output lines 4 ₁ to 4 _n at timings such as idle cells and arrive at the control cell separation circuits 30 ₁ to 30 _n . The control cell separation circuits 30 ₁ to 30 _n extract only the control cells and send other data to the outgoing lines 2 ₁ to 2 _n . On the other hand, the extracted control cells are interpreted, and when the congestion state is determined, the cell save circuits 22 _{1 to} 22 _n are notified.

FIG. 19 is a diagram showing a mounting form of the cell exchange apparatus shown in FIG. The control cell multiplexing circuit is mounted on the common buffer type switch substrate 100. The congestion determination circuit 20 connects the congestion determination output line 31 to the control cell multiplexing circuits 29 _{1 to} 29 _n . Further, the control cell separation circuits 30 ₁ to 30 _n are respectively provided on the interface board. When the implementation form shown in FIG. 19 is adopted, the congestion judgment output line 31 from the congestion judgment circuit 20 exists only inside the common buffer type switch substrate 100, and the congestion judgment output line 31 as shown in FIG. Need not be connected to each interface board. Therefore, the number of signal lines between the interface board and the common buffer type switch board can be reduced.

Example 9. In addition, in the said Examples 1-8,
Although a single cell switching device is shown, this device may be linked and sequentially connected in multiple stages.

Example 10. Further, in the first to eighth embodiments, a single cell exchange device is shown, but the devices may be connected in a grid pattern and sequentially connected in a matrix pattern.

Example 11. In addition, the above-mentioned Examples 1 and 2
Then, the common buffer type switch 9 uses, as the destination information,
Although an example of directly referring to the header part of the cell is shown, a dedicated tag indicating the destination is added before or after the cell in the front stage of the common buffer type switch 9, and the destination information is detected by referring to this tag. Good. Further, the destination information does not directly indicate the destination but may be coded.

Example 12. Further, in the embodiment 1-8, but one cell has been described a case where output to only one destination output line 2 ₁ to 2 _m, the specification of how the destination, a plurality of outgoing lines 2 ₁ - It is also possible to set to output to 2 _m , and there may be a broadcast function.

Example 13 Further, the above-mentioned Examples 1 and 2
In the above, the common buffer type switch 9 processes one cell at a time, but the header part and the data part may be separated due to the structure of the cell and the cells may be exchanged using circuits of different speeds.

Example 14 In addition, in the above-described Examples 1 to 8, the speed of the incoming lines 1 ₁ to 1 _{n and} the speed of the outgoing lines 2 ₁ to 2 _m are the same, but _if the speed of the outgoing lines 2 ₁ to 2 _m is increased, the traffic focusing is achieved. It is also possible to increase the speed of the incoming lines 1 ₁ to 1 _n . Further, when the cell switching devices are linked, the inter-stage speed can be made faster than the incoming line speed to reduce the cell discard rate between stages.

Example 15. Further, in the first to eighth embodiments, the priority class for discarding cells is set to one, but by defining the priority class in cell units or virtual paths or virtual channel units and discarding insignificant cells first. , It is possible to minimize the impact on the terminal. Further, discard priority may be defined in burst units.

Example 16. Further, in the first to eighth embodiments, there is no restriction on the operation speed, but when there is a restriction on the operation speed, the cell switching device is provided with a front stage and a rear stage, respectively.
A serial / parallel conversion circuit and a parallel / serial conversion circuit may be provided to reduce the operation speed as a parallel signal.

[0157]

As described above, according to the present invention, even when traffic having a high burst characteristic is input to a plurality of incoming lines and they are destined to a single outgoing line, an expensive common buffer memory is used. There is an effect that a cell switching device capable of suppressing the cell discard rate to a low level can be obtained without expanding.

Further, according to the present invention, the cell discard rate can be kept low even when only one common buffer memory exists.

Further, according to the present invention, the cell discard rate can be kept low even when there are a plurality of common buffer memories.

Further, according to the present invention, the congestion state can be determined by the simple determination of comparing the cell reservation number of the common buffer memory with the threshold value.

Further, according to the present invention, when the congested state is determined, the cell is saved by the simple control of saving the cell, so that the structure of the save buffer control means is simplified.

Further, according to the present invention, since the threshold value is dynamically changed, the congestion state can be determined according to the system.

Further, according to the present invention, since the two threshold values are provided for determining the congestion state, it is possible to suppress the rapid state change between the congestion state and the non-congestion state.

Further, according to the present invention, since the history is used to determine the congestion state, the determination of congestion can be obtained more accurately.

Further, according to the present invention, with respect to the delay time, a cell bypassing the save buffer is provided for a cell having a severe demand, and the delay time for writing or reading to the save buffer is shortened. You can avoid the increase.

Further, according to the present invention, since the save buffer is bypassed for cells having high priority, priority processing can be performed even when the save buffer is used.

Further, according to the present invention, since the congestion state is detected by using the control cell, it is possible to detect the congestion state without using a special signal line.

[Brief description of drawings]

FIG. 1 is a block diagram showing a cell exchange apparatus according to an embodiment of the present invention.

2 is a block diagram showing details of a common buffer type switch 9 in FIG. 1 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 3 is a diagram showing a counting method of a cell accumulation number according to an embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure of the congestion determination circuit 20 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 5 is a diagram showing a cell input state according to an embodiment of the present invention.

FIG. 6 is a flowchart showing a procedure of the cell retraction circuit 22 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 7 is a diagram showing an operation of a save buffer according to an embodiment of the present invention.

FIG. 8 is a diagram showing an implementation of a cell exchange apparatus according to an embodiment of the present invention.

9 is a block diagram showing details of a common buffer type switch 9 in FIG. 1 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 10 is a flow chart showing a procedure of the congestion determination circuit 20 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 11 is a flow chart showing a procedure of the congestion determination circuit 20 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 12 is a block diagram showing details of the congestion determination circuit 20 in the cell exchange apparatus according to one embodiment of the present invention.

FIG. 13 is a flowchart showing the procedure of the congestion determination circuit 20 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 14 is a block diagram showing a cell exchange apparatus according to an embodiment of the present invention.

FIG. 15 is a flowchart showing the procedure of the cell retraction circuit 22 in the cell switching apparatus according to the embodiment of the present invention.

FIG. 16 is a block diagram showing a cell exchange apparatus according to an embodiment of the present invention.

FIG. 17 is a flowchart showing a procedure of the cell retraction circuit 22 in the cell exchange apparatus according to the embodiment of the present invention.

FIG. 18 is a block diagram showing a cell exchange apparatus according to an embodiment of the present invention.

FIG. 19 is a diagram showing an implementation of a cell exchange apparatus according to an embodiment of the present invention.

FIG. 20 is a block diagram showing a conventional cell exchange apparatus.

FIG. 21 is a block diagram showing a conventional ATM switch.

FIG. 22 is a configuration diagram of a conventional input control unit.

[Explanation of symbols]

1 ₁ to 1 _n incoming line 2 _{1 to} 2 _m outgoing line 3 _{1 to} 3 _n switch input line 4 ₁ to 4 _m switch output line 7 cell multiplexing circuit 8 cell separation circuit 9a common buffer type switch 9b common buffer type switch 10 header processing Circuit 11 Common buffer memory 11 _{1 to} 11 _p Common buffer memory 12 Free address management circuit 12 _{1 to} 12 _p Free address management circuit 13 Input line side crosspoint switch 14 Output line side crosspoint switch 15a Buffer control circuit 15b Buffer control circuit 16a Write buffer selection circuit 16b write buffer selecting circuit 17 the address exchange circuit 18 ₁ ~ 18 _m address queue 19a read buffer selecting circuit 19b read buffer selecting circuit 20 congestion determination circuit 21a switches the internal monitor 21b switches the internal monitor 22 ₁ - 2 _n cells save circuit 23 ₁ ~ 23 _n save buffer 24 ₁ to 24 _n save buffer control circuit 25 ₁ to 25 _n evacuation input selector 26 ₁ ~ 26 _n evacuation output selector 27 ₁ ~ 27 _n bypass link 28 _{1-28 n} priority cell discrimination circuit 29 _{1 to} 29 _n control cell multiplexing circuit 30 ₁ to 30 _n control cell separation circuit 31 congestion determination output line 32 history storage pool 33 history operation circuit 34 comparison circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hirotoshi Yamada 5-1-1, Ofuna, Kamakura City Mitsubishi Electric Corp. Communication Systems Research Laboratories (72) Ichino Oshima 5-1-1, Ofuna, Kamakura City Mitsubishi Electric Communication Systems Research Institute, Inc.

Claims (11)

[Claims] 1. A cell switching device having the following elements: (a) a plurality of incoming lines for inputting a cell consisting of a data part and a header part containing its destination information; (b) destination information specified in the header part of the cell. A plurality of output lines from which cells are output in accordance with the above, (c) a common buffer memory commonly provided for each output line is provided, the cells are input and stored in the common buffer memory, and the stored cells are A common buffer type switch for outputting to the output line designated by the header section, (d) Congestion judging means for monitoring the cell holding state of the common buffer memory of the common buffer type switch and judging the congested state, (e) the input Cell evacuation means provided between the line and the common buffer type switch corresponding to each of the incoming lines, and temporarily storing cells arriving at the incoming line. 2. The common buffer type switch comprises: a switch input line to which a cell is input; a plurality of switch output lines to which the cell is output according to a destination designated in a header part thereof; and the switch input line. The header processing circuit that detects the destination switch output line from the header portion of the cell that is input by the cell, the cell is written by designating the address, and the order of writing is designated by the address. A common buffer memory capable of reading the cells regardless of the above, a cell multiplexing circuit that multiplexes the output of the header processing circuit in cell units and connects to the common buffer memory, and separates the output of the common buffer memory in cell units. A cell separation circuit for allocating cells to the switch output line, and a common buffer memory in which the cells are written A buffer control circuit that manages the address for each cell destination, instructs a read address to a common buffer memory based on the address, and outputs the cells to the switch output line designated by the header section in a predetermined order. The cell switching device according to claim 1, further comprising: 3. The common buffer type switch comprises: a switch input line to which a cell is input; a plurality of switch output lines to which the cell is output according to a destination specified in its header section; and the switch input line. The header processing circuit that detects the destination switch output line from the header portion of the cell that is input by the cell, the cell is written by designating the address, and the order of writing is designated by the address. A plurality of common buffer memories capable of reading the cells regardless of the relationship; an input side crosspoint switch for selectively connecting the output of the header processing circuit to the predetermined common buffer memory; An output side crosspoint switch selectively connected to the switch output line, and the input side crosspoint switch Control the switch to select a common buffer memory to which the cell is written, and manage the address of the written cell in the buffer memory for each destination of the cell, and based on that, the output side crosspoint 2. The cell exchange apparatus according to claim 1, further comprising a buffer control circuit that controls a switch to output the cells in a predetermined order to the switch output line designated by the header section thereof. 4. The congestion determination means monitors the cell reservation number of a common buffer memory in the common buffer switch, and when the cell reservation number exceeds a predetermined threshold value, it is determined that the congestion state exists. The cell switching device according to claim 1, 2 or 3, characterized in that. 5. The evacuation buffer for writing a cell arriving at an incoming line, reading the written cell and outputting it to the switch output line, and the evacuation buffer for storing the cell in the evacuation buffer when the congestion determination means determines a congestion state. Puts on hold the cells entered on the incoming line,
In addition, control is performed such that nothing is read out and nothing is output to the switch input line, and when the congestion determination circuit does not determine a congestion state, the save buffer holds the cells input to the input line, and 5. The cell exchange apparatus according to claim 2, further comprising a save buffer control circuit that controls reading of the written cell. 6. The cell switching device according to claim 4, wherein the congestion determination unit dynamically changes a threshold value for determining congestion. 7. The congestion determination means, as thresholds for determining congestion, a first threshold for detecting a congestion state from a non-congested state and a second threshold for detecting a congestion state from a non-congested state. 6. The cell switching device according to claim 4, wherein the cell switching device has a threshold value of. 8. The congestion determining means collects a past history of the number of cells held in a common buffer memory in the common buffer type switch, and determines the congestion state from the history. 5. The cell exchange device according to item 5. 9. The cell exchanging device according to claim 4, wherein the cell evacuation means includes a bypass means that bypasses the evacuation buffer. 10. The cell exchange according to claim 9, wherein the cell evacuation means detects a priority regarding a delay of an input cell, and processing is different between a delay-sensitive cell and an insensitive cell. apparatus. 11. The congestion determination means mixes a control cell into the outgoing line when a congestion state is detected, and the cell evacuation means detects the congestion state by extracting the control cell from the outgoing line. The cell switching device according to claim 1, 2 or 3.