JPH07273612A - Gold code generating circuit - Google Patents

Abstract

PURPOSE:To automatically restore a malfunction in shift register circuit into a normal operation by generating a data set signal from output data of two kinds of shift registers and a data load signal and loading the data set signal to the shift register circuits. CONSTITUTION:A load circuit 4 is provided in addition to a GOLD code generating circuit provided with code generating circuits 1, 2 respectively outputting an m-series code and output data of a shift register circuit and an OR circuit 3 ORing two kinds of m-series codes from the code-generating circuits 1, 2 to generate a GOLD code, and the load circuit 4 generates a data set signal SET 401 by using output data 112, 212 of shift register circuits in code- generating circuits 5, 6 and a data load signal LD 402 received externally to give the signal 401 to the shift register circuits 110, 210 and initial data 111, 211 are automatically reset at the time of malfunction of the shift register circuits 110, 210.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GOLD code generation circuit in a digital logic circuit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a basic structure of a general GOLD code generating circuit.

Referring to FIG. 4, a general GOLD code generation circuit is composed of two shift registers 5 and 6, and a synthesis circuit 7 which synthesizes outputs 501 and 601 of the shift registers 5 and 6. .

A clock signal CLK502 is input to each shift register 5 and 6, and each output data 501 and 601 is an m-sequence code (maximum length).
linear shift register seq
Unce code).

Many codes (GOLD codes) 701 can be generated by combining these two m-sequence codes by the shift register output combining circuit (+) 7.

Next, FIG. 6 is a block diagram of an example of a conventional GOLD code generation circuit.

Referring to FIG. 6, a 1-bit GOLD code 301 is a 1-bit code generation circuit output signal 101 and a 1-bit GOLD code 301.
Bit-code generation circuit output signal 201 and OR circuit 3
It is obtained by synthesizing by.

Since the code generating circuit 1 and the code generating circuit 2 have the same internal structure, the operation of the conventional example will be described with reference to FIG. 7 together with the code generating circuit 1 as an example.

FIG. 7 is an operation timing chart of each data and signal in FIG.

Initial data 1 of N bits (N is a positive integer)
11 and the data load signal (LD) 402 initialize the N-bit parallel input shift register circuit 110.

Next, the shift register circuit 110 outputs the N-bit shift register circuit output data 112 to the tap circuit 1.
20 and 130, and the 1-bit tap circuit output signal 122 output from the tap circuit 120 is input as the shift input signal SI of the shift register circuit 110 to shift the data.

The tap circuit 120 is the shift register circuit 1
10 N-bit shift register circuit output data 112
And a feedback tap data 121 of N bits for generating a tap circuit output signal 122.

The tap circuit 130 is a tap circuit for code generation for generating the code generation circuit output signal 101 from the N-bit shift register circuit output data 112 and the N-bit code tap data 131.

The tap circuit 120 and the tap circuit 130
Have the same function, the operation of the tap circuit will be described by taking the tap circuit 120 as an example and also using FIG.

FIG. 3 is a circuit diagram of an example of the tap circuit shown in FIGS. 1 and 6.

Referring to FIG. 3, the tap circuit includes shift register circuit output data 112 and feedback tap data 121.
, "N-1", "N" of each bit "1", "2", ..., "N-1", AND circuit 140, 150, ..., 160, 170
After taking the logical product with, the output bit "1"
The exclusive OR of the selection signal 141, the bit “2” selection signal 151, ..., The bit “N−1” selection signal 161, and the bit “N” selection signal 171 is obtained by the exclusive OR circuit 180. The tap circuit output signal 122 is generated.

The code generation circuit 2 includes an N-bit shift register circuit 210, a feedback tap circuit 220, and a code generation tap circuit 230.
Since it has the same function as, the detailed description will be omitted.

[0018]

In this conventional GOLD code generation circuit, as shown in FIG. 7, the shift register circuit output data 112 is "0" due to a malfunction of the shift register circuit 110 in the code generation circuit 1, for example. When it becomes ", the tap circuit output signal (shift input signal SI) 122 output from the tap circuit 120 also outputs" 0 ".

Therefore, the shift register circuit 110 becomes a data shift of only "0" and cannot return to the normal operation. As a result, the code generation circuit output signal (m-sequence code) 101 of the code generation circuit 1 is always "0", and the GOLD code 301 is always "0".

The same applies when the shift register circuit 210 in the code generation circuit 2 malfunctions.

That is, in such a case, there is a problem that the original operation cannot be restored unless the initial data is manually reset in the shift register circuit in the code generation circuit.

An object of the present invention is to provide a load circuit that generates a data set signal from two types of shift register circuit output data and a data load signal and loads the data set signal into the shift register circuit. Another object of the present invention is to provide a GOLD code generation circuit capable of automatically returning to normal operation.

[0023]

According to the present invention, first and second code generating circuits for outputting an m-sequence code and shift register circuit output data, respectively, and the first and second code generating circuits. The two types of m-sequence codes from
In a GOLD code generation circuit including an OR circuit for generating an OLD code, a data set signal is generated from the shift register circuit output data of the first and second code generation circuits and a data load signal input from the outside. A GOLD code generation circuit having a load circuit is obtained.

The load circuit outputs N of the shift register circuit output data of the first and second code generation circuits.
First and second all “0” data detection circuits for respectively detecting that all bits are “0”, and the first and second
All "0" from the second all "0" data detection circuit
An OR circuit for ORing the detection signal and the data load signal from the outside, a first flip-flop circuit for inputting an output signal of the OR circuit, a clock signal and an output of the first flip-flop circuit A GOLD code generating circuit is obtained, which comprises a second flip-flop circuit that inputs a signal and outputs a data set signal to the first and second shift register circuits.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the GOLD code generation circuit of the present invention.

Referring to FIG. 1, the GOLD code generation circuit of this embodiment is constructed by adding one load circuit to the conventional GOLD code generation circuit shown in FIG.

That is, the GOLD code generation circuit of this embodiment comprises a code generation circuit 1, a code generation circuit 2, an OR circuit 3, and a load circuit 4.

Next, the operation of this embodiment will be described.

The N-bit GOLD code 301 is obtained by synthesizing the 1-bit code generation circuit output signal 101 and the 1-bit code generation circuit output signal 201 by the OR circuit 3.

The shift register circuits 110 and 210 in the code generation circuits 1 and 2 are initialized by the 1-bit data set signal SET401 output from the load circuit 4.

Here, the operation of the code generation circuit 1 will be described as an example.

First, the shift register circuit 110 is initialized by the N-bit initial data 111 and the 1-bit data set signal SET401.

The shift register circuit 110 outputs N-bit shift register circuit output data 112 to the tap circuit 12.
0, 130, and the output of tap circuit 120 is 1
Bit tap circuit output signal 122 shifts input signal S
I is input to the shift register circuit 110, and the shift register circuit 110 shifts the data.

The tap circuit 120 generates a tap circuit output signal 122 from the shift register circuit output data 112 and the N-bit feedback tap data 121.

The tap circuit 130 also outputs the shift register circuit output data 112 and N-bit code tap data 1
1 and a 1-bit code generation circuit output signal 101 is generated.

The code generation circuit 2 is similar to the code generation circuit 1, and the shift register circuit 210 is similar to the shift register circuit 110. Furthermore, tap circuit 2
Reference numerals 20 and 230 are similar to the tap circuits 120 and 130, respectively.

The details of the tap circuit are as described above with reference to FIG. 3, and the description thereof will be omitted.

Next, the GOL of this embodiment including the load circuit
The D code generation circuit will be described in detail with reference to FIGS.

FIG. 2 is a circuit diagram of an example of the load circuit in FIG. 1, and FIG. 5 is an operation timing chart of each data and signal in FIG.

Referring to FIG. 2, this load circuit is the shift register circuit output data 112, 21 of the code generation circuit.
All “0” data detection circuits (DET) 410, 4 for detecting that all N bits of 2 are “0”
20 and the all “0” detection signals 411 and 421 from the DETs 410 and 420 and the data load signal LD402 from the outside, and an OR circuit (OR) 430.
And a flip-flop circuit (FF) 440 that inputs the OR circuit output signal 431 of the OR 430 and the clock signal CLK and the flip-flop circuit output signal 441 of the FF 440 that outputs the data set signal SET401 to the shift register circuit. It consists of and.

The data load signal LD402 is input, or all bits of the shift register circuit output data 112 (shift register circuit output data 212) are "0".
When the all "0" detection signal 411 (all "0" detection signal 421) becomes "1", the OR circuit output signal 431 from the OR 430 rises to "1".

Using the OR circuit output signal 431 as a clock, the flip-flop circuit output signal 441 from the FF 440 in the standby state rises to "1",
The FF450 retakes this and resets the data set signal SET.
It is output as 401.

At the same time, the inverted output of the FF 450 is output as a reset signal RST 451 to reset the FF 440, whereby the FF 440 is again in the waiting state for the OR circuit output signal 431.

As described above, in this embodiment, the data load signal LD402 is input, or the shift register circuit output data 112 or the shift register circuit output data 2 is input.
When all 12 bits are "0", the data set signal SET4 is sent to the shift register circuit in the code generation circuit.
01 is output.

[0046]

As described above, according to the present invention, the first and second code generating circuits for outputting the m-series code and the shift register circuit output data, respectively, and the first and second code generating circuits are provided. In a GOLD code generation circuit including a logical sum circuit for synthesizing two kinds of m-sequence codes to generate a GOLD code, shift register circuit output data of the first and second code generation circuits and a data load signal input from the outside The provision of the load circuit for generating the data set signal from and has the effect that the initial data can be automatically reset even if the shift register circuit malfunctions.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a GOLD code generation circuit of the present invention.

FIG. 2 is a circuit diagram of an example of a load circuit in FIG.

FIG. 3 is a circuit diagram of an example of the tap circuit in FIGS. 1 and 6.

FIG. 4 is a block diagram showing a basic configuration of a general GOLD code generation circuit.

5 is an operation timing chart of each data and signal in FIG. 1. FIG.

FIG. 6 is a block diagram of an example of a conventional GOLD code generation circuit.

FIG. 7 is an operation timing chart of each data and signal in FIG.

[Explanation of symbols]

1, 2 code generation circuit 3, 430 logical sum circuit 4 load circuit 5, 6 shift register 7 shift register output synthesis circuit (+) 101, 201 code generation circuit output signal 110, 210 shift register circuit 111, 211 initial data 112, 212 shift register circuit output data 120, 130, 220, 230 tap circuit 121, 221 feedback tap data 122, 222 tap circuit output signal 131, 231 code tap data 140, 150, 160, 170 AND circuit 141 bit "1" selection Signal 151 bit "2" selection signal 161 bit "N-1" selection signal 171 bit "N" selection signal 180 Exclusive OR circuit 301,701 GOLD code 401 Data set signal SET 402 Data load signal LD 410,420 Oh "0" data detection circuit (DE
T) 411, 421 all “0” detection signal 431 OR circuit output signal 440, 450 flip-flop circuit (FF) 441 flip-flop circuit output signal 442 “1” level clamp signal 451 reset signal RST 452, 502 clock signal CLK 501 , 601 Shift register output signal

Claims (2)

[Claims] 1. A first and second code generation circuit for outputting an m-series code and shift register circuit output data, respectively, and two kinds of the m-series code from the first and second code generation circuits. In a GOLD code generation circuit including a logical sum circuit for synthesizing to generate a GOLD code, a data set signal is generated from the shift register circuit output data of the first and second code generation circuits and a data load signal input from the outside. A GOLD code generation circuit comprising a load circuit for generating 2. The load circuit detects that all N bits of the shift register circuit output data of the first and second code generation circuits are “0”, respectively.
The second all "0" data detection circuit and the first and second
OR circuit for taking the OR of the all "0" detection signal from the all "0" data detection circuit and the data load signal from the outside, and the first flip-flop circuit for inputting the output signal of this OR circuit. And a second flip-flop circuit that inputs a clock signal and the output signal of the first flip-flop circuit and outputs a data set signal to the first and second shift register circuits. The GOLD code generation circuit according to claim 1.