JPH0727689B2 - Data storage - Google Patents

Description

The present invention relates to a data storage device, and more particularly to a read circuit of a magnetic storage device and an optical disk device.

(Prior Art) Conventionally, in this type of data storage device, the following two methods are known to guarantee the reading of data.

The first method is realized by a read circuit as shown in FIG. 3, and the read circuit is composed of the level detection circuit 6 and the variable resistor 13. The read signal is applied to one input of the level detection circuit 6 via the signal line 301, and the sliding terminal voltage of the variable resistor 13 is applied to the other input from the signal line 302. The variable resistor 13 is configured such that the voltage V is applied to one terminal and the other terminal is grounded.

FIG. 4 is a waveform diagram showing the signal waveform of each part of FIG. In normal operation, the output voltage k of the variable resistor 13 is used as a threshold voltage to detect the amplitude of the read signal on the signal line 301 with a voltage of k _1. However, in the case of a read operation guarantee test, adjustment of the variable resistor 13 is performed. To set the threshold voltage to the values of k ₂ and k ₃ . As a result, it is possible to guarantee the margin of the read operation with respect to the pseudo peak r and the amplitude decrease s caused by the minute defect included in the read signal on the signal line 301.

When the threshold voltage is k ₂ , the level detection circuit 6 sends the signal line
Looking at the output signal on 303, the output pulse s ₀ corresponding to the waveform portion of s in the read signal on the signal line 301 is extremely thin as shown by the broken line, and it is confirmed that it is close to the detection limit. Shows. In addition, when the threshold voltage is k ₃ , it indicates that there is still room for the pseudo peak r.

Next, the second method is a data discrimination circuit as shown in FIG.
15 and the delay line 14, the data lock circuit 15 has one input terminal to which a lead lock is input via the signal line 503 and the other input terminal to the delay line.
An output signal is input from 14 through a signal line 502.
When the delay line 14 is input, a data pulse obtained by pulsing a read signal is input from the signal line 501. Delay of Day rate line 14 is the output terminal t ₁ ~t ₃
Different time values can be taken by switching between.

During normal operation, the delay amount of the delay line 14 is set to t ₁ , which is the position with the maximum margin for data discrimination. In the case of the guarantee test of the read operation, the delay amount of the delay line 14 is set to the values of t ₂ and t ₃ .

FIG. 6 is a waveform diagram showing the waveform of each part of FIG. Sixth
According to the figure, the operation of FIG. 5 is from the delay line 14 to the signal line.
The leading edge of the data pulse that is the output signal to 502 is the signal line 5
If it is located in the "high" level time zone of the lead clock on 03, an output signal pulse is generated from the data discrimination circuit 15 on the signal line 504 in synchronization with the trailing edge of the lead clock on the signal line 503. Otherwise, the pulse is not generated. That is, the data discrimination circuit 15 synchronizes the data pulse on the signal line 501 including the peak shift caused by the interference between the reproduced waveforms and the defect of the recording medium with the lead clock on the signal line 503 having a different phase, A phased output data pulse is generated on signal line 504.

In the guarantee test, when the delay amount of the delay line 14 is set to t ₂ , the phase of the data pulse on the signal line 502 relatively advances by the time of t ₁ −t ₂ = τ. At this time, among the data pulses on the signal line 502, the pulse v ₂ overflows from the “H” area of the lead clock on the signal line 503, and the data cannot be discriminated. On the contrary, when the delay amount of the delay line 14 is set to t ₃ , the phase of the data pulse on the signal line 502 is relatively delayed by the time of t ₃ −t ₁ , which is different from the case of t ₂ described above.
Data discrimination is guaranteed for u ₂ .

As described above, the second method guarantees the margin for phase discrimination of the data pulse on the signal line 502.

(Problems to be Solved by the Invention) The conventional read operation guarantee method described above has the following drawbacks.

First, the NRZI 8-9 code is well known as the MFM method in the recording modulation method used in the conventional magnetic storage device. Since the demodulation of MFM is a phase discrimination method, the guarantee test by the data discrimination circuit as shown in FIG. 5 is adopted, and the test is performed with different binary delay amounts. The demodulation of the 8-9 code is basically a phase discrimination method like the MFM, but the margin of the amplitude detection operation is smaller than the margin of the phase discrimination operation due to the characteristics of the reproduced waveform. The guarantee test by the level detection circuit as shown in (3) is adopted, and the test is performed with different binary threshold voltages.

However, the most recent recording modulation method is the 2-7 code or the 1-7 code, and even if these signal detections are basically the same as the 8-9 code described above, they are different from the 8-9 code in phase discrimination. Since the margin of operation is extremely small, it is necessary to guarantee the phase discrimination in addition to the guarantee of the amplitude detection, and it is necessary to set a total of four conditions, which results in a long guarantee test time. Atsuta

Further, as a matter of course, the switching of the threshold voltage and the delay time is automatically performed through the control signal line between the data storage device and the host device, or between the test devices. However, there is a drawback in that the reliability of the system as a whole is increased.

An object of the present invention is to provide noise generating means so that the magnitude of noise voltage output corresponding to an input signal when reproducing stored data can be controlled, and the output voltage of the noise generating means can be used as a read signal. By removing the above defects by mixing,
It is an object of the present invention to provide a data storage device having a read circuit configured so that the reliability of the entire system can be kept high while shortening the time of the guarantee test.

(Means for Solving Problems) A data storage device according to the present invention comprises a noise mixing means for mixing a reproduced data signal read from a recording medium with a noise voltage whose magnitude changes according to a control signal, Level detection means for generating a pulse voltage corresponding to an amplitude of a predetermined threshold value or more of the reproduction data signal output from the noise mixing means, and a peak position of the reproduction data signal output from the noise mixing means. Correspondingly, it is provided with peak detecting means for generating a pulse voltage, and arithmetic means for performing a logical product of the pulse voltage from the level detecting means and the pulse voltage from the peak detecting means.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data storage device according to the present invention. Referring to FIG. 1, an embodiment of the present invention includes a recording medium 2, a magnetic head 1 for reproducing a stored signal from the recording medium 2, an amplifier 3 for amplifying an output read signal of the magnetic head 2. Signal line 101 from amplifier 3
An automatic gain control circuit (hereinafter referred to as an AGC circuit) 4 for amplifying the output read signal to the above to a predetermined average amplitude,
A noise generator 9 for outputting a noise voltage corresponding to a control input signal on the signal line 107, and a mixing circuit 1 for adding the output voltage of the noise generator 9 to the output signal of the AGC circuit 4 described above.
0, a filter circuit 5 for inputting an addition signal of the signal line 102 to perform low-frequency removal and equalization, an output signal from the filter circuit 5 to the signal line 103, and a threshold voltage Vth are compared, A level detection circuit 6 for generating an output pulse for an amplitude larger than Vth, a peak detection circuit 7 for generating a pulse voltage corresponding to the peak position of the output signal of the filter circuit 5, and a level detection circuit 6 From the peak detection circuit 7 to the output signal on the signal line 105 and an AND gate circuit 8 for performing an AND operation.

2 (a) and 2 (b) are waveform diagrams showing the waveforms of the respective portions of FIG.

FIG. 2 (a) shows a waveform when the noise generator 9 is not operating,
FIG. 2B shows a waveform when the noise generator 9 is operating.

When the control signal applied from the signal line 107 to the noise generator 9 is at "H" level, the noise generator 9 is in the non-operation mode, and the noise voltage is not output. At this time, the pseudo peak x caused by a defect on the storage medium included in the read signal x
₀ and the amplitude decrease y ₀ are respectively x ₂ and y _{2 in} the output signal from the filter circuit 5 onto the signal line 103, but since there is a detection margin with respect to the threshold voltage Vth, the level detection circuit 6 There is no pulse at the position x ₃ corresponding to the pseudo peak x ₂ in the output signal from the to the signal line 104, and at the position corresponding to the amplitude decrease y ₂
y ₂ pulse is generated. y ₃ and the output signal from the peak detection circuit 7 to the signal line 105 are ANDed, and the output signal from the AND gate circuit 8 to the signal line 106 is output as y ₄ .

Of the bits included in the output signal from the AND gate circuit 8 to the signal line 106, z ₁ , z ₂ , z ₃ including many peak shifts.
Bits of z and z ₄ are in the “H” area of the read clock [RC] generated in the data discrimination circuit (not shown) in the subsequent stage, and the data can be discriminated.

Next, the control signal from the signal line 107 to the noise generator 9 is "L".
When the level is reached, the noise generator 9 is in the operation mode and the random noise voltage is output. At this time, the waveform of each part is as shown in FIG.

The random noise output from the noise generator 9 is the AGC circuit 4
The signal is superimposed on the output signal on the signal line 102 from, and a thick waveform is observed like the output signal from the AGC circuit 4 to the signal line 102 in FIG. 2 (b). The noise is slightly smaller. The pseudo peak x ₀ and the amplitude decrease y ₀ included in the read signal are the output signal C of the filter circuit 5.
Then x ₂ and y ₂ respectively. Since x ₂ has a margin with respect to the threshold voltage Vth even if random noise is superimposed, no pulse is generated in the output signal from the level detection circuit 6 to the signal line 104. When random noise is superimposed on y ₂ , of the output signal from the level detection circuit 6 onto the signal line 104, the pulse of y ₃ has large jitter and has the opportunity to disappear.
This is because there is no detection margin for the threshold voltage Vth. As a result, the bit of y ₄ included in the output signal from the AND gate circuit 8 to the signal line 106 also has a chance to disappear, and normal reading becomes impossible.

Therefore, it can be seen that the read operation margin of this magnetic storage device is small. Also, from the AND gate circuit 8 to the signal line 106
Bits z ₁ , z ₂ , z ₃ and z ₄ included in the upward output signal f and having many peak shifts have large fluctuations because random noises are superposed on each other. Therefore, as compared with the "H" area of the read clock (RC) generated in the data discrimination circuit (not shown) in the subsequent stage, the bits of z ₂ and z ₃ are often out of the "H" area and are normal. Reading becomes impossible. Therefore, the read operation margin of this device can be determined here as well.

As described above, by superimposing an appropriate amount of noise on the read signal, it is possible to simultaneously determine the margin for amplitude detection and the margin for phase discrimination.

Further, in this embodiment, the noise voltage is superposed on the output part of the AGC circuit 4, but it is superposed on the output part of the amplifier 3 and the output part of the filter circuit 5 to set the noise voltage value to an appropriate value. It can be easily inferred that almost the same results can be obtained.

(Effects of the Invention) As described above, the present invention incorporates a noise generator to operate the noise generator at the time of a guarantee test of the read operation, and reads out random noise of an appropriate size output from the noise generator. By superimposing it on the signal, there is an effect that it is possible to simultaneously determine the margin for amplitude detection and the margin for phase discrimination.

As described above, there is an effect that the threshold value switching control system for testing the amplitude detection margin and the delay amount switching control system for testing the phase discrimination margin are unnecessary, and the control is simplified. Therefore, there is an effect that the reliability of the device is improved and the assurance test is easy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data storage device according to the present invention. 2 (a) and 2 (b) are explanatory views showing the waveforms of the respective parts of FIG. FIG. 3 is a block diagram showing an example of a conventional amplitude detecting circuit. FIG. 4 is an explanatory view showing the waveforms of the respective parts of FIG. FIG. 5 is a block diagram showing an example of a phase discrimination circuit according to the prior art. FIG. 6 is an explanatory view showing the waveforms of the respective parts of FIG. 1 ... Magnetic head, 2 ... Recording medium 3 ... Amplifier 4 ... Automatic gain control (ACG) circuit 5 ... Filter circuit, 6 ... Level detection circuit 7 ... Peak detection circuit, 8 ... AND gate circuit 9 …… Noise generator, 13 …… Variable resistor 14 …… Delay line 15 …… Data discrimination circuit

Claims (1)

[Claims] 1. A noise mixing means for mixing a reproduced data signal read from a recording medium with a noise voltage whose magnitude changes according to a control signal, and the reproduced data signal outputted from the noise mixing means. Level detecting means for generating a pulse voltage corresponding to an amplitude of a predetermined threshold value or more; peak detecting means for generating a pulse voltage corresponding to the peak position of the reproduction data signal output from the noise mixing means; A data storage device comprising: an arithmetic means for performing a logical product of a pulse voltage from the level detecting means and a pulse voltage from the peak detecting means.