JPH0727830A - Integrated circuit test pattern evaluation device - Google Patents

Abstract

(57) [Abstract] [Purpose] To facilitate the evaluation of test patterns in large-scale analog / digital mixed integrated circuits. [Configuration] A normal voltage value in each signal line inside the integrated circuit is calculated from the circuit information and the input / output characteristics, and a fault voltage range in which a normal voltage value of each signal line can be regarded as a fault state is determined for each signal line. A voltage signal in a specific failure voltage range, which is a failure voltage range of one specific signal line arbitrarily selected from among the signal lines, is propagated to the output side of the integrated circuit by using the circuit information and the input / output characteristics. When this is done, the output side of the integrated circuit is reduced while reducing the specific failure voltage range so that the output of that circuit element is in the range corresponding to the failure voltage range with respect to the normal voltage value in order from the circuit element closer to the specific signal line. Toward, the analysis is sequentially performed by changing the specific signal line to all the signal lines to determine the detectable fault voltage range in the signal line in which the fault can be detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for evaluating a test pattern for checking the operation of an integrated circuit in which analog elements and digital elements are mixed.

[0002]

2. Description of the Related Art Conventionally, for checking the operation of an integrated circuit,
Various input patterns are input to an integrated circuit, and an abnormality of the integrated circuit is detected depending on whether or not the output voltage value of the integrated circuit becomes a normal value. In this case, if you try to create all input patterns,
It increases exponentially as the number of input terminals of the integrated circuit increases. Therefore, the operation check using all the input patterns has a problem that the inspection time becomes long, which is not practical. Therefore, it is necessary to design the shortest input pattern that enables the most efficient operation check. For this,
There is a need for a device for evaluating an input pattern, that is, a device for evaluating a failure detection rate according to an input pattern and reducing an overlapping input pattern that can detect only the same failure.

For this evaluation it is necessary to simulate an integrated circuit failure. A method is known in which the following conditions are introduced as a fault simulation in a logic circuit. That is, firstly, the logic circuit is configured by a combination of logic gates that perform binary (0, 1) logical operation in discrete time. Secondly, the failure of the logic circuit is limited to the failure (single stuck-at failure) in which one signal line in the circuit is always fixed to one logic value (0 or 1).

In analog circuits, the operation of circuits composed of electronic components such as transistors, resistors and capacitors is simulated. In this case, the element level operation of the electronic component is defined by the differential equation regarding the current / voltage time element at each terminal, and the simultaneous equations established in the target circuit are numerically solved to The current / voltage value of the signal line is obtained.

The simulation of this analog circuit is
Since it is necessary to solve the differential equations and simultaneous equations for each of the assumed failure phenomena, the simulation takes a lot of time.

On the other hand, in an integrated circuit in which analog elements and digital elements are mixed (hereinafter referred to as "analog / digital mixed integrated circuit"), the digital circuit is developed into electronic parts such as transistors and resistors, and is regarded as an analog circuit. Therefore, the failure simulation performed in the analog integrated circuit is possible. In this simulation, for a set of input signals having a test pattern, a normal circuit that does not include a fault and a fault circuit that assumes a fault are both simulated, and two simulation results (output of the integrated circuit) Is compared to determine whether or not a fault assumed in the fault circuit can be detected by the set of input signals. By performing such a simulation similarly for all possible faults and evaluating the results, the fault coverage of one set of input signals of the test pattern can be evaluated. Similarly, the failure detection rate of the entire test pattern can be evaluated by performing the same evaluation on each of the input signals of all the sets of the test pattern.

[0007]

In the analog / digital mixed integrated circuit, since the analog circuit exists, the simulation for the logic circuit cannot be applied. Further, as described above, in the analog / digital mixed integrated circuit, the simulation for the analog circuit can be applied by regarding the digital circuit as the analog circuit. However, this method requires an extremely large amount of time because it is a method of numerically analyzing and simulating differential equations and simultaneous equations for the number of failures. Further, in the simulation for the analog circuit, the analysis value may not converge and a numerical solution may not be obtained depending on the failure mode. Therefore, in an embedded integrated circuit with a large number of elements, the number of assumed failures increases, and it is not realistic to use this method for evaluation of test patterns.

The present invention has been made to solve the above problems, and an object thereof is to easily carry out evaluation of a test pattern in a large-scale analog / digital mixed integrated circuit.

[0009]

SUMMARY OF THE INVENTION The structure of the invention for solving the above-mentioned problems is an apparatus for evaluating a test pattern input to an integrated circuit in which analog elements and digital elements are mixed, and circuit information, each element I / O characteristics are stored, and for one set of input signals in the test pattern,
A calculating unit that calculates a normal voltage value in each signal line inside the integrated circuit from the circuit information and the input / output characteristics, and a failure voltage range in which a normal voltage value of each signal line can be regarded as a failure state for each signal line. Circuit information and a failure state setting unit that sets the voltage signal in a specific failure voltage range that is a failure voltage range of one specific signal line arbitrarily selected from the signal lines set by the failure state setting unit. When propagating to the output side of the integrated circuit using the input / output characteristics, in order from the circuit element close to the specific signal line, the output of the circuit element exists in the range corresponding to the fault voltage range with respect to the normal voltage value,
While limiting the specific failure voltage range, the analysis is sequentially performed toward the output side of the integrated circuit by changing the specific signal line to all the signal lines and by the propagation analysis unit. And a detectable range determining means for determining a detectable fault voltage range in each signal line capable of fault detection by a set of input signals of the test pattern from the propagation result at the output of the integrated circuit. .

[0010]

The normal voltage value of each signal line of the integrated circuit is calculated by using the circuit information and the input / output characteristics of each element for one set of input signals of the test pattern. next,
A voltage range that can be distinguished from the normal voltage value of each signal line is set as a fault voltage range that originally occurs in each signal line. Focusing on one signal line (the focused signal line is the “specific signal line”, the fault voltage range of the specific signal line is the “specific fault voltage range”), and the specific fault voltage range is used as circuit information and input / output characteristics. Based on this, the signal is propagated to the output terminal side of the integrated circuit. At that time, in the output of each circuit element, only the input voltage range corresponding to the output voltage that can be distinguished from the normal voltage value becomes the fault voltage range that can propagate further downstream in the signal line of the output. The voltage range in the specific signal line corresponding to the detectable voltage range in this output is obtained. This voltage range is a reduction of the fault voltage range. Thus, as the propagation analysis progresses, the range of fault voltage that can be detected in the specific signal line is limited. Then, the detectable fault voltage range of the specific signal line corresponding to the detectable voltage range at the output of the integrated circuit (this range is finally determined as the “detectable fault voltage range”).

As described above, the detectable fault voltage range in one specific signal line is determined. Similarly, with respect to other signal lines, the propagation analysis of the fault voltage range initially set as the fault origin is executed to finally determine the detectable fault voltage range in the signal line as the fault source. In this way, the detectable fault voltage range of each signal line in which a fault can be detected by one input signal set of the test pattern is sequentially determined.

As described above, even if analog elements and digital elements are mixed, a fault voltage which originally occurs in each signal line for one input signal set of the test pattern and can be detected in the signal line is detected. The range is first initialized. And while propagating the fault voltage range to the downstream side,
The fault voltage range of the specific signal line, which is the source of the fault, is gradually reduced along with the propagation so that the voltage range can be distinguished from the normal value in each signal line, and eventually, at the output end of the integrated circuit. The failure voltage range (detectable failure voltage range) of the specific signal line is determined so that the failure detection is possible. Therefore, the analysis calculation is to calculate the output value according to the input / output characteristics for each element and to calculate the range of the input voltage so that the output value falls within a predetermined range. Can be evaluated.

[0013]

EXAMPLES The present invention will be described below based on specific examples. The apparatus of this embodiment is composed of the computer system shown in FIG. In FIG. 1, a CPU 1 that executes a failure simulation is connected to a ROM 2 that stores a program that executes a failure simulation, a RAM 3 that stores various data, and an input / output interface 5. The input / output interface 5 has a CRT 4 for displaying data, a keyboard 6 for inputting data and operation commands, a test pattern, circuit information, and a floppy disk (FD) storing input / output characteristics of each element.
A floppy disk drive (FDD) 7 for reading data 8 is connected.

Further, the RAM 3 stores a circuit information memory 301 in which circuit information including circuit elements and connection information between the elements is stored, and input / output characteristics of each circuit element are approximated by a broken line to store a linear function of this broken line. Input / output characteristic memory 302, test pattern memory 303 for storing an input test pattern, normal voltage value memory 3 for storing a normal voltage value of each signal line for a set of input signals having a test pattern
04, a failure state memory 305 that stores a failure voltage range that can be determined as a failure with respect to the normal voltage value of each signal line, detects a failure state when a signal in the failure voltage range of a certain signal line is propagated toward the output side A propagation data memory 306 that stores propagation data such as a voltage range of a signal line that can be formed, and a detectable voltage range memory 307 that stores a detectable fault voltage range of each signal line obtained as a result of propagation calculation of a fault voltage range are formed. ing.

Next, the processing procedure of the CPU 1 of this apparatus will be described with reference to the flowcharts of FIGS.

1. Circuit information In step 100, circuit information is input from the FD 8 and the circuit information is stored in the circuit information memory 301. This circuit information is, for example, a circuit diagram of the analog / digital mixed integrated circuit shown in FIG.
It is described as shown in FIG. The circuit information is composed of information about circuit elements and connections, and as shown in FIG. 5, circuit element numbers (A1, A2, etc.), function names of circuit elements (amp, comp, nor, alogS, etc.) , Input signal line numbers of circuit elements (L1, L2, L3, etc.) and output signal line numbers of circuit elements (L2, L5, L6, etc.). In the function names of circuit elements, amp means amplifier, comp means comparator, nor means NOR gate, and alogS means analog switch.

2. Input / Output Characteristics Next, in step 102, the input / output characteristics of each circuit element are input from the FD 8, and the input / output characteristics are stored in the input / output characteristics memory 302. For example, the input / output characteristic of the amplifier A1 is given as shown in FIG. In this case, it is approximated by two broken lines. That is, the first broken line S1
When Vin ≦ 0, Vout = 0, and the second broken line S2 is 5 / G
When ≧ Vin> 0, it is given by Vout = G × Vin. However,
G is the amplification factor of the amplifier A1 given by the circuit information.
Straight line data that specifies each of these broken lines is stored in the input / output characteristic memory 302.

The input / output characteristics of the comparators A2 and A3 are approximated by three broken lines T1, T2 and T3 as shown in FIG. That is, the first broken line T1 is V when Vin- <Vin +
When out = 5 and the second broken line T2 is Vin-> Vin +, Vou
It is expressed as t = 0. The third broken line T3 is represented as Vout = indefinite when Vin- = Vin +.

The analog switch A6 is such that when Vin ≧ 3, Vout = 5, Vin <2.5, Vout = 0, 2.5 ≦.
When Vin <3, Vout = indefinite. in this way,
The input / output characteristic of each circuit element is approximated by a polygonal line, and data specifying each polygonal line is stored in the input / output characteristic memory 302.

3. Test Pattern Next, in step 104, the test pattern stored in the FD 8 is input, and the data is stored in the test pattern memory 303. The test pattern is used to check the operation of the analog / digital mixed integrated circuit, and is given by a column of a set of input signals simultaneously given to each input terminal. Then, when the set of input signals is input to the integrated circuit and the output of the integrated circuit does not exhibit a predetermined true value, the failure is detected by the set of input signals. The criteria for what kind of failure is detected by the set of signals are given in advance.

4. Calculation of Normal Voltage Value Next, in step 106, a variable I representing one input signal set of the test pattern is initialized to 1. Next, in step 108, one input signal set D
The normal voltage value of each signal line for (I) is calculated, and the calculation result is stored in the normal voltage value memory 304. For example, in the circuit shown in FIG. 4, it is assumed that the reference voltage 1.5V is applied to the signal line L3 and the reference voltage 3.5V is applied to the signal line L4, and 0.05V is applied to the signal line L1. . These voltage values are values determined by the set of input signals D (I) of the test pattern.

According to the circuit information shown in FIG. 5, the above voltage values are sequentially propagated to the output side to calculate the normal voltage value of each signal line. For example, if the voltage of the signal line L1 is 0.05 V, the circuit element inputting the signal line L1 is searched from the circuit information of FIG. Then, the amplifier A1 changes the signal line L1.
Input / output characteristic memory 302
From the input / output characteristics of the amplifier A1 stored in the table, the output voltage Vout = 0.5 for the input voltage Vin = 0.05.
Is calculated. Therefore, the normal voltage value of the signal line L2 is 0.
It is determined to be 5V.

Next, when the voltage of the signal line L2 is determined,
The circuit element inputting the signal line L2 is searched from the circuit information of FIG. Then, the comparators A2 and A3 are determined as the circuit elements inputting the signal line L2. Since the voltage values of the input signal lines L3 and L4 input to the other comparators A2 and A3 are already known, the input / output characteristic memory 302
The normal voltage value of the output signal line L5 of the comparator A2 and the normal voltage value of the output signal line L6 of the comparator A3 are determined to be 5V and 0V, respectively, from the input / output characteristics of the comparator stored in FIG.

Next, when the normal voltage values of the signal lines L5 and L6 are determined, the circuit element inputting the signal lines L5 and L6 is searched from the circuit information of FIG. The element is N
The OR gates A4 and A5 are determined. The other input signal lines of the NOR gates A4 and A5 are L8,
Determined to be L6. In this case, the signal lines L8 and L6
, The voltage value is undecided, so L8 is 0V and L6 is 5V.
Calculated as in the initial state of V. Then, the voltage values of the output signal lines L7 and L8 are determined in that state, and the output values of the NOR gates A4 and A5 are calculated again based on the values. This operation is repeated until the output voltage value does not change. After all, in the converged state, the signal line L
Normal voltage values of 7 and L8 are determined to be 0V and 5V.

Next, the circuit element inputting the signal line L7 is searched from the circuit information of FIG. 5, and the circuit element is determined to be the analog switch A6. Then, from the input / output characteristic of the analog switch A6 stored in the input / output characteristic memory 302, the output for the normal voltage value 0V of the signal line L7 is determined to be 0V, and the normal voltage value of the signal line L9 is determined to be 0V. . In this way, the normal voltage value of each signal line is determined as shown in FIG. These values are stored in the normal voltage value memory 304.

5. Calculation of Fault Voltage Range Next, in step 110, a voltage range that can be distinguished from the normal voltage value of each signal line calculated as described above is determined as a fault voltage range. Assuming that the failure location is one location in the integrated circuit,
When one failure source is set for each signal line, it is defined as a voltage range distinguishable from the normal voltage value in each signal line. For example, it is determined in consideration of an appropriate margin with respect to the normal voltage value. That is, (L1 [0.1,-] L1
[0.1,-]), (L2 [1,-] L2 [1,
-]), (L3 [-, 1] L3 [-, 1], (L3
[2,-] L3 [2,-]), (L4 [4,-] L4
[4,-]), (L4 [-, 3] L4 [-, 3]),
(L5 [-, 4.5] L5 [-, 4.5], (L6
[0.5,-] L6 [0.5,-]), (L7 [0.
5,-] L7 [0.5,-]), (L8 [-, 4.5]
L4 [-, 4.5]), (L9 [0.5,-] L9
[0.5,-]). Here, the voltage range is represented by (signal line number [lower limit voltage value, upper limit voltage value] signal line number [lower limit voltage value, upper limit voltage value]). The signal line number [lower limit voltage value, upper limit voltage value] in the first half means a voltage range based on a failure originally caused in the signal line, and the signal line number [lower limit voltage value, upper limit voltage value] in the latter half is The breakdown voltage range of the origin occurrence defined in the first half means the voltage range when observed on the signal line. It should be noted that only the symbols in the first half are sufficient to determine only the fault voltage range of each signal line, but in order to make the description same as the propagation voltage range described later, the first half and the second half are duplicated as described above. Is described. FIG. 9 shows the fault voltage range of each signal line when the signal line L1 is the specific signal line of the fault origin.

The fault voltage range means, for example, that the signal line L1 has a normal voltage value of 0.05 V, and therefore the fault voltage range is 0, which is more than the normal voltage value of 0.05 V, which is distinguishable from this normal voltage value. It is defined as 0.1V higher than 0.05V. In addition, the signal line L5 has a normal voltage value of 5V.
To 0.5V lower than 4.5V,
The signal line L6 has a voltage range of 0.5 V or higher, which is higher than the normal voltage value of 0 V by 0.5 V.

These fault voltage ranges are stored in the fault state memory 3
It is stored in 05. The fault voltage range of each signal line is obtained by calculation in the above embodiment, but the operator presets each signal line for each input signal set of the test pattern and inputs the value. You may do it.

6. Propagation Analysis Next, by repeating steps 112 to 120, a failure propagation analysis when one input signal set of the test pattern is applied is executed. In step 112, the number J of the signal line originating from the failure is specified as the initial value 1. Next, in step 114, the fault voltage range of the signal line J is propagated toward the output side of the integrated circuit as all other circuit elements are normal except for the fault origin. For example, if J = 1, the signal line L1 is first defined as the specific signal line of the fault origin, and the fault voltage range of the signal line L1 (L1 [0.1,
−] L1 [0.1, −]) is defined as the specific failure voltage range. Then, when the signal line L1 exists in this specific fault voltage range, the voltage range of the circuit element existing on the downstream side, that is, the output of the amplifier A1 is obtained. The voltage range of this output can be determined from the characteristic data of the amplifier A1 stored in the input / output characteristic memory 302. In this case, since the amplifier A1 is an amplifier with a gain of 10, the output voltage range is 1 V or more. If this is described by the above-mentioned symbols, it becomes (L1 [0.1,-] L2 [1,-]). That is, this symbol indicates that the fault voltage range [0.1, −] originally generated in the signal line L1 can be observed as the voltage range [1, −] in the signal line L2.

Since the input / output characteristics of each circuit element are approximated by a plurality of broken lines, when the voltage range to be propagated extends over a plurality of broken lines, the voltage range is divided for each broken line. The propagation calculation is executed for each of the divided voltage ranges.

Next, until it is judged at step 116 that the voltage range on the output signal line L9 of the integrated circuit is obtained,
The analysis of step 114 is repeatedly executed. That is, this voltage range (L1 [0.1,-] L2 [1,-]) is further propagated to the downstream side. The circuit element inputting the signal line L2 is searched from the circuit information of FIG. 5, and the element is determined to be the comparators A2 and A3. The voltage range of the outputs of the comparators A2 and A3 is set to the input / output characteristic memory 30.
2 is calculated by using the characteristic data of the comparators A2 and A3 stored in No. 2. The voltage range of the output of the comparator A2 is L2
0V to 5V for input to the [1,-] inverting terminal
It also becomes. However, since the normal value of the output is 5V, the failure cannot be detected in the voltage range of the signal line L1 which is the origin of the failure and the output is 5V. That is, in this case, the failure does not propagate. Therefore, the output is 4.5V, which can be distinguished from the normal value of 5V.
It becomes possible to detect a fault only in the voltage range of the signal line L1 of the following fault origin, and the voltage in this range is further
It can be propagated to the downstream side as a detectable voltage range.

This range is obtained by using the characteristic data stored in the input / output characteristic memory 302 to calculate the range of the input voltage at which the output becomes 4.5 V or less. In this case, the input voltage range is 1.5 V or more. or,
The output of the comparator A2 becomes 0V for the input in that range. Therefore, the fault voltage range in which the signal line L5 can propagate is (L2 [1.5,-] L5 [0,0]).

Further, the voltage range (L
Since the input / output relationship between the signal line L1 and the signal line L2 is obtained as a straight line from 1 [0.1, −] L2 [1, −]), the failure origin corresponding to L2 [1.5, −] is obtained. The voltage range of the signal line L1 can be obtained by linear interpolation. Therefore, the propagable failure fault voltage range in the signal line L5 converted into the voltage range in the signal line L1 which is the origin of the failure is calculated as (L1 [0.15, −] L5 [0,0]).

By the same calculation, the output of the comparator A3 is calculated, and the propagable fault voltage range in the signal line L6 is calculated as (L1 [0.35,-] L6 [5,5]).

Next, since the fault voltage range in which the signal lines L5 and L6 can propagate is determined, the range of the output voltage is determined in the circuit elements NOR gates A4 and A5 inputting those signal lines. . Circuit element NOR gate A4, A
Reference numeral 5 constitutes a flip-flop circuit in which each output is fed back to other elements. Therefore, with the reset state as the initial state, each circuit element NOR gate A
The outputs of 4 and A5 are calculated. Then, the calculation is executed again for the newly determined output voltage value. This repetitive calculation is executed until the output value does not change. That is, the outputs of the circuit element NOR gates A4 and A5 are 5V and 0V, respectively, with respect to 0V of the signal line L5 and 5V of the signal line L6. This voltage state is the signal line L7,
Since it shows a voltage value opposite to the normal voltage value of L8, failure detection is possible.

However, since fault propagation is possible only when the signal line L7 becomes 5V, in this case, the signal line L6 must be 5V and the signal line L5 must be 0V. In order to satisfy this condition, the fault voltage range in which the signal lines L5 and L6 can propagate must be a common range. Therefore, the fault voltage range in which the faulty signal line L1 in the signal line L7 can propagate is (L1 [0.35,-] L7 [5,5]).
Is decided.

Next, since the voltage range of the signal line L7 has been determined, the analog switch A6 input to the signal line L7 is searched from the circuit information of FIG. According to the characteristic, the voltage range of the signal line L7 is propagated to the signal line L9. Therefore, the voltage range on the signal line L1 originating from the failure on the signal line L9 is (L1 [0.35, −] L9 [5,
5]) is determined.

As described above, the propagated fault voltage range is
The intermediate value is stored in the propagation data memory 306 for each specific signal line and each signal line.

When it is determined in step 116 that the voltage range of the output signal line L9 has been determined as described above, in step 118, the output of the integrated circuit is output by the set of input signals D (I) of the test pattern. The fault voltage range in which a fault can be detected in the fault-origin signal line L1 in which a fault can be detected at the terminal is determined to be L1 [0.35,-]. This voltage range is the detectable voltage range memory 30.
7 is stored corresponding to the number L1 of the signal line originating from the failure. FIG. 10 shows how the fault voltage propagates.

Next, at step 120, it is judged whether or not the failure propagation analysis for all the signal lines as the signal line (specific signal line) of the failure origin has been completed. And
If not completed, the process proceeds to step 122, J is incremented by 1 so that the signal line number J of the specific signal line is set as the next signal line, the process returns to step 114, and the fault voltage for the next specific signal line is returned. Propagation analysis is performed. Then, in step 120, it is repeatedly executed until it is determined that the identification of the failure origin has been executed for all the signal lines. FIG. 11 shows the detectable fault voltage range in each signal line at this time.

Next, when the detectable fault voltage range of all the signal lines is determined, the process proceeds to step 122,
It is determined whether the propagation analysis has been performed for all the input set signals of the test pattern. If not completed, the process proceeds to step 124 and the number I for identifying the input signal set is set.
Is updated by 1 and the process returns to step 108 to perform the above-described propagation analysis for the next input signal set.

In the above embodiment, the input / output characteristic is approximated by a broken line and defined by a function representing the straight line of each broken line. However, the input / output characteristics may be defined by one function or a plurality of functions. In that case, in the voltage propagation analysis, it is necessary to define an inverse function that makes an output correspond to an input in each circuit element.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a test pattern evaluation apparatus according to a specific embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure by a CPU of the apparatus of the embodiment.

FIG. 3 is a flowchart following FIG. 2;

FIG. 4 is a circuit diagram of an example of an integrated circuit that is an operation check target.

FIG. 5 is an explanatory diagram showing circuit information describing an integrated circuit.

FIG. 6 is a characteristic diagram showing input / output characteristics of an amplifier, which is one of circuit elements.

FIG. 7 is a characteristic diagram showing input / output characteristics of a comparator, which is one of circuit elements.

FIG. 8 is a circuit diagram showing a reference voltage value of each signal line of an integrated circuit.

FIG. 9 is a circuit diagram showing a fault voltage range that is a fault source of each signal line.

FIG. 10 is a circuit diagram showing how the fault voltage range of the signal line 1 which is the fault origin propagates.

FIG. 11 is an explanatory view showing a detectable fault voltage range of each signal line finally determined.

[Explanation of symbols]

1 ... CPU 3 ... RAM 8 ... Floppy disk 301 ... Circuit information memory (circuit information storage means) 302 ... Input / output characteristic memory (input / output characteristic storage means) Step 108 ... Calculation means 304 ... Normal voltage value memory (calculation means) Step 110 ... Fault state setting means 305 ... Fault state memory (fault state setting means) Steps 112 to 122 ... Propagation analysis means Step 118 ... Detectable range determining means 307 ... Detectable voltage range memory (detectable range determining means)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical display location 7623-5L G06F 15/60 360 D (72) Inventor Naoya Nakajo, Nagakute-cho, Aichi-gun, Aichi Prefecture 41 Yokochi 1 Toyota Central Research Institute Co., Ltd. (72) Inventor Kohei Hata 1-1, Showa-cho, Kariya City, Aichi Prefecture Nihon Denso Co., Ltd. (72) In-house Osamu Seya 1-1 Showa-cho, Kariya City, Aichi Prefecture No. 1 within Nippondenso Co., Ltd.

Claims (2)

[Claims] 1. An apparatus for evaluating a test pattern input to an integrated circuit in which analog elements and digital elements coexist, in which circuit information including circuit elements of the integrated circuit and connection information between the elements is stored. Circuit information storage means, input / output characteristic storage means for storing input / output characteristics of each element, and one set of input signals of the test pattern,
Calculating means for calculating a normal voltage value in each signal line inside the integrated circuit from the circuit information and the input / output characteristics; and a fault voltage that can be regarded as a fault state for the normal voltage value in each signal line. Failure state setting means for setting a range for each signal line, and a specific failure voltage range which is the failure voltage range of one specific signal line arbitrarily selected from the signal lines set by the failure state setting means When the voltage signal of is propagated to the output side of the integrated circuit by using the circuit information and the input / output characteristics, the output of the circuit element is in the failure voltage range with respect to the normal voltage value in order from the circuit element closer to the specific signal line. In order to exist in the range corresponding to, while limiting the specific failure voltage range, the analysis is sequentially performed toward the output side of the integrated circuit. From the result of propagation at the output of the integrated circuit calculated by the propagation analysis unit and the propagation analysis unit that is changed to An apparatus for evaluating a test pattern of an integrated circuit, comprising: a detectable range determining means for determining a fault voltage range. 2. The test pattern evaluation apparatus according to claim 1, wherein the input / output characteristics of each of the circuit elements stored in the input / output characteristic storage means are divided into a plurality of sections by polygonal line approximation and stored. It is characterized by