JPH0728093A - Active matrix substrate for display - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the pixel aperture ratio of a display active matrix substrate. [Structure] A display active matrix substrate includes pixels 1 arranged in a matrix in the left-right and up-down directions. Each pixel 1 is composed of a thin film transistor TFT, a pixel electrode PXL, and a storage capacitor Cs. The pixel electrode PXL is T
It is connected to the drain D of the FT. One end of the storage capacitor Cs is also connected to the drain D. Storage capacity Cs
The other end of is connected to the capacitance line 2. TFT gate G
Are connected to the gate line 3. The source S of the TFT is connected to the signal line 4. In such a configuration, the capacitance line 2 overlaps the signal line 4 and extends in the column direction. On the other hand, the gate line 3 extends in the row direction orthogonal to the capacitance line 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display active matrix substrate. More specifically, the present invention relates to the structure of a storage capacitor used to hold a signal voltage written in a pixel.

[0002]

2. Description of the Related Art The configuration of a conventional liquid crystal display device assembled using a display active matrix substrate will be briefly described with reference to FIG. This figure is an equivalent circuit diagram corresponding to one pixel arranged in a matrix. Pixel 1
00 (schematically indicated by the area surrounded by the dotted line)
Has a liquid crystal capacitance LC composed of a liquid crystal layer sandwiched between the pixel electrode PXL and the counter electrode COM. A holding capacitor C for holding the image signal written in the liquid crystal capacitor LC.
s are connected in parallel. The storage capacitance Cs is the liquid crystal capacitance L
Since it occupies a part of the pixel 100 including C (the region surrounded by the dotted line), the pixel aperture ratio is sacrificed by this amount. A thin film transistor (TFT) is provided to drive the liquid crystal capacitance LC. The drain D of the TFT is connected to the pixel electrode PXL and one terminal of the storage capacitor Cs. The other terminal of the storage capacitance Cs is connected to the capacitance line 101.
The source S of the TFT is connected to the signal line 102, and the gate G is connected to the gate line 103. In response to the gate signal, the TFT becomes conductive and the image signal is written in the liquid crystal capacitor LC. At this time, an extra charge is stored in the storage capacitor Cs. When the gate signal is released, the TFT is turned off and the written image signal is held. A display active matrix substrate having a storage capacitor is disclosed in, for example, Japanese Patent Publication No. 1-33833.

[0003]

FIG. 5 schematically shows a sectional structure taken along line YY shown in FIG. As shown, an insulating substrate 1 made of quartz or the like
On the surface of 04, an island-patterned polysilicon film is formed and constitutes the element region 105. In the drawing, a TFT is formed on the left side of the element region 105, and a storage capacitor Cs is formed on the right side. TFT is insulating film 1
The gate electrode G is stacked via the gate electrode 06. The gate electrode G is composed of a part of the gate line 103 shown in FIG. A source region S and a drain region D are formed in the element region 105 on both sides of the gate electrode G. The wiring electrode 107 is connected to the source region S. The wiring electrode 107 is the signal line 102 shown in FIG.
It has been extended from. On the other hand, the pixel electrode PXL is connected to the drain region D.

The storage capacitance Cs is composed of a capacitance line 101 which is superposed with an insulating film 106 interposed therebetween. Conventionally, the capacitance line 101 is made of the same film material as the gate line 103, and, for example, polysilicon is used. Since the capacitor line 101 and the gate line 103 are formed of the same film material, the capacitor line 101 is arranged in parallel with the gate line 103 in the row direction. Also, due to the layout of the wiring pattern,
Conventionally, the capacitance line 101 has passed directly below the pixel electrode PXL. The capacitance line 101 is made of polysilicon or the like, is optically opaque, and partially blocks the opening of the pixel electrode PXL. Therefore, in the conventional capacitance line arrangement structure,
There is a problem that the pixel aperture ratio is sacrificed.

[0005]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to improve the pixel aperture ratio by devising the layout of capacitance lines. The following measures have been taken in order to achieve this object. That is, the active matrix substrate for display according to the present invention includes thin film transistors arranged in rows and columns, pixel electrodes arranged in rows and columns connected to the drains of the thin film transistors, and storage capacitors arranged in rows and columns connected to the drains of the thin film transistors. ing. Further, a gate line connected to the gate of the thin film transistor in each row and extended in the row direction, and a signal line connected to the source of the thin film transistor in each column and extended in the column direction,
A capacitor line connected to the storage capacitor of each column and overlapping the signal line and extending in the column direction is provided. Specifically, it includes an element region made of a semiconductor thin film patterned in a predetermined shape, and the capacitance line overlaps a part of the element region via an insulating film to form the storage capacitor. On the other hand, the gate line intersects with the other part of the element region through the insulating film to form the gate of the thin film transistor. More specifically, the element region is made of a first polysilicon layer, the gate line is made of a second polysilicon layer, and the capacitance line is made of a third polysilicon layer.

[0006]

According to the present invention, the capacitance line extends in the column direction and overlaps with the signal line. Therefore, the pixel aperture is not sacrificed because it does not traverse the pixel electrode. On the other hand, in the conventional configuration, the capacitance line is laid out in parallel with the gate line along the row direction. For this reason, the pixel electrode is crossed, and the pixel aperture ratio is sacrificed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing a basic configuration of a display active matrix substrate according to the present invention.
This figure shows an equivalent circuit corresponding to one pixel of an active matrix liquid crystal display device assembled using a display active matrix substrate. Pixel 1 shown
Shows one of those arranged in a matrix in the left-right direction and the up-down direction schematically surrounded by a dotted line. Pixel 1
Includes a thin film transistor (TFT). This TFT is an insulated gate field effect transistor having a gate G, a drain D and a source S. The pixel electrode PXL is connected to the drain D. This pixel electrode PX
A counter electrode COM is arranged facing L in L with a predetermined gap. A liquid crystal layer is interposed between the two to form a liquid crystal capacitor LC. One terminal of the storage capacitor Cs is connected to the drain D of the TFT. The other terminal of the storage capacitor Cs is connected to the capacitance line 2. The gate line 3 is connected to the gate G of the TFT. The signal line 4 is connected to the source S of the TFT.

As shown in the figure, the gate line 3 extends along the row direction. The signal line 4 extends in the column direction orthogonal to this. As a feature of the present invention, the capacitance line 2 overlaps with the signal line 4 and extends in the column direction.

When a gate signal is applied to the gate line 3, TF
T becomes conductive. When an image signal is supplied through the signal line 4 in synchronization with this, signal charges are charged in the liquid crystal capacitor LC via the TFT in the conductive state. A predetermined voltage is applied between the pixel electrode PXL and the counter electrode COM according to the amount of charge, and the transmittance of the liquid crystal layer is changed to display a desired image. At this time, extra signal charges are stored in the storage capacitor Cs. Next, when the gate signal is released, the TFT is turned off and the written image signal is held.
Even if a current leak occurs in the liquid crystal capacitor LC or TFT during this holding period, the charge accumulated in the holding capacitor Cs compensates for this, so that a desired image display can be maintained.

FIG. 2 is a plan view showing a specific structural example of the pixel 1 shown in FIG. As shown in the figure, the portion surrounded by the chain double-dashed line is the pixel electrode PXL. The pattern surrounded by the alternate long and short dash line represents the signal line 4. This signal line 4
The pattern surrounded by the solid line so that it overlaps with the capacitance line 2
Is represented. On the other hand, a pattern surrounded by a solid line arranged so as to be orthogonal to the capacitance line 2 represents the gate line 3. In addition, the area surrounded by the dotted line represents the element region 5. This element region 5 is obtained by patterning a semiconductor thin film into a predetermined shape.

As can be seen from the figure, the capacitor line 2 is extended in the column direction so as to overlap the signal line 4, and is laid out so as not to cross the pixel electrode PXL. Therefore, the pixel aperture ratio is not sacrificed. The capacitance line 2 overlaps with a part of the element region 5 via the insulating film to form a storage capacitance Cs. On the other hand, the gate line 3 is connected to the element region 5 through the insulating film
The gate G of the above-mentioned thin film transistor TFT is formed by intersecting the other part. The drain D of this TFT is connected to the pixel electrode PXL via a contact hole. On the other hand, the source S of the TFT is also electrically connected to the signal line 4 via the contact hole. The contact portion of the source S is laid out so as not to overlap the capacitance line 2.

FIG. 3 is a schematic view showing a sectional structure of the display active matrix substrate shown in FIG. (A)
FIG. 3 is a sectional view taken along line AA shown in FIG. 2. The line AA passes through the drain contact portion of the TFT. Similarly, (B) is B shown in FIG.
It is sectional drawing cut | disconnected along the B line. The line BB passes through the gate section. Similarly (C) is C in FIG.
It is sectional drawing cut | disconnected along the C line. This CC line passes through the source contact portion of the TFT.

To facilitate understanding, the laminated cross-section structure will be described first with reference to FIG. An element region 5 is formed on the surface of an insulating substrate 6 made of quartz or the like. The element region 5 is formed by patterning a first polysilicon thin film into a predetermined shape, for example. The surface of the element region 5 is covered with an insulating film 7. The gate line 3 crosses the element region 5 in the row direction via the insulating film 7. Gate line 3
A gate G of the TFT is formed at the intersection of the element region 5 and the element region 5. The gate line 3 is formed by linearly patterning a second polysilicon thin film, for example. On the gate line 3, the capacitance line 2 is extended in the column direction via the first interlayer film 8. The column direction is perpendicular to the paper surface. The capacitance line 2 is, for example, a line pattern of a third polysilicon thin film. Further, a second interlayer film 9 is formed on the capacitance line 2.
The signal line 4 is extended in the column direction via the. The signal line 4 is formed by linearly patterning a metal thin film such as aluminum.

Next, referring to (A), the capacitance line 2 is in direct contact with the element region 5 via the insulating film 7 and constitutes a storage capacitance Cs. The first interlayer film 8 described above is removed from the storage capacitor Cs. A signal line 4 is arranged in parallel on the capacitance line 2 with a second interlayer film 9 interposed therebetween. On the other hand, the pixel electrode PXL is electrically connected to the drain D of the TFT via a contact hole provided through the first interlayer film and the second interlayer film.

Finally, referring to (C), the extended portion of the signal line 4 is electrically connected to the source S of the TFT through a contact hole. Source S as shown
The contact part has a layout that does not overlap with the capacitance line 2. According to such a laminated structure, the capacitance line 2 overlaps with the signal line 4 and extends in the column direction, so that the capacitance line 2 does not affect the pixel electrode PXL. In order to realize such a laminated structure, as described above, for example, the gate line 3 and the capacitance line 2 are formed by using the polysilicon thin films of different layers. Further, in order to electrically insulate the capacitance line 2 and the signal line 4, an additional second interlayer film 9 is provided.
Will be required.

[0016]

As described above, according to the present invention, the capacitance line is overlapped with the signal line and extends in the column direction. Unlike the conventional structure in which the capacitance line is extended in the row direction in parallel with the gate line, it does not traverse the pixel electrode, so that the pixel aperture ratio can be improved.

[Brief description of drawings]

FIG. 1 is a pattern wiring diagram of a display active matrix substrate according to the present invention.

FIG. 2 is a schematic plan view showing a specific example of a wiring pattern of an active matrix substrate for display according to the present invention.

FIG. 3 is a cross-sectional view showing a laminated structure of a display active matrix substrate according to the present invention.

FIG. 4 is a wiring pattern diagram of a conventional display active matrix substrate.

FIG. 5 is a schematic cross-sectional view showing a laminated structure of a conventional display active matrix substrate.

[Explanation of symbols]

 1 Pixel 2 Capacitance Line 3 Gate Line 4 Signal Line 5 Element Area 6 Insulating Substrate 7 Insulating Film 8 First Interlayer Film 9 Second Interlayer Film TFT Thin Film Transistor Cs Storage Capacitance PXL Pixel Electrode G Gate D Drain S Source

Claims (3)

[Claims] 1. A matrix-arranged thin film transistor, a pixel electrode connected to the drain of each thin film transistor and also arranged in a matrix, a storage capacitor connected to the drain of each thin film transistor and arranged in a matrix, and a row connected to the gate of each thin film transistor. Gate line extending in the direction,
For display, including a signal line connected to the source of the thin film transistor in each column and extending in the column direction, and a capacitor line connected to the storage capacitor in each column and extending in the column direction overlapping with the signal line Active matrix substrate. 2. The gate line includes an element region made of a semiconductor thin film patterned in a predetermined shape, and the capacitance line overlaps with a part of the element region through an insulating film to form the storage capacitor. The active matrix substrate for display according to claim 1, wherein the gate intersects with the other part of the element region through an insulating film to form a gate of the thin film transistor. 3. The display according to claim 2, wherein the element region is made of a first polysilicon layer, the gate line is made of a second polysilicon layer, and the capacitance line is made of a third polysilicon layer. Active matrix substrate.