JPH0728443B2 - Radio control receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention is for a radio control (hereinafter referred to as radio control) system for a radio control system for remotely controlling industrial equipment such as a crane, including models of automobiles, airplanes and the like. The present invention relates to a receiving device.

(Prior Art) A radio-controlled system that controls various steered objects by using FM (frequency modulation) or AM (amplitude modulation) signals of PCM (pulse code modulation) signals or PPM (pulse phase modulation) signals. Are used in various fields.

Conventionally, as a technique in such a field, for example, there is one as shown in FIG. The configuration will be described below.

FIG. 2 is a block diagram showing an example of the configuration of a conventional PCM radio control receiver.

This radio control receiver receives serial signals of a plurality of channels transmitted from a radio control transmitter (not shown),
It has a receiving section 1 for demodulation, and the output side of the receiving section 1 is
Received data S1 which is a serial digital signal from the receiver 1
A sampling pulse generator 2 for generating a sampling pulse S2 synchronized with the sampling pulse S2 and a sampling circuit 3 for sampling the received data S1 based on the sampling pulse S2 and outputting serial or parallel digital signal data S3 are connected. Further, on the output side of the sampling circuit 3, a data decoder 4 for performing data processing using the sampled data S3, and the data processed by the data decoder 4 are used to control a steered motor such as a tape motor. A drive unit 5 that drives the parts is connected.

FIG. 3 is a diagram showing an example of the signal waveform of FIG.

The signal from the transmitter is received and demodulated by the receiver 1 of the receiver, and the received data S1 is formed by repeating one frame of the period Fs consisting of the synchronization pattern S1a and the data portion S1b. Here, the data portion S1b is, as shown in the enlarged waveform of the reception data S1 in FIG.
Let Lb be the minimum length of the high-level (henceforth H-level) or low-level (henceforth L-level) section of the data, the length of Lb × n (however, n = 1,2,3, ...) It is composed of a combination of H level or L level, and switching of H level or L level is always Lb × m (however, m = 1,2,
3, ...) position. Also, the synchronization pattern S1 inserted in the reception data S1 at regular intervals Fs.
It is assumed that a is for separating the data and for distinguishing the contents of the data, and is selected as a pattern that never appears in the data portion S1b.

When such reception data S1 is output from the reception unit 1,
The sampling pulse generation circuit 2 generates a sampling pulse S2 synchronized with each data in the data section S1b in the received data S1 and gives it to the sampling circuit 3. Based on the sampling pulse S2, the sampling circuit 3 receives the receiving section S1.
Sample the data in b. The sampled data S3 is decoded by the data decoder 4, and the decoded signal drives the steered portion of the steered body via the drive unit 5.

FIG. 4 is a block diagram showing a configuration example of the sampling pulse generating circuit 2 and the sampling circuit 3 in FIG.

The sampling pulse generation circuit 2 selects a reference clock generation circuit 10 for generating a reference clock S10, a first frequency divider 11 for outputting a clock S11a and frequency-divided outputs S11b, S11c, and an output S17 for selecting the output S11b or S11c. A clock selector 12 that outputs a signal S12, a second frequency divider 13 that divides the signal S12 and sends an output S2, a D-type flip-flop (hereinafter referred to as D-FF) 14 that captures data by a clock S11a, a clock D-FF15 that takes in the received data S1 by S11a and outputs the data S15, AND gate (hereinafter referred to as AND gate) 16 that takes the logical product of the D-FF14, 15 and output S2 by the output of AND gate 16 It is composed of a D-FF 17 which outputs an output S17. The sampling circuit 3 is composed of an n-bit serial-in / parallel-out shift register 18.

Next, the operation of FIG. 4 will be described with reference to FIG.

The received data S1 received and demodulated by the receiver 1 is D-FF15.
Then, sampling is performed by a clock S11a which is sufficiently smaller than the minimum length Lb of the H or L level section of the data, and the falling of the data S15 (switching from H level to L level) is detected by the AND gate 16 and D-FF14. With respect to the detected fall position of the data S15, the first and second
The D-FF 17 detects whether the output S2 of the second frequency divider 13 having the period Lb divided by the frequency dividers 11 and 13 is in the H level section or the L level section. The original frequency (S12) of the second frequency divider 13 is obtained by the clock selector 12 from the first frequency divider 1
The output S11b or S11c of 1 is selected by the output S17 of the D-FF 17, and by adjusting the clock input to the second frequency divider 13, the period Lb of the second frequency divider 13 is changed. The falling edge of the output S2 is controlled to coincide with the falling edge of the data S15. By using the output S2 adjusted in this way for the sampling pulse of the reception data S1,
I am able to receive and process data correctly. When the shift register 18 for sampling data converts the serial data S15, that is, the received data S1 into the n-bit parallel data S3, the data S3 is subjected to data processing by the data decoder 4 in the subsequent stage.

(Problems to be Solved by the Invention) However, the radio control receiver having the above configuration has the following problems.

When a sampling pulse generation and sampling circuit as shown in Fig. 4 is used, the circuit is only intended to match the phases of the received and demodulated data S1 and the sampling pulse S2. is there
If the reference clocks for setting Lb do not match between the transmitter and the receiver, reception and sampling of the demodulated data S1 become impossible. Then, among various carrier frequencies used for data transmission / reception, the reference clock for setting the data length in the receiving device may cause interference in the receiving unit 1 of the receiving device depending on a certain specific carrier frequency. It is also necessary to shift the reference clock for data length setting on the receiving device side from the reference clock for data length setting on the transmitting device side, but in that case, there is a problem that the radio control receiving device cannot be configured. As a problem that the conventional technology has, in the radio control system, the same reference clock for data length setting must be used on the transmitter side and the receiver side, and the reference clock for data length setting is transmitted. (EN) Provided is a radio control receiver which solves the problem that the device and the receiver cannot be displaced from each other.

(Means for Solving Problems) In order to solve the above problems, the present invention synchronizes with reception data of serial transmission / reception data configured by repeating a frame signal including a synchronization pattern and a plurality of channel data. A sampling pulse generating circuit for generating a sampling pulse, and a sampling circuit for sampling the received data using the sampling pulse,
In a radio control receiver including a data decoder that decodes the output of the sampling circuit and a drive circuit that drives a steered portion of a steered body based on the output of the data decoder, the received data and the sampling pulse generation circuit And a frequency correction circuit for detecting the frequency fluctuation of the frame signal based on the data and correcting the sampling frequency of the sampling pulse generation circuit according to the frequency fluctuation.

(Operation) According to the present invention, since the radio control receiver is configured as described above, in the frequency correction circuit, the reference clock for setting the data length is deviated between the transmitter and the receiver, and the frequency of the frame signal is increased. If fluctuates, it works to correct the sampling frequency according to the fluctuation. As a result, the sampling circuit of the receiving device can accurately sample the data from the transmitting device. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a PCM receiver according to an embodiment of the present invention.

This receiving device has a receiving unit 21 for receiving and demodulating serial signals of a plurality of channels transmitted from a radio control transmitting device (not shown) as in the conventional case, and a sampling pulse generating circuit is provided on the output side of the receiving unit 21. 22 and sampling circuit
Besides 23, a newly added frequency correction circuit 26 is connected. The sampling pulse generation circuit 22 includes a reception unit 21.
Is a circuit that generates a sampling pulse S22a synchronized with the received data S21 by using the received data S21 that is a serial digital signal from the frequency correction circuit 26 and the signal S26 from the frequency correction circuit 26.
This is a circuit for sampling the reception data S21 based on 2a and outputting serial or parallel digital signal data S23. The frequency correction circuit 26 is a circuit that outputs a signal S26 for sampling pulse correction using the received data S21 and the data S22b from the sampling pulse generation circuit 22.

Further, on the output side of the sampling circuit 23, similarly to the conventional case, a data decoder 24 that performs data processing using the sampled data S23, and the data processed by the data decoder 24 A drive unit 25 that drives the controlled area is connected.

In the above configuration, when a signal is transmitted from the radio control transmitting device, the signal is received and demodulated by the receiving unit 21 and is in the form of reception data S21 which is a binary serial signal, the frequency correction circuit 26, the sampling generation circuit. 22 and the sampling circuit 23. In the frequency correction circuit 26, the received data
Based on S21, the difference between the reference clocks of the transmitter and the receiver is detected, and the sampling circuit 23 generates a signal S26 for adjusting the sampling pulse S22a so that the reception data S21 can be sampled correctly, and the sampling pulse generator 22 Give to. Sampling pulse generation circuit
22 uses the signal S26 and the received data S21 to receive the received data S2
A sampling pulse S22a synchronized with 1 is generated and given to the sampling circuit 23. Then, the received data S21
Is sampled by the sampling circuit 23, and the sampled data S23 is decoded by the data decoder 24, and then the driven part drives the controlled part of the controlled object.

FIG. 5 is a block diagram showing a configuration example of the sampling pulse generation circuit 22 and the frequency correction circuit 26 of FIG.

FIG. 5 shows a combination of the sampling pulse generating circuit 22 and the frequency correcting circuit 26 shown in FIG.
Reference clock generation circuit 30 for generating S30, reference clock S
Variable frequency division of 30 is performed and first and second variable frequency dividers 31 and 32 for outputting clocks S31 and S32 respectively, reference clock S30 and received data S21 are input, and the frame frequency of the transmitter is measured to obtain signal S33. And a first counter 34 for counting the frame frequency of the receiving device by inputting the clock S31 and the signal S33. Further, the frequency deviation detection circuit 35 which inputs the output of the first counter 34 and the signal S33, detects the deviation between the frame frequency of the transmitter and the frame frequency of the receiver, and outputs the deviation signal S35, the deviation signal S35 and the signal A division ratio setting circuit 36 that inputs S33 and outputs a signal S36 for controlling the division ratio of the first and second variable frequency dividers 31 and 32, and a clock S3 of the second variable frequency divider 32.
A second counter 37 that generates a sampling pulse S22a using 2 and a sampling pulse S32a and received data S2
There is also provided a phase comparison circuit 38 which performs a phase comparison of 1 and outputs a signal S38 for controlling the frequency division ratio of the second variable frequency divider 32.

Next, the operation of FIG. 5 will be described with reference to the signal waveforms of FIG.

The data S21 received and demodulated by the receiver 21 is input to the synchronization pattern detection circuit 33, and 1 is output as a signal S33 every time the synchronization pattern detection circuit 33 detects a synchronization pattern for separating data. Output pulse. That is, one pulse is output as the signal S33 every frame period Fs on the transmitter side. However, in the pattern detection for synchronization at this time, it is not possible to detect the reception data S23 after sampling using the sampling pulse S22a in a pattern combination of H level and L level. The reason is that the sampling pulse S22a and the reception data S21 are not synchronized at the initial stage of the circuit operation. Therefore, for example, when the H level or the L level continues for a certain section, the synchronization pattern is selected so that the synchronization pattern can be distinguished from the data portion of the received data S21, and the synchronization pattern detection circuit 33 also appears in the data portion. It is necessary to have a circuit that detects a characteristic length of an H or L level that is not present.

The clock S31 is input to the first counter 34 through the first variable frequency divider 31 based on the reference clock S30 on the receiver side, and the first counter 34 determines the cycle FsO of one frame on the receiver side. Counting. Next, using the output of the first counter 34 and the output signal S33 of the synchronization pattern detection circuit 33, the frequency deviation detection circuit 35 detects the difference (Fs-FsO) in the frame period between the transmitter and the receiver, and Fs such that absolute value of period difference (Fs−FsO) | Fs−FsO | approaches zero
The frequency division ratio is set by the signal S36 of the frequency division ratio setting circuit 36 so that the first counter 34 counts O in the next frame, and the first variable frequency divider 31 and the second variable frequency divider 32 are set. The frequency division ratio between the frames next to. The frequency division ratio of the first variable frequency divider 31 is the signal S3.
Every 3 pulses, that is, when the synchronization pattern is detected (cycle Fs)
Is updated to 1st with a constant division ratio during one certain frame.
It means that the counter 34 of is counting the clock S31. FIG. 6 shows an example of the above operation.

FIG. 6 is a diagram for explaining the operation of FIG. 5, in which the horizontal axis represents the time t after the synchronization pattern is detected, and the vertical axis represents the cumulative count number of the first counter 34 in FIG. Has been. Also, the solid line in FIG. 6 shows the cumulative count number at the reference clock on the transmitter side, and the broken line shows the cumulative count number of the first counter 34 in FIG. 5 on the receiver side.
In the example of FIG. 6, an example is shown in which the clock on the receiver side has a higher frequency than the clock on the transmitter side.

The synchronization pattern is detected at time t = 0, and the first counter
34 starts counting, but due to the difference from the reference clock of the transmitter, a deviation of Cs1 = Fs−FsO from the original count occurs at time t = Fs, that is, at the time of detecting the next synchronization pattern. Fifth
The deviation Cs1 is detected by the frequency deviation detection circuit 35 in the figure, and the division ratio setting circuit 36 sets the division ratio in the direction of decreasing the absolute value | Cs1 | of the deviation. Such operation 1
By repeating every frame period Fs, | Cs1 |> | Cs2 |
> | Cs3 |> | Cs4 |> ...
The FsO on the receiver side approaches Fs.

The second one is actually used as the sampling pulse S22a.
Of the counter 37, which corresponds to the conventional second frequency divider 13 of FIG. Although the output of the second variable frequency divider 32 is used as the clock S32 input to the second counter 37, the second variable frequency divider 32 is in phase with the output signal S36 of the frequency division ratio setting circuit 36. The output signal S38 of the comparison circuit 38 is used to increase / decrease the clock S32 supplied to the second counter 37. That is, the signal S36 is used to match the frequency, the signal S38 is used to match the phase with the received data S21,
Actual sampling is possible.

Here, the phase comparison circuit 38 detects the position of the falling edge or the rising edge of the reception data S21 according to the same principle as the conventional technique shown in FIG. 4, and the position is detected by the sampling pulse S22a.
By looking at the H level section or L level section of
The control signal S38 for increasing / decreasing the clock is sent to the second variable frequency divider 32, and the phase of the sampling pulse S22a and the received data S21 is matched.

FIG. 7 is a circuit diagram showing a configuration example of the first and second variable frequency dividers 31, 32 used in FIG.

Since the first and second variable frequency dividers 31 and 32 are composed of the same circuit, for convenience of explanation, one of the first variable frequency divider 31 will be described as an example. The second variable frequency divider 31 is D-FF40,4.
1,42, Exclusive OR gate (hereinafter referred to as ExOR gate) 4
3, 44, 45, AND gates 46, 48, and OR gate 47.

8 (a), (b), and (c) are the signal waveform diagrams of FIG. 7, and FIG. 8 (a) shows the signal S36a = H level and the signal S36b = L.
1/8 frequency division operation at level, signal S36a =
1/4 frequency division operation when H or L level and signal S36b = H level, FIG. 7C shows signal S36a = L level, signal S36b =
The operation without the clock output at the L level is shown.

For example, as shown in FIG. 8A, the signal S36a is set to H level and the signal S36b is set to L level. The first stage D-FF40 is
The H level of the signal S36a is taken in through the ExOR gate 43 at the falling edge of the reference clock S30, and the output signal S40 is held at the H level until the next falling edge of the reference clock S30. When output signal S40 is at H level, AND gate 46 and OR gate 47
Since the input side of each one of the ExOR gate 44 and the AND gate 48 becomes H level, the D-FF 41 in the second stage takes in the H level at the falling edge of the signal S40 in synchronization with the reference clock S30, and the next signal S40. The output signal S41 is held at the H level until the falling edge of. Similarly, the D-FF 42 of the third stage takes in the H level through the AND gate 48 and the ExOR gate 45 at the falling edge of the signal S41 and holds the output signal, that is, the output clock S32 at the H level until the next falling edge of the signal S41. To do. As a result, the reference clock S30 is divided by 1/8.

Therefore, as shown in FIGS. 8B and 8C, the signal S36
By controlling A and S36b, the output clock S32 can be operated as a variable frequency divider with respect to the reference clock S30 by dividing the output clock S32 by 1/8, 1/4, or no clock output.

The embodiment described above has the following advantages.

Since the frequency correction circuit 26 is provided, the radio control system can operate even if the reference clock for setting the data length, that is, the frame frequency of the data deviates between the transmitter and the receiver of the radio control system. Therefore, when the reference clock S30 for setting the data length of the receiving device interferes with the carrier frequency of transmission / reception and the reference clock S30 for setting the data length on the receiving device side must be shifted, or in other designs and implementations. The radio control system can be constructed even when the reference clocks for setting the data lengths of the transmission device and the reception device have to be shifted for some reason in the manufacturing process or part procurement. Furthermore, since the frequency correction circuit 26 performs frequency correction based on the cycle (frame cycle) of the synchronization pattern in the received data S21, the channel data of the data portion can be coded (encoded) relatively freely. There is also.

Although the above embodiment has been described by taking the PCM receiver as an example, the receiver 21 and the data decoder 24 shown in FIG.
It can also be applied to other modulation methods such as the PPM method by changing the internal circuit such as.

(Effect of the Invention) As described in detail above, according to the present invention, since the frequency correction circuit is provided in the sampling pulse generation circuit for sampling the received data, the reference clock for setting the data length is the same as that of the transmitter. In the case where a shift occurs with the receiving device, that is, even if the frame frequency of the data shifts, the data from the transmitting device can be accurately sampled by the sampling circuit of the receiving device.

[Brief description of drawings]

FIG. 1 is a block diagram of a radio control receiver showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional radio control receiver, FIG. 3 is a signal waveform diagram of FIG. 2, and FIG. 2 is a block diagram of the sampling pulse generating circuit and the sampling circuit of FIG. 2, FIG. 5 is a block diagram of the sampling generating circuit and the frequency correction circuit of FIG. 1, and FIG. 6 is an operation explanatory diagram of FIG. FIG. 7 is a circuit diagram of the first and second variable frequency dividers of FIG. 5, and FIGS. 8 (a), (b), and (c) are signal waveform diagrams of FIG. 21 …… Reception part, 22 …… Sampling pulse generation circuit, 23
...... Sampling circuit, 24 …… Data decoder, 25 ……
Drive unit, 26 ... frequency correction circuit, 30 ... reference clock generation circuit, 31, 32 ... first and second variable frequency dividers, 33 ... synchronization pattern detection circuit, 34, 37 ... first , Second counter, 3
5: Frequency deviation detection circuit, 36: Dividing ratio setting circuit, 38
...... Phase comparison circuit.

Claims (2)

[Claims] 1. A sampling pulse generating circuit for generating a sampling pulse in synchronization with received data of serial transmission / reception data composed of repetition of a frame signal composed of a synchronization pattern and a plurality of channel data, and the sampling pulse. Radio control reception including a sampling circuit for sampling the received data using the data decoder, a data decoder for decoding the output of the sampling circuit, and a drive circuit for driving a steered portion of a steered body based on the output of the data decoder. The apparatus is provided with a frequency correction circuit that detects a frequency fluctuation of the frame signal based on the received data and the data of the sampling pulse generation circuit, and corrects the sampling frequency of the sampling pulse generation circuit according to the frequency fluctuation. Radio controlled character Receiver for mobile phones. 2. The sampling pulse generation circuit and the frequency correction circuit, a reference clock generation circuit for generating a reference clock of a predetermined cycle, and a first and second variable frequency divider for performing variable frequency division of the reference clock. A first counter for counting the frequency of the frame signal in the received data using the output of the first variable frequency divider; and a synchronization pattern detection circuit for measuring the frequency of the frame signal in the transmitted data, A frequency deviation detection circuit for detecting a deviation between a frame signal frequency of transmission data and a frame signal frequency of the reception data; and the first and second deviations based on the deviation of the frame signal frequency.
A frequency division ratio setting circuit for controlling the frequency division ratio of the variable frequency divider, a second counter for generating a sampling pulse using the output of the second variable frequency divider, the sampling pulse and the reception data 2. The radio control receiver according to claim 1, further comprising: a phase comparison circuit that controls the frequency division ratio of the second variable frequency divider by performing the phase comparison of 1.