JPH07296524A - Digital data playback device - Google Patents

Abstract

PURPOSE:To reduce a decision error for a multi-valued signal and to provide binary information with a low error rate by providing a viterbi decoding circuit of a maximum likelihood decoding means in a quantization feedback equalizer of a reproducing side. CONSTITUTION:An original reproducing code is obtained estimating by the viterbi decoding circuit 46A in the quantization feedback equalizer 27 based on the multi-valued signal S12 inputted through an equalizer of a waveform equalization means and an A/D conversion circuit 25. An envelope extraction circuit 31, low-pass filters(LPF) 33, 35 and a feedback voltage generation circuit 34 constituting a DC reproducing means input a reproducing code and the multi- valued signal S11 by the viterbi decoding circuit 46A and generate a lost DC component S21 to output it to an addition circuit 32. The addition circuit 32 corrects a low band cutoff characteristic adding the DC component 21 to the multi-valued signal S11, and the viterbi decoder 47 obtains the binary information S15 from the corrected multi-valued signal S14 to output it. Thus, the binary information with the error rate further lower than as usual is obtained.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology (FIG. 8) Problem to be Solved by the Invention (FIGS. 9 to 13) Means for Solving the Problem (FIGS. 1 and 7) Action Example (FIGS. 1 to 7) (1) First Example (FIGS. 1 to 6) (1-1) Overall Configuration (FIG. 1) (1-2) Configuration of Quantization Feedback Equalizer (FIGS. 2 to 5) (1-2) -1) Overall configuration (Figs. 2 and 3) (1-2-2) Configuration of envelope extraction circuit (Figs. 4 and 5) (1-3) Reproducing operation (Fig. 6) (2) Second embodiment (FIG. 7) (2-1) Configuration and Operation of Quantization Equalizer (FIG. 7) (3) Other Embodiments Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data reproducing apparatus, and is suitable for application to, for example, decoding a partial response code in which a reproduced signal waveform is a ternary waveform.

[0003]

2. Description of the Related Art Conventionally, helical scan system digital video tape recorders (hereinafter referred to as digital VTRs) and digital audio tape recorders (hereinafter referred to as DAs) are used.
As the recording code (referred to as T), a recording code in which the eye pattern of the reproduction signal has a binary waveform as shown in FIG. 8 is adopted.

However, the scrambled NRZ (non
While this type of recording code represented by a return to zero code has an excellent signal-to-noise ratio (SN ratio),
It is characterized by being easily affected by low-frequency cutoff. Therefore, in the digital VTR, a quantizing feedback equalizer is provided on the reproducing side to compensate for the low frequency cutoff of the reproduced signal.

[0005]

By the way, in recent years, it has been considered to employ a personal response code, which has few low-frequency components and is suitable for high-density recording, as a recording code of a digital VTR. This partial response code is a recording code in which the eye pattern has three values as shown in FIG. 9, and an interleaved NRZI code is known as this type of code. Generally, there is no example of providing a quantizing feedback equalizer on the reproducing side in a digital VTR which reproduces this kind of code, but in order to further reduce the occurrence of code errors, if the reproducing signal is passed through the quantizing feedback equalizer It is possible to further reduce errors.

First, let us consider that the quantization feedback equalizer currently used in a digital VTR for reproducing a reproduction signal whose eye pattern is binary is applied as it is. Figure 10
The quantized feedback equalizer 1 is shown in FIG. Quantization feedback equalizer 1
Compensates the low frequency component S2 lacking in the reproduced RF signal S1 reproduced via the magnetic head in the adder circuit 2 and outputs the compensated ternary signal S3 from the output end. At this time, it is assumed that the low frequency component is generated based on the pulse series received up to the present time.

The low frequency component S2 is generated as follows. First, the ternary signal S3 is input to the comparator 3, and the signal level is at "H" level (hereinafter referred to as +1 level), at intermediate level (hereinafter referred to as 0 level), or "L".
It is detected whether it is a level (hereinafter referred to as -1 level).
The comparator 3 outputs detection outputs S4A to S4C based on the detection result.
Is output, and any one of the switches SW1, SW2, and SW3 is controlled to the ON state by the three detection outputs S4A to S4C.

The input terminals of these three switches SW1 to SW3 are respectively code values ("+1", "0", "-").
1 ”) is applied from the reference voltage source. Therefore, one of these three voltages is applied to the low-pass filter 4 as the feedback signal voltage S5 from the switches SW1 to SW3. The low-pass component S2 is obtained by passing the feedback signal voltage S5 through the low-pass filter 4.

However, the signal level of the reproduction RF signal S1 is apt to change due to a track linearity error or the like. On the other hand, the signal level of the feedback signal voltage S5 given to the low-pass filter 4 is always constant. Therefore, when the reproduction RF signal S1 has a large attenuation amount, the feedback amount becomes excessive.
Therefore, when the signal level of the feedback signal voltage S5 is fixed, an automatic gain control circuit (hereinafter referred to as AGC (auto gain)
It is necessary to adjust so that the feedback amount of the DC component does not become excessive by using the (n control) circuit) together.

An example of a circuit using an AGC circuit in this quantized feedback equalizer is shown in FIG. 11 in which parts corresponding to those in FIG. This quantization feedback equalizer 5 is an AGC circuit 6
Thus, the ratio of the feedback signal voltage S5 to the reproduction RF signal S1 is controlled to be constant by amplifying or attenuating the signal level of the reproduction RF signal S1.

At this time, in order to properly adjust the signal level of the reproduction RF signal S1 by the AGC circuit 6, it is necessary to properly detect the signal level of the reproduction RF signal S1. For this purpose, the envelope waveform of the reproduction RF signal S1 obtained by integration and equalization is obtained, and the reproduction RF signal S1 is correspondingly obtained.
It becomes necessary to adjust the amplitude of. As such an envelope detection circuit, there is a conventional one shown in FIG.

The manner in which the binary waveform envelope waveform is obtained by this circuit is shown in FIGS. 12 (B) to 12 (E). First, the reproduction RF signal S1A is sampled by the first-stage analog digital conversion circuit 11, and the AD conversion output S1B is output to the rectification circuit 12. Subsequently, the AD conversion output S1B is rectified by folding it back with the center level of the amplitude value as a reference, and the rectification result is given to the low-pass filter 13 as a rectification output S1C. The signal from which the high frequency component is removed by passing through the low pass filter 13 is the envelope output S1D.

However, when the reproduced RF signal S1A having a ternary waveform is input to this circuit and the envelope waveform is obtained as in the case of the binary waveform, as shown in FIG. 13, the output waveform of the envelope output S1D is the actual envelope. There was a problem that it was smaller than the waveform. Also, envelope output S1
There was a possibility that undulations would remain on D.

This is the AD conversion output output S in the rectifier circuit 12.
When rectifying 1B, 0 which is almost the center level of the amplitude
This is because the level signal component remains as a low level signal component. That is, the integral value of the signal component of 0 level is reduced. Further, since the integral value becomes small, the envelope output S1D is easily affected by the swell. Therefore, when inputting the reproduction signal of the ternary waveform to the quantization feedback equalizer 5, FIG. 12 (A) and FIG. 13 (A)
It is not suitable to use the envelope output obtained by using the circuit shown in (4) as it is as the reference voltage of the AGC circuit or the comparison circuit.

Generally, as the recording density is increased, the SN ratio of the reproduced signal tends to decrease. When a reproduction signal having a small SN ratio is input to the quantization feedback equalizer, many errors occur in the output of the comparison circuit, and the low frequency component of the signal containing many errors is fed back to the input side of the comparison circuit. become.
When the low-frequency component containing an error is fed back to the comparison circuit in this way, the comparison result becomes more and more erroneous.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a digital data reproducing apparatus capable of reducing the determination error for a multilevel signal as compared with the conventional case.

[0017]

In order to solve such a problem, in the present invention, a waveform equalizing means (24) for equalizing and outputting a multilevel signal reproduced from a recording medium and a waveform equalizing means ( 24) the waveform-equalized multilevel signal (S1
1) is input, and the maximum likelihood decoding means (46A) that estimates the original reproduction code based on the multilevel signal (S11) and the multilevel signal (S11) that has been reproduced code and waveform equalization are input, DC regeneration means (31), (3) for generating a DC component (S21) lost in the waveform-equalized multilevel signal (S11).
3), (34), (35) and an addition means for adding a DC component (S21) to the waveform-equalized multi-level signal (S11) and correcting the low frequency cutoff characteristic of the multi-level signal (S11). (3
2) and the multilevel signal (S14) whose low-frequency cutoff characteristic has been corrected by the adding means (32) are input, and the multilevel signal (S)
Comparison means (4) for obtaining binary information (S15) from 14)
7) and are provided.

Further, in the present invention, a waveform equalizing means (24) for waveform-equalizing and outputting a multi-valued signal reproduced from a recording medium, and an envelope waveform (S17) from the waveform-equalized multi-valued signal (S11). ), And a feedback signal generation circuit (31) for generating a plurality of feedback signal voltages that the multilevel signal (S11) waveform-equalized at each time point can take based on the envelope waveform (S17). 33) and (34) and a selection circuit (3) that outputs a feedback signal voltage (S20) selected from a plurality of feedback signal voltages.
4), a low-pass filter (35) that generates a DC component from the feedback signal voltage (S20) input from the selection circuit (34), and a DC component (S21) to the waveform-equalized multilevel signal (S11). The addition means (32) for adding and correcting the low frequency cutoff characteristic of the multilevel signal (S11) and the multilevel signal (S14) having the low frequency cutoff characteristic corrected by the addition means (32) are input. , And comparison means (28) for obtaining binary information (S15) from the multi-valued signal (S14).

[0019]

The original reproduction code is estimated and obtained by the maximum likelihood decoding means (46A) based on the multilevel signal input through the waveform equalization means (24), and the multivalued code is obtained based on this reproduction code. The DC component (S21) lost from the signal is generated and corrected. At this time, the reproduced code is obtained by using the maximum likelihood decoding means (46A), so that the error contained in the fed back DC component can be reduced. As a result, it is possible to obtain binary information having a much lower error rate than the conventional one.

Further, since the DC component (S21) to be fed back is generated based on the envelope waveform (S17) of the multilevel signal, it is possible to effectively reduce the possibility that the feedback amount becomes excessive. At this time, the DC component (S
The reduced cutoff characteristic can be effectively reduced by setting the pass characteristic of the low-pass filter (35) for generating 21) to the reverse characteristic of the low range cutoff characteristic of the rotary transformer.

Further, a multilevel signal (S
Comparison means (2) for obtaining binary information (S15) from 14)
By adopting the maximum likelihood decoding method in 8) and (47), the identification accuracy can be further improved. When the envelope waveform is extracted, the rectified output (S21A) obtained by rectifying the multilevel signal (S11) is compared with the DC component (S22) included in the rectified output (S21A) to obtain the rectified output (S2).
1A) is discriminated between the non-zero signal portion and the zero signal portion, and in the zero signal portion, the voltage level of the non-zero signal portion that is held at the previous value is output instead of the rectified output (S21A) to output the multilevel signal ( The true envelope waveform (S17) in S11) can be obtained. As a result, the DC component (S21) having an appropriate magnitude can be fed back.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment (1-1) Overall Structure In FIG. 1, 20 is a digital VTR or DA as a whole.
The reproduction system of T is shown. The reproducing system 20 equalizes a reproduced signal reproduced from the magnetic tape 21 into a signal having a ternary eye pattern, and then performs signal processing. In this embodiment, the partial response (1, 1) (hereinafter PR
Equalize to the (1,1) system code.

First, the reproducing system 20 reproduces the reproduced signal reproduced from the magnetic tape 21 via the head system 22.
3 and amplifies the waveform, and supplies it to the equalizer 24 for waveform equalization. Here, the head system 21 is formed by a magnetic head 21A and a rotary transformer 21B.

The reproduction RF signal S11 equalized into a three-valued waveform by the equalizer 24 is given to an analog digital conversion circuit 25 (hereinafter referred to as A / D conversion circuit 25), and the reproduced RF signal S11 is supplied to the analog digital conversion circuit 25.
The value is converted into an AD conversion output S12. At this time A / D
The conversion circuit 25 is a PLL (phase locked l).
loop) clock pulse S regenerated by circuit 26
13 is used.

The quantized feedback equalizer 27 is the A / D conversion circuit 2
The AD conversion output S12 is input from 5 and the low frequency cutoff characteristic deteriorated by the rotary transformer 22B is corrected. The low-frequency compensated reproduction signal S14 having a ternary waveform adjusted to an appropriate signal level by this correction is output to the comparison circuit 28.

The comparison circuit 28 compares the low frequency compensation reproduction signal S14 with a predetermined threshold value and decodes it into binary data S15. After that, the reproduction system 20 corrects the error of the binary data S15 by the demodulator 29, and the corrected reproduction data S16 is corrected.
Is processed in the digital signal processing circuit 30 in the subsequent stage.

(1-2) Structure of Quantization Feedback Equalizer (1-2-1) Overall Structure Next, FIG. 2 shows the internal structure of the quantization feedback equalizer 27.
The quantized feedback equalizer 27 is an envelope extraction circuit 3 capable of accurately extracting envelope information from a ternary reproduced waveform.
1 is built in. That is, the quantized feedback equalizer 27 adjusts the signal level of the ternary voltage fed back to the AD conversion output S12 based on the extraction result of the envelope extraction circuit 31, to thereby convert the AD conversion output S12.
The ratio of the three-valued voltage with respect to is controlled to be constant. As a result, even when the amplitude of the reproduced digital signal S12 is attenuated, the feedback amount of the low frequency component is controlled to an appropriate amount, and the discriminating power in the comparison circuit 28 can be improved.

First, the overall structure of the quantization feedback equalizer 27 will be described. The quantization feedback equalizer 27 supplies the input AD conversion output S12 (FIG. 3A) of the ternary waveform to the adder circuit 32 and the envelope extraction circuit 31, respectively. The envelope extraction circuit 31 extracts an envelope from the AD conversion output S12 and outputs it as an envelope output S17 to the low-pass filter 33. Low pass filter 33
Converts the envelope output S17 into an envelope signal S18 having a smooth waveform (FIG. 3 (B)), and supplies this envelope signal S18 to the feedback voltage generation circuit 34.

The feedback voltage generation circuit 34 uses the envelope signal S18 as it is as a +1 level, uses the polarity inversion signal S19 which is the inverted polarity thereof as a -1 level, and further uses the ground potential as a 0 level. As a result, a three-valued voltage (+1 level, 0 level, -1 level) that increases or decreases according to the amplitude fluctuation of the digital signal S12 is generated. The digital feedback voltage generation circuit 34 selects any one of the three-valued voltages (+1 level, 0 level, -1 level) by the switches SW1 to SW3, and outputs it to the low pass filter 35 as a feedback signal voltage S20.

The low pass filter 35 has a feedback signal voltage S2.
The low frequency component reproduced by integrating 0 is given to the adding circuit 32 as the low frequency component S21. By the way, the signal passing characteristics of the low pass filter 35 are
In the case of this embodiment, the low-frequency cutoff characteristic of the rotary transformer is set to the opposite characteristic. Therefore, a signal having an inverse characteristic with respect to the low-frequency cutoff characteristic of the rotary transformer is fed back to the AD conversion output S12. As a result, from the output terminal of the adder circuit 31, a low-frequency compensation reproduction signal S14 in which the sag of the AD conversion output S12 is compensated is obtained.

Incidentally, the low-frequency compensation reproduction signal S14 is output from the quantization feedback equalizer 27 to the comparison circuit 28 in the subsequent stage,
It is given to the comparison circuit 36 provided inside the quantization feedback equalizer 27. The comparison circuit 36 uses the low-frequency compensation reproduction signal S
By comparing 14 with two threshold values, the low-frequency compensated reproduction signal S14 has a ternary level (+1 level, 0 level-
1 level), and the detection output S22
Switches SW1-S based on A, S22B, S22C
It is designed to close one of the W3s to the on state.

(1-2-2) Configuration of Envelope Extraction Circuit The envelope extraction circuit 31 used in this embodiment is constructed as shown in FIG.
An envelope output S17 that is faithful to the envelope waveform of the signal S11 can be obtained. Below, this is shown in FIG.
Will be explained. Incidentally, in the case of this embodiment, the amplitude of the reproduction RF signal S11 is ± 1 [V] during normal reproduction, as shown in FIG. 5, but there is a period during which it is temporarily attenuated to ± 0.5 [V]. There is.

First, the envelope extraction circuit 31 receives the AD conversion output S12 (FIG. 5) input from the A / D conversion circuit 25.
(C)) is rectified by the rectifier circuit 37, and a rectified signal S21A (FIG. 5D) folded back with 0 [V] as a reference is obtained. The amplitude of the rectified signal S21 corresponds to the amplitude of the AD conversion output S12. Therefore, the amplitude during normal reproduction is 1 [V] or 0 [V], and the amplitude during attenuation is 0.5 [V]. The process from this point onward is a process peculiar to the envelope extraction circuit 31.

That is, the envelope extraction circuit 31 does not output the low frequency component S22 of the rectified signal S21A passing through the low pass filter 38 as an envelope output as it is, but during the 0 level section of the reproduction RF signal S11.
The previous value hold value of the rectified signal S21 is set to the envelope output S
It is output as 17. At this time, the voltage held in each period is the maximum amplitude itself in the ± 1 level section, and the output connected to this maximum amplitude is the rectified signal S2.
1 is the envelope waveform itself.

Thus, detecting the 0 level section of the reproduction RF signal S11 is an important process. Therefore, the envelope extraction circuit 31 uses the smoothed output S22 (FIG. 5 (E)) increased or decreased by the coefficient multiplier 39 as a threshold,
The comparator 40 compares this threshold value with the rectified signal S21A. The 0 level section can be detected by this comparison for the following reason.

The amplitude of the rectified signal S21A is 1 [V] or 0 [V] during the period in which the reproduced RF signal S11 is normally reproduced, and the output DC component of the smoothed output S22 output from the low-pass filter 38 is approximately. 0.5 [V]
Becomes On the other hand, a reproduction RF signal S11 is generated due to reproduction abnormality or the like.
The amplitude of the rectified signal S21A is 0.5 [V] or 0 [V] in the period in which the amplitude of V is attenuated to ± 0.5 [V],
The output DC component of the smoothed output S22 output from the low-pass filter 38 is approximately 0.25 [V].

As described above, the voltage of the smoothed output S22 is too low for the envelope output, but follows the amplitude fluctuation of the reproduction RF signal S11. In this way, the smoothed output S22 stores the information on the amplitude fluctuation. Therefore, in this embodiment, it is used as the threshold value of the comparator 40. By the way, the smoothed output S22 is given to the comparator 40 after being multiplied by a predetermined value (k times) by the coefficient multiplier 39.

For example, in the case of DAT, the coefficient k is set to 1.67. This is the value set for the following reasons. In DAT, 8-1 is used as the block code at the time of recording / reproducing.
Since the 0 conversion is used, the reproduction RF signal S11 is PR (1,
1), the appearance ratios of ± 1 and 0 are about 0.
It becomes 6: 1. Therefore, the output DC voltage after passing the reproduction RF signal S11 of DAT through the rectifier circuit 37 and the low-pass filter 38 is strictly 0.3. Comparison circuit 40
Since the threshold value of 0.5 is desirable to be 0.5, the value of the coefficient k may be set to 1.67 in this case.

It goes without saying that the value of the coefficient k has a value suitable for the conversion code of the block code to be adopted. Further, the value of the coefficient k does not require so high accuracy, and in the case of DAT, setting the value of the coefficient k to 1.5 is sufficiently practical. Further, when the SN ratio of the reproduced RF signal is high, the coefficient k may be 1.0.

The comparator 40 compares the threshold value (smoothed output S22 × coefficient multiple k) set in this way with the rectified signal S21A, and in the section where the rectified signal S21A is larger than the threshold value, the logic "H". Comparison output S23 which rises to
(F)) is output. That is, the signal level of the reproduction RF signal S11 is 0 in the logical "L" section of the comparison output S23.
Correspond when level.

The latch circuit 41 uses this comparison output S23 as a latch enable signal. Therefore, the latch circuit 4
1 is the rectification signal S when the latch enable signal is at "H" level (the logic level of the comparison output S23 is "H" level).
The amplitude of the "H" level of 21A is latched, and the previous value level is held when the latch enable signal is "L" level (the logic level of the comparison output S23 is the logic "L" level). As a result, the envelope output S17 (FIG. 5G) in which the 0 level section of the reproduction RF signal S11 is masked is obtained.

The envelope output S17 is used as a low-pass filter 3 provided at the subsequent stage of the envelope extraction circuit 31.
0 of the reproduction RF signal S11 by passing 3
The net envelope output S18 (FIG. 5 (H)) excluding the level section can be obtained.

(1-3) Reproduction Operation The reproduction operation of the reproduction system 20 used for the digital VTR or DAT in the above configuration will be described. Here, FIG.
The reproduction RF signal S11 reproduced from the magnetic tape 21 via the head system 22 will be described separately for the case where the low frequency cutoff is included and the case where the low frequency cutoff is included. By the way, Fig. 6 (A) shows the reproduction RF in an ideal state without low frequency cutoff.
6B is a signal waveform of the signal S11, and FIG. 6B shows a signal waveform of the reproduction RF signal S11 in which sag has occurred due to lack of low frequency components due to low frequency cutoff.

Reproduction RF reproduced via the head system 22
The signal S11 is input to the A / D conversion circuit 25 via the head amplifier 23 and the equalizer 24 in this order, and is sampled in the A / D conversion circuit 25 at the timing indicated by a circle. At this time, when the reproduction RF signal S11 in which sag is generated as shown in FIG. 6B is A / D converted,
The reproduced digital signal S12 shown in (C) is obtained. Incidentally, the dotted line in the figure is the threshold value of ± 0.5 in the comparison circuit 28.

As can be seen from this figure, as the signal level of the reproduced RF signal S11 deviates from the original signal level due to the sag, the signal level of the reproduced digital signal S12 deviates. Therefore, the signal level of the reproduced digital signal S12, which is originally -1 level, is -0.5.
There is a portion that exceeds the threshold value of or a portion where the signal level of the reproduction digital signal S12 which is originally 0 level exceeds the threshold value of +0.5. If the reproduced digital signal S12 is directly input to the comparator 28 and the signal level is judged, a ternary signal shown in FIG. 6D is obtained, and a judgment error occurs in the shaded portion.

Therefore, the reproduced digital signal S12 is input to the quantization feedback equalizer 27 to compensate for sag due to low frequency cutoff. First, the quantized feedback equalizer 27 inputs the reproduced digital signal S12 whose signal level has changed due to sag to the rectifier circuit 37 of the envelope extraction circuit 31 to obtain the rectified signal S21A. Then, the latch enable signal is generated by comparing the rectified signal S21A with the smoothed output S22 obtained by smoothing the rectified signal S21A.

Then, the latch circuit 41 is controlled on the basis of this latch enable signal to reproduce the digital signal S21.
In the 0 level section, the envelope output S17 that does not include the 0 level is obtained by holding the amplitude value of the +1 level or the -1 level at the previous value. Based on the envelope output S17, the feedback voltage generation circuit 34 generates a ternary feedback voltage signal S20 (FIG. 6 (G)) having the same amplitude as the reproduced digital signal S12.

The feedback voltage signal S20 is converted into a low frequency component through the low pass filter 35. Here, since the characteristic of the low pass filter 35 is set to the inverse characteristic of the low frequency cutoff characteristic of the rotary transformer, the output is output. The low frequency component S21 (FIG. 6 (G)) output from the end is the reproduction RF signal S1.
It is equal to the low frequency component lacking in 1. The correction amount is appropriate because the low-frequency component S21 increases / decreases in accordance with the amplitude fluctuation of the reproduction RF signal S11. Therefore, when the low frequency component S21 is added to the reproduction RF signal S11 by the adder circuit 32, a low frequency compensation signal S14 in which sag is reduced by compensation is obtained as shown in FIG. 6 (E).

Since the sag is reduced in this way, the judgment in the comparison circuit 28 becomes accurate, and a demodulated signal having a correct signal level can be obtained as shown in FIG. 6 (F). The comparison circuit 28 obtains the binary data S15 based on this signal and supplies it to the demodulator 29. This binary data S15 is subjected to 10-8 conversion and error correction in the demodulator 29 and processed in the digital signal processing circuit 30 in the next stage. Then, the musical sound is reproduced from the speaker at the final stage.

According to the above configuration, the ternary feedback voltage signal S20 is input to the low pass filter 35 having the reverse characteristic of the rotary transformer, and the low frequency component S21 generated by the low pass filter 35 is reproduced as the reproduction digital signal S12. By adding it to (that is, the reproduction RF signal S11), it is possible to compensate for the insufficient DC component due to the low-frequency cutoff characteristic of the rotary transformer. As a result, it is possible to further reduce the determination error during reproduction of the partial response code.

Further, the three-valued feedback voltage signal S20 is generated by the envelope signal S18 of the reproduction digital signal S12 (that is, the reproduction RF signal S11) and its polarity inversion signal S19 and 0 [V]. By doing so, the magnitude of the feedback voltage can always be controlled to an appropriate amount. As a result, the influence of the amplitude fluctuation can be reduced, and the code identification accuracy can be further improved.

Further, when the envelope signal S18 is generated, the reproduction RF signal S12 (that is, the reproduction RF signal S11) is compared by comparing the rectified signal S21 of the reproduction digital signal S12 (that is, the reproduction RF signal S11) and its smoothed output S22. 0 level is discriminated, and within this 0 level part ±
The envelope signal S18 is generated by holding the output voltage of the 1-level portion at the previous value. As a result, it is possible to effectively eliminate the possibility that the envelope waveform is detected smaller than the actual signal waveform due to the presence of the 0 level portion and the possibility that the swell component remains. As a result, the code identification accuracy can be further improved.

(2) Second Embodiment In FIG. 7 in which parts corresponding to those in FIGS. 1, 2 and 4 are designated by the same reference numerals, the reproducing system 45 uses a Viterbi decoding circuit in the comparison circuit part. It has the same configuration except for.
Here, the quantization feedback equalizer 46 and the Viterbi decoding circuit 47 will be mainly described.

(2-1) Configuration and Operation of Quantization Equalizer As shown in FIG. 7, the quantization feedback equalizer 46 directly inputs the reproduced digital signal S12 to the Viterbi decoding circuit 46A,
Based on the decoding result of the Viterbi decoding circuit 46A, any one of the switches SW1 to SW3 of the feedback voltage generating circuit 34 is switched and operated. Further, the quantized feedback equalizer 46 gives the reproduced digital signal S12 to the adder circuit 32 via the delay circuit 46B, and the reproduced digital signal S12 and the low frequency component S added in the adder circuit 32.
It is designed to match the time with 21.

This means that the Viterbi decoding circuit 46A generally uses a number of
This is because, since a shift register of several tens of bits is built in, several to several tens of clocks are required for the comparison result to appear on the output side after the reproduction digital signal S12 is input.
In this way, the delay circuit 46B can absorb the time difference between the reproduced digital signal S12 and the low-frequency component S21, so that the feedback operation can be correctly operated.

Further, the envelope signal S extracted through the envelope extraction circuit 31 and the low-pass filter 32.
By selecting the ternary signal level generated on the basis of 18 based on the demodulation result of the Viterbi decoding circuit 46A, reproduction is performed as compared with the case where the ternary signal level is selected using a normal comparison circuit. Even if the SN ratio of the RF signal S11 (that is, the reproduced digital signal S12) is low, the feedback signal voltage S
It is possible to further reduce the code error contained in 20.

Moreover, the low-frequency compensated reproduction signal S14 output from the quantization feedback equalizer 46 is input to the Viterbi decoding circuit 47, and the Viterbi decoding circuit 47 outputs the binary data S1.
By converting to 5, the code error can be further reduced. This makes it possible to realize a reproduction system 45 of good quality.

(3) Other Embodiments Although the PR (1,1) code has been described in the above embodiment, the present invention is not limited to this, and PR (1,-) is used.
1) It can be widely applied to the case of reproducing a signal recorded by another partial response code such as a code or PR (1, 0, -1) code.

In the above embodiment, the case where the recording code having the ternary eye pattern is reproduced is described, but the present invention is not limited to this, and the recording code having the ternary or more eye pattern. It can be widely applied when playing.

Further, in the above embodiment, the quantized feedback equalizer 27 in which the envelope extraction circuit 31, the feedback voltage generation circuit 34 and the low pass filter 35 are combined,
Although the case of using 45 has been described, the present invention is not limited to this, and can be widely applied to other circuits combining these and a reproducing system having a quantizer equalizer including one of these circuits.

Further, although the helical scan type digital tape recorder has been described in the above embodiments, the present invention is not limited to this, and can be widely applied to other types of digital tape recorders and other digital data reproducing devices. .

[0063]

As described above, according to the present invention, the original reproduction code is estimated by the maximum likelihood decoding means on the basis of the multilevel signal input via the waveform equalizer, and this reproduction code is obtained. On the basis of this, the DC component lost from the multilevel signal is generated and corrected during reproduction, so that the error of the fed-back DC component can be reduced. This makes it possible to further reduce the error rate included in the binary information as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital data reproducing apparatus according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a quantization feedback equalizer.

FIG. 3 is a signal waveform diagram showing a method of generating a feedback signal voltage using an envelope signal.

FIG. 4 is a block diagram showing a configuration example of an envelope extraction circuit.

FIG. 5 is a signal waveform diagram showing an envelope waveform extraction process.

FIG. 6 is a signal waveform diagram showing an envelope waveform extraction process.

FIG. 7 is a block diagram showing a configuration example of a quantized feedback equalizer.

FIG. 8 is a signal waveform diagram for explaining an NRZ code.

FIG. 9 is a signal waveform diagram for explaining a partial response code.

FIG. 10 is a block diagram for explaining a conventionally used quantized feedback equalizer.

FIG. 11 is a block diagram for explaining a conventionally used quantization feedback equalizer.

FIG. 12 is a signal waveform diagram showing an envelope waveform extraction process.

FIG. 13 is a signal waveform diagram showing an envelope waveform extraction process.

[Explanation of symbols]

20, 45 ... Playback system, 21 ... Magnetic tape, 22 ...
Head system, 23 ... Head amplifier, 24 ... Equalizer, 25 ... AD conversion circuit, 26 ... PLL circuit, 2
7, 46 ... Quantization feedback equalizer, 28, 40 ... Comparator, 29 ... Demodulator, 30 ... Digital signal processing circuit, 31 ... Envelope extraction circuit, 32 ... Addition circuit, 33, 35 , 38 …… Low-pass filter, 34 ……
Feedback voltage generation circuit, 37 ... Rectifier circuit, 39 ... Coefficient multiplier, 41 ... Latch circuit, 46A, 47 ... Viterbi decoding circuit, 46B ... Delay circuit.

Claims (6)

[Claims] 1. A multi-valued signal reproduced from a recording medium, wherein a waveform equalization means for equalizing and outputting the waveform is inputted, and the multi-valued signal equalized by the waveform is inputted from the waveform equalization means. The maximum likelihood decoding means for estimating the original reproduction code based on the following, and the reproduction code and the waveform-equalized multi-valued signal are input, and the DC component lost in the waveform equalized multi-valued signal is input. DC regenerating means for generating, and adding the DC component to the waveform equalized multi-valued signal,
An adding means for correcting the low-frequency cutoff characteristic of the multi-valued signal, and a comparing means for inputting the multi-valued signal having the low-frequency cutoff characteristic corrected by the adding means to obtain binary information from the multi-valued signal. A digital data reproducing device characterized by comprising: 2. The direct current reproducing means includes an envelope extracting circuit for extracting an envelope waveform from the waveform-equalized multi-valued signal, and the waveform equalized multi-valued signal at each time point based on the envelope waveform. A feedback signal generation circuit that generates a plurality of possible feedback signal voltages, a selection circuit that outputs a feedback signal voltage selected based on the reproduction code among the plurality of feedback signal voltages, and a selection circuit that is input from the selection circuit. The digital data reproducing apparatus according to claim 1, further comprising a low-pass filter that generates the DC component from a feedback signal voltage. 3. The digital data reproducing apparatus according to claim 2, wherein the pass characteristic of the low-pass filter is set to an inverse characteristic of the low frequency cutoff characteristic of the rotary transformer. 4. A waveform equalizer for equalizing and outputting a multilevel signal reproduced from a recording medium, an envelope extracting circuit for extracting an envelope waveform from the waveform equalized multilevel signal, and the envelope waveform. A feedback signal generation circuit that generates a plurality of feedback signal voltages that the waveform equalized multi-valued signal can take at each time point, and a selection that outputs a feedback signal voltage selected from the plurality of feedback signal voltages. A circuit, a low-pass filter that generates a DC component from the feedback signal voltage input from the selection circuit, and the DC component added to the waveform-equalized multilevel signal,
An adding means for correcting the low-frequency cutoff characteristic of the multi-valued signal, and a comparing means for inputting the multi-valued signal having the low-frequency cutoff characteristic corrected by the adding means to obtain binary information from the multi-valued signal. A digital data reproducing device characterized by comprising: 5. The digital data reproducing apparatus according to claim 1, claim 2, claim 3, or claim 4, wherein the comparing means obtains the binary information by using a maximum likelihood decoding method. 6. The envelope extraction circuit passes a rectification circuit section for rectifying the waveform-equalized multi-valued signal and a rectification output output from the rectification circuit section, and a DC component included in the rectification output. And a discrimination circuit section for comparing the DC component contained in the rectified output and the rectified output to discriminate between the non-zero signal portion and the zero signal portion of the rectified output, and the discrimination circuit section. Based on the result, the voltage level of the rectified output in the non-zero signal portion is output as the envelope waveform, and the zero signal portion outputs the voltage level of the non-zero signal portion located immediately before the zero signal portion. 6. A digital data reproducing apparatus according to claim 1, claim 2, claim 3, claim 4, or claim 5, comprising a latch circuit unit.