JPH07297193A - Integrated circuit flattening method - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the influence of fluctuations in polishing rate, fluctuations in film thickness of embedded films and low polishing rate films on flatness. A polishing stopper film 2 is formed on a surface of a substrate 1 having a concave portion and a convex portion, and a polishing rate is higher than that of the polishing stopper film 2 on the polishing stopper film 2, or compared with the polishing stopper film 2. The embedding film 3 having a different friction coefficient of polishing is formed so that the surface position of the embedding film 3 of the concave portion is lower than the surface position of the polishing stopper film 2 of the convex portion, and the polishing rate is higher than that of the embedding film 3 on the embedding film 3. The low low polishing rate film 4 is deposited so that the surface position of the polishing stop 2 film of the convex portion and the surface position of the low polishing rate film 4 of the concave portion are substantially equal to each other, and the low polishing rate film 4 of the convex portion is deposited. Then, the embedded film 3 is removed by polishing until the polishing stopper film 2 on the convex portion is exposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of flattening an integrated circuit included in a groove-buried type element isolation step, a multilayer wiring step, etc. in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, such as a groove-buried element isolation step or a multi-layer wiring step of arranging wiring having steep steps at a high density, a method for reducing a difference in surface height generated during the step, namely an integrated circuit. The planarization method plays an important role. In particular, an integrated circuit flattening method using polishing has recently attracted attention because it can be flattened over a wide range (globally) and the process is simple.

FIG. 7 is an explanatory view of a conventional integrated circuit flattening method utilizing polishing. First, as shown in FIG.
A buried film 3 thicker than the step of the unevenness is deposited on the uneven substrate 1 to be flattened. Next, as shown in FIG. 7B, polishing is performed by a known method to form a structure in which the embedded film 3 is embedded in the concave portion of the substrate 1.

However, according to this integrated circuit flattening method, as shown in FIG. 7B, although the unevenness of the substrate 1 can be reduced, it cannot be completely flattened and the unevenness of the substrate 1 is reflected. The formed unevenness also remains on the surface after polishing. example,
Even if a device such as a hard polishing cloth made of closed-cell polyurethane is used, it cannot be flattened over a wide range of 1000 μm or more.

In order to solve this problem, an improved integrated circuit flattening method as shown in FIG. 8 (see, for example, S. Kishii et al., 1993 Proceedings of International Conference on Solid-State Device Materials, pages 189-191). ) Is proposed. In this integrated circuit flattening method, as shown in FIG. 8A, first, a buried film 3 thicker than the step of the unevenness is deposited on a substrate 1 having unevenness to be flattened, and the buried film 3 is formed on the buried film 3 as a layer. A low polishing rate film 4 having a polishing rate lower than 3 is thinly deposited. Next, as shown in FIG. 8B, the low polishing rate film 4 on the convex portions is selectively polished and removed by utilizing the property that the film on the convex portions is polished faster than the film on the concave portions. Next, FIG.
As shown in (c), when the polishing is continued thereafter, the polishing rate of the embedded film 3 is higher than that of the low polishing rate film 4, and the exposed embedded film 3 projects in a convex shape. It is selectively removed by polishing to flatten the surface. At that time, since the flat surface of the embedded film 3 embedded in the recess of the substrate 1 is protected by the low polishing rate film 4, the flat state is maintained.

In this integrated circuit flattening method, if the time when polishing is stopped is properly selected, it is possible to flatten even within a width of 5000 μm.

[0007]

However, in such an integrated circuit flattening method, when polishing progresses beyond the state shown in FIG. 8C, the flat surface on the concave portion of the substrate 1 is polished to a low level. Although it is protected by the velocity film 4 and kept substantially flat,
Since the embedded film 3 on the convex portion of the substrate 1 is polished faster than the low polishing rate film 4, as shown in FIG. 8D, the central portion has a depressed shape, resulting in the loss of the overall flatness. Prone. Therefore, variations in the polishing rate and variations in the thickness of the embedded film 3 and the low polishing rate film 4 affect the finally obtained flatness. In addition, the embedded film 3 is formed from the beginning of polishing.
Since the polishing is performed under polishing conditions in which the polishing rate is higher than the polishing rate of the low polishing rate film 4, the embedded film 3 of the convex portion is rapidly polished after reaching the state of FIG. 8B. For this reason, the time to reach the state shown in FIG. 8B varies within the wafer surface due to variations in the wafer surface distribution of the polishing rate and the wafer surface distribution of the thickness of the low polishing rate film 4. Since the thickness of the buried film 3 remaining in the portion fluctuates greatly,
The flatness finally obtained is affected.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to maintain flatness even if there is a fluctuation in the polishing rate or the film thickness of the embedded film or the low polishing rate film. A circuit flattening method, and an integrated circuit flattening method capable of maintaining flatness even if there are variations in the wafer in-plane distribution of the polishing rate or the low polishing rate film thickness. To aim.

[0009]

To achieve this object, in the present invention, a step of forming a polishing stopper film on a surface of a substrate having a concave portion and a convex portion, and a step of stopping the polishing on the polishing stopper film. A buried film having a polishing rate faster than that of the film, or a polishing coefficient different from that of the polishing stopper film is used, and the surface position of the buried film in the concave portion is greater than the surface position of the polishing stopper film in the convex portion. And a low polishing rate film having a polishing rate lower than that of the embedded film on the embedded film, a surface position of the polishing stopper film of the convex portion and the low polishing rate film of the concave portion. A step of depositing a film having a height substantially equal to that of the surface position, and a step of polishing and removing the low polishing rate film and the embedding film of the convex portion until the polishing stopper film of the convex portion is exposed. And.

Further, a step of forming a polishing stopper film on the surface of the substrate having concave portions and convex portions, and a first step on the polishing stopper film
Under the polishing conditions, the polishing speed is higher than that of the polishing stopper film, or the embedded film having a different friction coefficient of polishing as compared with the polishing stopper film is used. Forming a film thickness lower than the surface position of the polishing stopper film, and forming the first film on the embedded film.
Under the polishing conditions of, the polishing rate is lower than that of the embedded film,
A low polishing rate film having a relative polishing rate with respect to the embedded film under the second polishing condition is higher than that under the first polishing condition,
A step of depositing so that the surface position of the polishing stopper film of the convex portion and the surface position of the low polishing rate film of the concave portion are substantially equal to each other; Polishing the low-polishing rate film of the convex portion until the embedded film of the convex portion is exposed; and, under the first polishing condition, the embedded film of the convex portion is polished by the polishing of the convex portion. A step of polishing and removing until the stop film is exposed.

Further, a step of depositing a polishing stopper film on the entire surface of the substrate, a recess is formed by selectively etching the polishing stopper film and the substrate, and a protrusion having the polishing stopper film on the upper surface is formed. And a step of leaving the embedded film on the substrate, which has a polishing rate higher than that of the polishing stopper film or has a different friction coefficient of polishing as compared with the polishing stopper film. Is formed with a film thickness lower than the surface position of the polishing stopper film of the convex portion, and a low polishing rate film having a polishing rate lower than that of the embedded film is formed on the embedded film to stop the polishing of the convex portion. A step of depositing a film having a film thickness such that a surface position of the film and a surface position of the low polishing rate film of the concave portion are substantially equal to each other; Of the polishing stop film Performing a step of polishing removed to expose.

Further, a step of depositing a polishing stopper film on the entire surface of the substrate, a recess is formed by selectively etching the polishing stopper film and the substrate, and a protrusion having the polishing stopper film on the upper surface is formed. And a step of leaving the embedded film on the substrate under the first polishing conditions, the polishing film having a higher polishing rate than the polishing stopper film, or a polishing coefficient different from that of the polishing stopper film. Forming a film thickness such that the surface position of the embedded film in the concave portion is lower than the surface position of the polishing stopper film in the convex portion, and polishing the embedded film on the embedded film under the first polishing condition. A low polishing rate film having a low polishing rate and a relative polishing rate with respect to the embedded film under the second polishing condition is higher than that under the first polishing condition, is formed on the surface position of the polishing stopper film of the convex portion and the concave portion of the concave portion. Low polishing rate Under a second polishing condition, the low polishing rate film of the convex portion is exposed until the embedded film of the convex portion is exposed. A step of polishing and removing and a step of polishing and removing the embedded film of the convex portion until the polishing stopper film of the convex portion is exposed under the first polishing condition.

[0013]

In this integrated circuit flattening method, in the final stage of flattening by polishing, the surface of the polishing stopper film on the convex portion of the substrate is exposed, and the surface of the low polishing rate film on the buried film in the concave portion is substantially flush with the surface. Line up For this reason, when the polishing stopper film has a property that the polishing rate is lower than the polishing rate of the embedded film, the polishing stops on the above-mentioned plane, and therefore the polishing does not proceed even if the polishing time is prolonged. In addition, if the friction coefficient of the polishing stopper film is different from that of the embedded film, when the polishing stopper film is exposed and flattening is completed, a motor for rotating the wafer to be polished or a surface plate with a polishing cloth is used. Since the driving torque of the rotating motor changes, the change can be detected and the polishing can be stopped without excessive polishing.

Under the second polishing condition, the low polishing rate film on the convex portion is removed by polishing until the embedded film on the convex portion is exposed, and the embedded film on the convex portion is removed under the first polishing condition. When polishing removal is performed until the polishing stopper film on the convex portion is exposed, the low polishing rate film on the convex portion can be removed under polishing conditions in which the polishing rate ratio between the embedded film and the low polishing rate film is not large. Even if there are variations in the wafer in-plane distribution or the low polishing rate film in-plane distribution of the film thickness, the time until the embedded film of the convex portion is exposed does not vary within the wafer surface. The thickness of the buried film remaining in the portion does not change significantly.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of an integrated circuit flattening method according to the present invention. First, as shown in FIG. 1A, a polishing stopper film 2, a filling film 3, and a low polishing rate film 4 are sequentially deposited on the entire surface of a substrate 1 having irregularities to be flattened. In this case, the burying film 3 is formed with a film thickness such that the surface position of the recessed burying film 3 is lower than the surface position of the convex polishing stopper film 2, and the low polishing rate film 4 is formed on the convex polishing stopper film 2. The film is deposited in such a thickness that the position and the surface position of the low polishing rate film 4 of the recess become substantially equal. Further, as the polishing stopper film 2, a film having a lower polishing rate than that of the embedded film 3 is used so that the polishing is stopped when the embedded film 3 is removed and the polishing stopper film 2 is exposed in the subsequent polishing step. Alternatively, a film having a polishing coefficient different from that of the embedded film 3 is selected so that the polishing stopper film 2 can be easily exposed.

Table 1 shows low pressure chemical vapor deposition (LPCVD).
Method), a silicon oxide film (SiO ₂ ), a polycrystalline silicon film (poly Si), a silicon nitride film (SiN), and a boron-phosphorus-added silicon oxide film (BPSG) having two polishing rates and friction coefficients It shows the case of polishing with an abrasive (ammonia-added fumed silica and amine-added colloidal silica).

[0017]

[Table 1]

As is clear from Table 1, when fumed silica is used as the polishing agent and a film having a low polishing rate is selected as the polishing stopper film 2, the combination of the polishing stopper film 2 and the burying film 3 is ( SiN, SiO ₂ ), (SiN, poly Si), (SiN, BPSG), (SiO ₂ , poly S)
i), (SiO ₂ , BPSG), (poly Si, BPS
G) etc. are considered. When colloidal silica is used as the polishing agent and a film having a low polishing rate is selected as the polishing stopper film 2, a combination of the polishing stopper film 2 and the embedded film 3 is (SiN, poly-Si), (SiO ₂ , Poly-Si) etc. are considered. When a film having a different friction coefficient is selected as the polishing stopper film 2, (SiO ₂ , poly Si), (SiN, poly Si) is used as the combination of the polishing stopper film 2 and the embedded film 3 regardless of the type of the polishing agent. ), (Poly Si, SiO
₂ ), (poly-Si, SiN), etc. are considered.

Further, the low polishing rate film 4 is formed when the embedded film 3 on the convex portion of the substrate 1 is polished in the subsequent polishing process.
Since the surface of the embedded film 3 embedded in the recess of the substrate 1 is covered and protected from being polished, the polishing rate needs to be low. According to Table 1, when fumed silica is used as the polishing agent, the combination of the embedded film 3 and the low polishing rate film 4 is (BPSG, SiN), (BP).
SG, SiO ₂ ), (BPSG, poly Si), (poly S
i, SiN), (poly Si, SiO ₂ ), (SiO ₂ , S
iN) etc. are considered. When colloidal silica is used as the polishing agent, the filling film 3 and the low polishing rate film 4 are used.
As a combination with (poly Si, SiN), (poly S
i, SiO ₂ ) and the like are conceivable.

The film and the abrasive used in the practice of the present invention are not limited to the above-mentioned ones, as long as the polishing rate and the friction coefficient of polishing satisfy predetermined conditions.
Any film or polishing agent may be used. Further, a multilayer film may be used as the polishing stopper film 2 and the like unless the properties for polishing are basically changed. For example, a multilayer film in which thin SiO ₂ is put under the poly-Si or SiN can be used.

Next, as shown in FIG. 1B, the low polishing rate film 4 on the convex portion is selectively polished and removed by utilizing the property that the film on the convex portion is polished faster than the film on the concave portion. . At this time, if the polishing rate ratio between the embedded film 3 and the low polishing rate film 4 is large,
After reaching the state shown in FIG. 1B, the embedded film 3 on the convex portion is rapidly polished, and the thickness of the embedded film 3 remaining on the convex portion of the substrate 1 greatly changes. It is desirable to perform polishing under polishing conditions in which the polishing rate ratio with the low polishing rate film 4 is small. For example, when poly-Si and SiO ₂ are used for the embedded film 3 and the low polishing rate film 4, respectively, it is better to use ammonia-added fumed silica than the amine-added colloidal silica as the polishing agent.

Next, as shown in FIG. 1C, polishing is performed under the conditions assumed when the polishing stopper film 2, the embedding film 3, and the low polishing rate film 4 are selected. In this case, since the exposed buried film 3 has a higher polishing rate than the low polishing rate film 4 and protrudes in a convex shape, it is selectively removed by polishing and the surface gradually becomes flat. When the polishing is further advanced, the surface of the polishing stopper film 2 on the convex portion of the substrate 1 is exposed, and the surface is aligned with the surface of the low polishing rate film 4 on the concave portion of the substrate 1 on substantially the same plane. At this time, for example, when poly-Si and SiO ₂ are used for the embedded film 3 and the low polishing rate film 4, respectively, when the amine-added colloidal silica is used as the polishing agent, the embedded film 3 and the low polishing rate film 4 are used. It is possible to increase the polishing rate ratio with.

In this integrated circuit planarization method, at the final stage of planarization by polishing, the surface of the polishing stopper film 2 on the convex portion of the substrate 1 is exposed, and the low polishing rate film 4 on the buried film 3 in the concave portion 4 is exposed. Line up on the same plane as the surface of the. For this reason,
When the polishing stopper film 2 has a property that the polishing rate is lower than the polishing rate of the buried film 3, the polishing stops on the above-mentioned plane, so that the polishing does not proceed even if the polishing time is prolonged. Also,
When the friction coefficient of the polishing stopper film 2 is different from that of the embedding film 3, when the polishing stopper film 2 is exposed and flattening is completed, a motor for rotating the wafer to be polished and a surface plate with a polishing cloth are provided. Since the drive torque of the motor for rotating the motor changes, the change can be detected and the polishing can be stopped without performing excessive polishing. Therefore, in either case, the flatness can be maintained even if the polishing rate varies or the film thicknesses of the embedded film 3 and the low polishing rate film 4 vary. Further, for example, when poly-Si and SiO ₂ are used for the embedded film 3 and the low polishing rate film 4, the low polishing rate film 4 on the convex portion is polished and removed until the polishing stopper film 2 on the convex portion is exposed. Sometimes ammonia added fumed as abrasive
When silica is used to polish and remove the convex embedded film 3 until the convex polishing stopper film 2 is exposed, when amine-added colloidal silica is used as the abrasive, the embedded film 3 and the low polishing rate film 4 are separated. Since the convex low polishing rate film 4 can be removed under polishing conditions where the polishing rate ratio is not large, there are variations in the polishing rate within the wafer surface distribution and the low polishing rate film 4 in the wafer surface distribution. Even if this is done, the time until the embedded film 3 on the convex portion is exposed does not fluctuate within the wafer surface, and therefore the thickness of the embedded film 3 remaining on the convex portion does not fluctuate significantly, so that the flatness is improved. Can be kept.

FIG. 2 is an explanatory view of another integrated circuit flattening method according to the present invention. First, as shown in FIG. 2A, a polishing stopper film 2 is deposited on the entire surface of a flat substrate 1, and a resist pattern 5 defining a convex portion is formed by a known lithography technique. Next, as shown in FIG. 2B, the polishing stopper film 2 and the substrate 1 are etched using the resist pattern 5 as a mask, and then the resist pattern 5 is removed. At this time, the resist pattern 5 may be removed immediately after etching the polishing stopper film 2, and the substrate 1 may be etched using the polishing stopper film 2 as a mask. Next, as shown in FIG. 2C, the filling film 3 and the low polishing rate film 4 are sequentially deposited. In this case, the types and thicknesses of the polishing stopper film 2, the embedding film 3, and the low polishing rate film 4 are the same as those in the integrated circuit flattening method described in FIG. Next, as shown in FIG. 2 (d), the low polishing rate film 4 on the convex portions is removed by the same method as the integrated circuit planarizing method described in FIG. 1, and then as shown in FIG. 2 (e). Then, the entire surface is flattened.

In this integrated circuit flattening method, since the polishing stopper film 2 can be formed only on the upper surface of the convex portion of the substrate 1, the polishing stopper film 2 is planarized after the flattening in an element isolation step as will be described later. Is useful when only the convex portions of the substrate 1 are exposed by removing. When the polishing stopper film 2 can also be used as a mask when etching the substrate 1, for example, when the substrate 1 made of silicon is etched using SiO ₂ or SiN as a mask, the polishing stopper film 2 is separately deposited later. You can save the trouble of doing.

FIG. 3 is an explanatory diagram of the groove-buried type element isolation step including the integrated circuit planarizing method described in FIG. In this step, after passing through the steps of FIGS. 2A to 2E, the polishing stopper film 2 is selectively removed to expose the surface of the convex portion which becomes the element forming region of the substrate 1 made of silicon. For example, using a poly-Si on the thin SiO ₂ film as a polishing stopper film 2, the SiO ₂ used as an embedded layer 3, in the case of using SiN as a low polishing rate film 4 was a chlorine gas as a main etching gas reaction Ion etching (RI
E) or the like is used to selectively remove poly-Si, and a slight amount of hydrofluoric acid wet etching is performed to remove thin SiO ₂ to expose the surface of the substrate 1.

FIG. 4 is an explanatory view of another groove-buried type element isolation step including the integrated circuit flattening method described in FIG. In this step, as the polishing stopper film 2, thin Si is used.
When SiN on the O ₂ film is used, SiO ₂ is used as the embedding film 3, and SiN is used as the low polishing rate film 4, FIG.
After passing through the steps (a) to (e), wet phosphoric acid wet etching at 160 ° C. is performed to selectively remove SiN between the polishing stopper film 2 and the low polishing rate film 4 to remove a slight amount of hydrogen fluoride. We do acid wet etching to remove thin SiO ₂ .
The surface of the substrate 1 made of silicon is exposed.

FIG. 5 is an explanatory view of another groove-buried type element isolation step including the integrated circuit flattening method described in FIG. In this step, as the polishing stopper film 2, thin Si is used.
When SiN on the O ₂ film is used, SiO ₂ is used as the embedding film 3, and SiN is used as the low polishing rate film 4, FIG.
After passing through the steps (a) to (e), as shown in FIG. 5A, the embedded film 3 is etched to the height of the convex portion of the substrate 1 using hydrofluoric acid. Next, as shown in FIG.
Hot phosphoric acid wet etching at 160 ° C. is performed to selectively remove SiN between the polishing stopper film 2 and the low polishing rate film 4, and a slight hydrofluoric acid wet etching is performed to remove thin SiO _2. The surface of the substrate 1 made of silicon is exposed.

In this element isolation step, the embedded film 3 does not project on both sides of the convex portion (element formation region) of the substrate 1.

FIG. 6 is an explanatory view of a multi-layer wiring process including another integrated circuit flattening method according to the present invention. First, FIG.
As shown in (a), a first interlayer insulating film 6 is formed on a substrate 1 made of silicon, and a first metal wiring layer 7 is formed by a known method. The state of FIG. 6A is the same as the state of FIG. 1A in terms of surface shape. Next, as shown in FIG. 6 (b), a polishing stopper film 2, a burying film 3, and a low polishing rate film 4 are sequentially deposited by the same method as described in FIG. 1, and as shown in FIG. 6 (c). Then, polishing is performed to obtain a flat surface. Next, as shown in FIG. 6D, a second interlayer insulating film 8 is further deposited. Next, as shown in FIG. 6 (e), the through hole 9 is opened and the second metal wiring layer 10 is formed by a known method.
To form. After that, the above steps are repeated to form the required number of layers of multilayer wiring.

In this multi-layer wiring process, since the interlayer insulating film 8 is deposited, the parasitic capacitance between the wiring layers can be reduced.

[0032]

As described above, in the integrated circuit flattening method according to the present invention, when the polishing stopper film has a property that the polishing rate is lower than the polishing rate of the buried film,
Even if the polishing time is prolonged, the polishing does not proceed, and if the friction coefficient of the polishing stopper film is different, the polishing can be stopped without performing excessive polishing. The flatness can be maintained even if the thickness of the film changes. Therefore, it is effective for improving the yield and reliability in the groove-embedded element isolation step and the multilayer wiring step.

Further, under the second polishing condition, the low polishing rate film on the convex portion is removed by polishing until the embedded film on the convex portion is exposed, and under the first polishing condition, the embedded film on the convex portion is removed. When polishing removal is performed until the polishing stopper film on the convex portion is exposed, even if there are variations in the in-plane distribution of the polishing rate on the wafer or in the in-plane distribution of the low polishing rate film thickness, the embedded film remaining on the convex portion remains Since the thickness does not change greatly, the flatness can be maintained.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an integrated circuit flattening method according to the present invention.

FIG. 2 is an explanatory diagram of another integrated circuit flattening method according to the present invention.

FIG. 3 is an explanatory diagram of an element isolation process including the integrated circuit planarization method described in FIG.

FIG. 4 is an explanatory diagram of another element isolation process including the integrated circuit flattening method described in FIG.

FIG. 5 is an explanatory diagram of another element isolation process including the integrated circuit planarization method described in FIG.

FIG. 6 is an explanatory view of a multilayer wiring process including another integrated circuit planarizing method according to the present invention.

FIG. 7 is an explanatory diagram of a conventional integrated circuit flattening method.

FIG. 8 is an explanatory diagram of another conventional integrated circuit flattening method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Polishing stop film 3 ... Buried film 4 ... Low polishing rate film 5 ... Resist pattern 6 ... First interlayer insulating film 7 ... First metal wiring layer 8 ... Second interlayer insulating film 9 ... Through hole 10 ... Second metal wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/76

Claims (4)

[Claims] 1. A step of forming a polishing stopper film on a surface of a substrate having a concave portion and a convex portion, and a polishing rate on the polishing stopper film is higher than that of the polishing stopper film, or compared with the polishing stopper film. Then, a step of forming a buried film having a different friction coefficient of polishing with a film thickness such that the surface position of the buried film of the concave portion is lower than the surface position of the polishing stopper film of the convex portion, and on the buried film, A low polishing rate film having a polishing rate lower than that of the embedding film is deposited with a film thickness such that the surface position of the polishing stopper film of the convex portion and the surface position of the low polishing rate film of the concave portion are substantially equal in height. A step, and the low polishing rate film and the embedding film of the protrusion,
And a step of polishing and removing the polishing stopper film of the convex portion until it is exposed. 2. A step of forming a polishing stopper film on a surface of a substrate having a concave portion and a convex portion, and a polishing rate higher than that of the polishing stopper film under the first polishing condition on the polishing stopper film, Alternatively, a step of forming a buried film having a different friction coefficient of polishing as compared with the polishing stopper film in a film thickness such that the surface position of the buried film in the recess is lower than the surface position of the polishing stopper film in the protrusion. And a polishing rate on the embedded film lower than that of the embedded film under the first polishing condition, and a relative polishing rate with respect to the embedded film higher than that of the first polishing condition under the second polishing condition. Depositing a polishing rate film with a film thickness such that the surface position of the polishing stopper film of the convex portion and the surface position of the low polishing rate film of the concave portion are substantially equal to each other; and the second polishing condition. Under the low polishing rate film of the convex portion, A step of polishing and removing until the embedded film of the convex portion is exposed, and a step of polishing and removing the embedded film of the convex portion until the polishing stopper film of the convex portion is exposed under the first polishing conditions. A method of planarizing an integrated circuit, comprising: 3. A step of depositing a polishing stopper film on the entire surface of a substrate, wherein a recess is formed by selectively etching the polishing stopper film and the substrate, and a protrusion having the polishing stopper film on the upper surface is formed. A step of remaining, and a polishing rate on the substrate is faster than the polishing stopper film,
Alternatively, a step of forming a buried film having a different friction coefficient of polishing as compared with the polishing stopper film in a film thickness such that the surface position of the buried film in the recess is lower than the surface position of the polishing stopper film in the protrusion. A low polishing rate film having a polishing rate lower than that of the embedded film is formed on the filling film, and a surface position of the polishing stopper film of the convex portion and a surface position of the low polishing rate film of the concave portion are substantially equal to each other. And a step of depositing the low polishing rate film and the embedding film of the convex portion,
And a step of polishing and removing the polishing stopper film of the convex portion until it is exposed. 4. A step of depositing a polishing stopper film on the entire surface of a substrate, wherein a recess is formed by selectively etching the polishing stopper film and the substrate, and a convex portion having the polishing stopper film on the upper surface is formed. And a step of leaving the embedded film on the substrate under the first polishing condition, the polishing film having a polishing rate faster than that of the polishing stopper film or a polishing coefficient different from that of the polishing stopper film. Forming a film thickness such that a surface position of the embedded film in the concave portion is lower than a surface position of the polishing stopper film in the convex portion, and polishing the embedded film on the embedded film under the first polishing condition. A low polishing rate film having a low polishing rate and a relative polishing rate with respect to the embedded film under the second polishing condition is higher than that under the first polishing condition, is formed on the surface position of the polishing stopper film of the convex portion and the concave portion of the concave portion. Low polishing rate film A step of depositing a film having a height such that the surface positions are substantially equal to each other, and polishing the low polishing rate film of the convex portion under the second polishing condition until the embedded film of the convex portion is exposed. And a step of polishing and removing the embedded film of the convex portion until the polishing stopper film of the convex portion is exposed under the first polishing condition. Method.