JPH07297802A - Line switching device - Google Patents

Abstract

PURPOSE:To prevent the change of the multiplexing position of a frame synchronizing pattern multiplexed with an output signal even at the time of switching from a current line to a standby line. CONSTITUTION:A write address counter 9-m generates a write address AWm in accordance with a select frame pulse F6m. A reference signal delay circuit 10-m outputs a delay reference signal (delay frame pulse) Rm obtained by delaying a reference signal (reference frame pulse) R0 by a certain time. A read address counter 11-m generates a read address ARm in accordance with the delay frame pulse. A select data signal string D6m is written as a stored data signal string in a FIFO memory 12-m in accordance with the write address AWm and the stored data signal string is read out in accordance with the read address ARm to output a changed data signal string D12. Thus, this signal string D12 where the frame synchronizing pattern multiplexing position always has a fixed phase is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line switching device, and more particularly to a line switching device in a receiving side communication device when transmitting a data signal sequence corresponding to a new synchronous digital hierarchy in a communication system of M to 1 line switching system. Regarding

[0002]

2. Description of the Related Art Conventionally, in this type of communication system, one spare line is provided for M working lines, and the transmitter side is used for maintenance or when a failure occurs in the working line. The M to 1 line switching method is used in which the same data signal sequence as the working line is sent to the protection line, and the receiving side switches the received data signal sequence to the protection line to rescue the working line.

On the other hand, in recent years, a new Synchronous Digital Hierarchy (SDH) has been standardized, and a communication system for transmitting a data signal string having an STM-N frame structure as shown in FIG. 6 has been constructed. The data signal sequence of the STM-N frame structure is a section overhead (Section Overhead: hereinafter, which is composed of actual information called a payload and information for frame synchronization, error monitoring, alarm transfer, etc.
SOH) and a pointer indicating the start position of the actual information. In such a communication system, on the receiving side of the communication system transmitting this STM-N data signal sequence, an external digital clock supply (Digi
tal Clock Supply: hereinafter referred to as DCS), a reference clock and a reference frame pulse that are synchronized with an input clock signal are generated, the clock is changed using the reference clock and the reference frame pulse, and the clock is changed. Calculate the change in the start position of the actual information that occurred in
A method of changing the pointer is used (for example,
See JP-A-4-267648. Therefore, in transmitting the data signal sequence having the STM-N structure by the M: 1 switching method, it is necessary to provide a line switching device suitable for transmitting the data signal sequence corresponding to the new synchronous digital hierarchy SDH. .

Next, a conventional line switching device will be described with reference to FIGS. FIG. 4 shows a conventional line switching device, and FIG. 5 is a timing chart for explaining the operation of the line switching device shown in FIG.
FIG. 6 is a diagram showing an STM-N frame structure. In order to simplify the explanation, it is assumed that the conventional line switching device of FIG. 4 transmits the data signal sequence of the STM-1 frame structure shown in FIG.

As shown in FIG. 7, the STM-1 frame is composed of 9 rows and 270 columns (bytes). SOH is one row ~
It is accommodated in the first to third rows and the fifth to ninth rows of the ninth column. The pointer is stored in the fourth row of the first to ninth columns. Rest (1
Actual information is stored in columns 0 to 270, lines 1 to 9).
In the SOH, in the first 9 bytes, the 3-byte frame synchronization patterns A1 and A2 and the 1-byte S
The TM identification pattern C1 is assigned.

In FIG. 4, the line switching device includes first to Mth active systems 1-1, 1-2, ..., 1-M (M is an integer of 2 or more) and a standby system 1- (M + 1). And a reference signal generation circuit 2. The first to M-th active systems 1-1 to 1-M respectively include the first to M-th reception processing units 3-1, 3-2, ..., 3-M and the first to M-th pointers. The replacement circuits 4-1, 4-2, ..., 4-M, and the first
To M-th active spare selection circuits 6-1, 6-2, ..., 6-
M and the first to Mth SOH multiplexing circuits 7-1, 7-2,
..., 7-M. Spare system 1- (M + 1)
Has a (M + 1) th reception processing unit 3- (M + 1), a (M + 1) th pointer replacement circuit 4- (M + 1), and a backup signal distribution circuit 5.

The reference signal generating circuit 2 receives the external DCS clock signal CLK and receives a reference signal R ₀ (see R _{0 in} FIG. 5) composed of a reference clock signal and a reference frame pulse signal synchronized with the external DCS clock signal CLK. Is output.

The first transmitted on the first to Mth working lines
The to Mth transmission data signal sequences are supplied to the first to Mth active systems 1-1 to 1-M, respectively. The m-th transmission data signal sequence transmitted on the m-th working line (1.ltoreq.m.ltoreq.M: integer) is subjected to frame synchronization establishment, SOH termination, etc. in the m-th reception processing unit 3-m. The m-th input data signal sequence D3 _m (see D3 _{m in} FIG. 5) and the m-th input frame pulse F3 _m (see F3 _{m in} FIG. 5) are output. The m-th pointer replacement circuit 4-m receives the m-th input data signal sequence D3 _m and the m-th input frame pulse F3 _m output from the m-th reception processing unit 3- _m, and the reference signal generation circuit 2. receiving a reference signal R ₀ which is output from the reference signal input data signal sequence of the m-th clock R ₀ D3 _m
After replacing the pointers by changing the position, the m-th replacement data signal sequence D4 _m (see D4 _{m in} FIG. 5) and the m-th replacement frame pulse F4 _m (see F4 _{m in} FIG. 5) are output.

Similarly, the backup transmission data signal sequence transmitted on the backup line is the (M +) th of the backup system 1- (M + 1).
Reception processing unit 1-(M + 1) establishment of frame synchronization in the 1), end the like of the SOH are performed, auxiliary input data signal sequence D3 ₀ (see D3 ₀ of FIG. 5) and auxiliary input frame pulse F3 ₀ (Fig. 5 F3 ₀ ) of the above). The (M + 1) th pointer replacement circuit 4- (M + 1) receives the preliminary data signal sequence D3 ₀ and the preliminary frame pulse F3 ₀ from the (M + 1) th reception processing unit 1- (M + 1), and receives the reference signal generation circuit 2 Clock replacement is performed using the reference signal R ₀ output from the spare replacement data signal sequence D
4 ₀ outputs a (see figure D4 ₀ 5) and re with the preliminary frame pulse F4 ₀ (see F4 ₀ in FIG. 5).

The spare signal distribution circuit 5 is a spare system 1-
(M + 1) th (M + 1) th pointer replacement circuit 4- (M
+1) is a circuit for distributing the pre-replacement data signal sequence D4 ₀ and the pre-replacement frame pulse F4 ₀ to the first to M-th active systems 1-1 to 1-M. Distributed data signal sequence D5 ₁ , D5 ₂ , ..., D5
_M (D5 _m see FIG. 5) and the first to the distribution frame pulse _F5 1 of the _{M, F5 2, ..., F5} M active system of first through M, respectively (see F5 _m in FIG. 5) 1-1 ~ 1
-Send to M.

In the m-th active system 1-m, the m-th
The active pre-selection circuit 6-m of the m-th active line outputs the m-th replacement data signal sequence D4 _m and the m-th replacement frame pulse F4 output from the m-th pointer replacement circuit 4-m of the m-th working line.
_m , the m-th distribution data signal sequence D5 _m output from the preliminary signal distribution circuit 5, and the m-th distribution frame pulse F5 _m
And the m-th selection control signal S _m (see S _{m in} FIG. 5)
After selection by, the m-th selected data signal sequence D6 _m (see FIG.
D6 _m ) and the m-th selected frame pulse F6
_m (see F6 _{m in} FIG. 5) is output. The m-th SOH multiplexing circuit 7-m, in accordance with the m-th selected frame pulse F6 _m output from the m-th working preliminary selection circuit 6-m, transmits the frame synchronization pattern or the like to the _m-th selected data signal sequence D6 _m . After SOH is multiplexed, the m-th output data signal sequence D7 _m (see D7 _{m in} FIG. 5) is output to the opposite transmission / multiplexing device (not shown).

[0012]

[SUMMARY OF THE INVENTION In the conventional line switching apparatus described above, as shown in _{F4 0, D4 0, F4 m} , D4 m in FIG. 5, the pointer modifiers circuit 4-1~4- (M + 1)
Sort data signal sequence _D4 0 to D4 _M and Tsukegae frame pulse _F4 0 .about.F4 _M with output are consistent with the active system 1-1 to 1-M and the spare system 1- (m + 1) from. However, the delay time generated in the data signal sequence and the frame pulse from the pointer replacement circuit 4-m of the active system 1-m to the active spare selection circuit 6m and the pointer replacement circuit 4- of the standby system 1- (M + 1). (M +
There is a difference between the delay time that occurs in the data signal sequence and the frame pulse from 1) until it is input to the active spare selection circuit 6m via the spare signal distribution circuit 5. For this reason,
The input of the current pre-selecting circuit 6m, _F4 m, D4 of FIG. 5
_As indicated by _{m 1} , F 5 _m , and D 5 _m , the phase of the frame pulse does not match. Therefore, when switching from a working line on the working preselection circuit 6m to the protection line, D6 _m in FIG. 5,
As indicated by F6 _m , the phase of the frame pulse input to the SOH multiplex circuit 7-m changes abruptly, so that the frame position of the data signal sequence D7 _m output from the SOH multiplex circuit 7-m also changes abruptly. . As a result, it is observed that the opposite transmission / multiplexer side momentarily loses synchronization and then recovers, resulting in the generation of an unnecessary frame out-of-sync warning.

Further, in order to prevent the above-mentioned unnecessary loss of frame synchronism, as in Japanese Patent Laid-Open No. 4-304725, the frame pulse of the working line and the protection line at the time of input of the working protection selection circuit are matched. There is also known a method in which a delay element is inserted in the data signal train of the active system so as to perform delay adjustment for each system and then switch. However, in such a method, since the delay times of the working line and the protection line are different for each system, there is a problem that the delay adjustment must be individually performed for each system.

Therefore, an object of the present invention is to prevent the multiplexing position of the frame synchronization pattern multiplexed on the output signal from changing even when the working line is switched to the protection line on the receiving side of the wireless terminal device to switch the system. An object of the present invention is to provide a line switching device capable of doing so.

[0015]

The line switching device of the present invention has one spare line for M (M: natural number) working lines, and fails during maintenance or one of the working lines. In the transmission system for transmitting the data signal sequence by switching the working line to the protection line in the case of occurrence of the error, the line switching device is provided in the communication device on the receiving side, and the data signal sequence is unified by the synchronous digital hierarchy. STM-N
A management information section overhead (SOH) having an (N: natural number) frame structure and including actual information, a pointer indicating the start position of this actual information, and a frame synchronization pattern.
And a reference signal generating circuit for generating a reference signal composed of a reference clock and a reference frame pulse synchronized with an input clock signal supplied from the outside, an M active system, and a spare unit. System, each of the M active and standby systems
After the input data signal sequence and the input frame pulse are transferred to the reference signal and the pointer representing the start position of the actual information is calculated,
The backup system is provided with a pointer replacement circuit that multiplexes the data signal sequence and outputs a replacement data signal sequence and a replacement frame pulse. The backup system distributes the replacement data signal sequence and the replacement frame pulse to M active systems. A spare signal distribution circuit that distributes as a signal sequence and a distribution frame pulse is provided, and each of the M active systems selects a distribution data signal sequence and a distribution frame pulse, and a replacement data signal sequence and a replacement frame pulse, as a selection control signal. In response to the switching, the selection circuit that outputs the selected data signal train and the selected frame pulse and the selected data signal train are delayed by the reference frame pulse by a fixed time longer than the maximum delay time that occurs in the data signal train in the backup system. The delayed frame signal is output and the transfer data signal sequence is output and the delayed frame pulse is output. And Nokawa means for, in accordance with delayed frame pulse, and having a SOH multiplexing circuit the SOH multiplexes outputs including a frame synchronization pattern in Nokawa data signal sequence.

The transfer means includes a write address counter for generating a write address according to the selected frame pulse, and a reference signal delay circuit for delaying the reference clock and the reference frame pulse for a predetermined time and outputting the delayed clock and the delayed frame pulse. , A read address counter that generates a read address according to a delayed frame pulse, and a memory that writes a selected data signal sequence as a stored data signal sequence according to a write address and reads a stored data signal sequence according to a read address and outputs a transfer data signal sequence Preferably consisting of

[0017]

In the line switching apparatus of the present invention, the selected frame data pulse output from the selection circuit is a delayed frame pulse obtained by delaying the reference frame pulse for a fixed time longer than the maximum delay time occurring in the data signal train in the spare system. By providing a transfer means for transferring the transfer data signal sequence to the output circuit, the selection circuit inputs the selection control signal while the phase of the data signal sequence of the active system and the data signal sequence of the standby system are different from each other. Thus, even when the working line is switched to the protection line, the frame synchronization pattern multiplexing position in the data signal sequence can be fixed.

[0018]

The present invention will be described in detail with reference to the drawings.

A line switching device according to an embodiment of the present invention will be described with reference to FIG. In the line switching device of the present embodiment, the first to M-th active systems 1-1 to 1-M have first to M-th transfer units 8-1, 8-2, respectively.
.., 8-M, and has the same configuration as that shown in FIG.

FIG. 1 shows the m-th working system 1 shown in FIG.
-M and the main part of the spare system 1- (M + 1) are shown. Hereinafter, the mth transfer unit 8-m which characterizes the present invention will be described with reference to FIG. 1. Mth transfer unit 8
-M is provided between the mth selection circuit 6-m and the SOH multiplexing circuit 7-m.

[0021] Nokawa unit 8-m m-th, the selection data signal sequence D6 _m of the m, only preliminary system 1- (M + 1) Maximum delay time over a predetermined time caused the data signal sequence in the reference signal ( the output of the reference clock and the reference frame pulse) the m Nokawa data signal sequence for changing carrying R ₀ to delay the reference signal R _m of the m delayed D12 _m,
The m-th delay reference signal (delay clock and delay frame pulse) R _m is output.

The mth transfer unit 8-m includes an mth write address counter 9-m, an mth reference signal delay circuit 10-m, and an mth read address counter 11-m.
And the m-th FIFO (First In First Out) memory 12
-M and.

The mth write address counter 9-m is
A circuit that generates and outputs the _mth write address AW _m based on the mth selected frame pulse F6 _m , and outputs the mth selected data signal sequence D6 _m to the mth FIFO memory described later according to the mth write address AW _m. Write to 12-m.
The m-th reference signal delay circuit 10-m delays the reference signal R ₀ consisting of a reference clock and a reference frame pulse by the above-mentioned fixed time to delay the m-th delay clock consisting of the m-th delay clock and the m-th delay frame pulse. and outputs the reference signal _{R m.} The mth read address counter 11-m generates and outputs the _mth read address AR _m according to the mth delayed reference signal R _m (mth delayed frame pulse). Mth FIF
The O memory 12-m writes the m-th selected data signal sequence D6 _m as the m-th stored data signal sequence according to the m-th write address AW _{m, and} according to the m-th read address AR _m. and outputs the Nokawa data signal sequence D12 _m of the m read a signal sequence.

Next, the operation of this embodiment will be described with reference to FIGS. 1 and 3. In FIG. 3, in the first to fourth rows, the preliminary input data signal sequence D3 ₀ , the preliminary input frame pulse sequence F3 ₀ , and the m-th input data signal sequence D, respectively.
3 _m , the m-th input frame pulse train F3 _m is shown. Fifth
The reference frame pulse of the reference signal R ₀ is shown in the row. Sixth
Through the 9th row, spare replacement frame pulse F4
₀ , preliminary replacement data signal sequence D4 ₀ , mth replacement frame pulse train F4 _m , mth replacement data signal sequence D4 _m
Indicates. In the 10th and 11th rows, the m-th distribution frame pulse train F5 _m and the m-th distribution data signal train D5, respectively.
indicates _m . The 12th row shows the _m-th selection control signal S _m . Respectively 13 and line 14 shows the selected frame pulse train F6 _m of selection data signal sequence D6 _m and a m of the m. The 15th to 17th rows show the mth write address AW _m , the mth delay reference signal R _m , and the mth read address AR _m , respectively. Each line 18 and 19 indicates an output data signal sequence D7 _m of Nokawa data signal sequence D12 _m and a m of the m. Also, A1 ', A2', C1 '
Indicates the SOH multiplex position. SP-DA and TP-DA show actual information. a, b, c, d, e, f, g, ..., s,
t, u, v, w, x, y, z represent addresses.

Consider the operation from the pointer replacement circuit to the selection circuit. As described in the prior art, the delay time from the m-th pointer replacement circuit 4-m to the m-th selection circuit 6-m input of the m-th active system 1-m and the standby system 1- (M + 1). (M + 1) th pointer replacement circuit 4 of
It is different from the delay time from-(M + 1) to the m-th selection circuit 6-m input. As a result, the m-th replacement frame pulse F4 _m of the m-th active system 1-m and the m-th distribution frame pulse F5 _m of the backup system 1- (M + 1) in the m-th selection circuit 6-m are , F4 _m and F5 _m in FIG. 3 do not match. Therefore, when the selection control signal S _m of the m switching the working line of the m in the protection line, the m selection frame pulse F6 _m the phase of the output from the selecting circuit 6-m in the m-th, the 3 It changes as shown by F6 _m .

The mth write address counter 9-m generates the _mth write address AW _m with reference to the mth selected frame pulse F6 _m . Therefore, D in FIG.
As indicated by 6 _m , F6 _m , and AW _m , the relative phase of the frame synchronization pattern multiplex position in the data signal sequence and the mth write address AW _m of the mth FIFO memory 12-m always match.

On the other hand, on the read side of the m-th FIFO memory 12-m, the (M +)-th spare system 1- (M + 1) is used.
1) from the output of the pointer replacement circuit 4- (M + 1)
The m-th reference signal delay circuit 10-m provides a constant delay time longer than the delay time that occurs in the data signal train until the input to the FIFO memory 12-m of the m-th reference signal delay circuit 1-
Delayed frame pulse of the m delay reference signal R _m of the m output from the 0-m on the basis generated by the read address counter 11-m of the m, the m indicating the AR _m in FIG. 3
By reading the m-th stored data signal sequence from the m-th FIFO memory 12-m at the read address AR _m of
The delay time difference generated at the input of the m-th selection circuit 6-m is absorbed, and the frame synchronization pattern multiplex position is always read at a constant timing.

[0028] Therefore, output from the by m selection control signal S _m by the selection circuit 6-m in the m even when switching the working line of the m in the protection line, SOH multiplexer 7-m of the m The multiplexing position of the frame synchronization pattern in the m-th output data signal sequence D7 _m is constant.

The present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and changes can be made without departing from the gist of the present invention.

[0030]

As described above, according to the present invention, the reference data frame pulse output from the selection circuit is delayed by the reference frame pulse by a constant time longer than the maximum delay time that occurs in the data signal stream in the spare system. By providing a transfer means for outputting the transfer data signal sequence by transferring to the delayed frame pulse, the selection circuit can keep the phases of the data signal sequence of the active system and the data signal sequence of the standby system different at the input of the selection circuit. Even when the working line is switched to the protection line by the selection control signal, the frame synchronization pattern multiplex position in the data signal sequence can be made constant.
The timing of multiplexing the frame synchronization pattern by the OH multiplexing circuit does not change. As a result, there is an effect that it is possible to prevent an unnecessary out-of-frame alarm from being issued on the side of the opposite transmission / multiplexing device at the time of system switching. Also,
Since the transfer means in the present invention performs the transfer operation based on the delayed frame pulse obtained by delaying the reference frame pulse for a certain time, it is not necessary to individually adjust the delay for each system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a line switching device of the present invention.

FIG. 2 is a block diagram showing a configuration of a line switching device according to an embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the line switching device shown in FIG. 1 (FIG. 2).

FIG. 4 is a block diagram showing a configuration of a conventional line switching device.

5 is a timing chart for explaining the operation of the line switching device shown in FIG.

FIG. 6 is a diagram showing an STM-N frame structure.

FIG. 7 is a diagram showing an STM-1 frame structure which is a data signal sequence used in the present invention and the prior art.

[Explanation of symbols]

 1-1 to 1-M Working system 1- (M + 1) Backup system 2 Reference signal generation circuit 3-1 to 3- (M + 1) Reception processing unit 4-1 to 4- (M + 1) Pointer replacement circuit 5 Backup signal distribution Circuits 6-1 to 6-M selection circuit (current spare selection circuit) 7-1 to 7-M SOH multiple circuit 8-1 to 8-M Transfer unit 9-1 to 9-M Write address counter 10-1 to 10-M reference signal delay circuit 11-1 to 11-M read address counter 12-1 to 12-M FIFO memory

Claims (2)

[Claims] 1. A backup line for M (M: natural number) working lines is provided, and the working line is used as a backup line during maintenance or when a failure occurs in one of the working lines. A line switching device provided in a receiving side communication device in a transmission system for switching a line to transmit a data signal sequence, wherein the data signal sequence is an STM-N (N: natural number) frame structure unified by a synchronous digital hierarchy. And a pointer indicating the start position of the actual information,
A reference signal generating circuit for generating a reference signal composed of a reference clock and a reference frame pulse synchronized with an input clock signal supplied from the outside in the line switching device, which circuit comprises a management information section overhead (SOH) including a frame synchronization pattern. And M active systems and one standby system, each of the M active systems and the standby system
With a pointer that replaces the input data signal sequence and the input frame pulse with the reference signal, calculates the pointer that represents the start position of the actual information, and then multiplexes the data signal sequence and outputs the replacement data signal sequence and the replacement frame pulse. And a spare signal distribution circuit for distributing the replacement data signal sequence and the replacement frame pulse to the M active systems as a distribution data signal sequence and a distribution frame pulse. Each of the active systems of the above switches the distribution data signal sequence and the distribution frame pulse and the replacement data signal sequence and the replacement frame pulse in response to a selection control signal, and selects the selection data signal sequence and the selection frame pulse. The selection circuit for outputting and the selected data signal sequence are stored in the data signal sequence in the backup system. According to the delay frame pulse, the transfer means outputting the transfer frame data signal train by transferring the transfer frame data signal to the delayed frame signal in which the reference frame pulse is delayed by a constant time equal to or more than the delay time, The SOH including the frame synchronization pattern in the transfer data signal sequence
And a SOH multiplexing circuit that multiplexes and outputs the line switching device. 2. A transfer address means for generating a write address according to the selected frame pulse, and a delay clock and the delayed frame pulse by delaying the reference clock and the reference frame pulse for the fixed time. A reference signal delay circuit for outputting, a read address counter for generating a read address according to the delay frame pulse, a write of the selected data signal sequence as a stored data signal sequence according to the write address, and a storage data signal according to the read address. The line switching device according to claim 1, further comprising a memory that reads out a column and outputs the transfer data signal sequence.