JPH07297805A - Spread spectrum code synchronization circuit and synchronization method - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the circuit scale and reduce the probability of erroneous determination to improve noise performance. [Structure] First, a synchronization candidate selection period corresponding to the m period period of a PN code is set, and a partial correlation using a part of the PN code is performed by the correlation detection circuit 41 during this period, and the partial correlation is detected. Among the correlation values, three correlation values are selected by the synchronization candidate selection circuit 43 as synchronization candidate timings in the order of increasing level from correlation values above the threshold value. Next, a cumulative addition period corresponding to the n cycle period is set, and during this period, the cumulative addition value of each correlation value selected as the synchronization candidate timing is calculated by the cumulative addition circuit 45, and the cumulative addition value of these cumulative addition values is calculated. Among them, the maximum level cumulative added value is selected by the cumulative value comparison circuit 49, and the timing of the selected cumulative added value is used as the synchronization timing, and thereafter the synchronization holding circuit 50 holds the synchronization.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum code synchronization circuit provided for establishing code synchronization between a received signal and a reference spread code in a radio communication apparatus adopting a spread spectrum communication system and the above code synchronization. It relates to a spread spectrum code synchronization method used for establishing.

[0002]

2. Description of the Related Art In recent years, a spread spectrum communication system, which is resistant to interference and interference, has attracted attention as one of communication systems applied to mobile radio communication systems. The spread spectrum communication system is used to realize a code division multiple access (CDMA) system. For example, in a device on the transmission side, PSK is applied to digitized voice data and image data.
Alternatively, after performing modulation (primary modulation) by a digital modulation method such as the FSK modulation method, the primary modulated transmission data is spread spectrum (secondary modulation) using a spread code such as a pseudo noise code (PN code). As a result, it is converted into a wideband baseband signal, and then converted into a radio frequency signal for transmission. On the other hand, in the device on the receiving side, after performing frequency conversion of the received radio frequency signal into the intermediate frequency signal or the baseband signal, despreading processing is performed using the same code as the spreading code used on the device on the transmitting side, Thereafter, digital demodulation is performed by a digital demodulation system such as PSK or FSK demodulation system to reproduce received data.

By the way, in a wireless communication apparatus adopting this type of communication system, it is necessary to establish code synchronization between the received signal and the reference spread code when despreading the received signal. As a method for establishing this code synchronization, for example, an initial synchronization acquisition mode is first set, and in this mode, synchronization is established by correlating the received signal and the reference spread code, and when synchronization is established, synchronization is established. A method of holding the synchronization established state after shifting to the holding mode is used.

As a circuit for detecting the correlation between the received signal and the reference spread code, for example, a matched filter is used. By using the matched filter, it is possible to establish synchronization in a relatively short time even if the spreading code is a high-speed code and has a long cycle. However, the circuit using the matched filter generally has a drawback that the circuit scale becomes large.

Therefore, recently, a method has been proposed in which the correlation calculation is not performed over the entire period of the spreading code, but the correlation calculation is performed by using only a part of one period of the spreading code. With such a method, the number of stages of the delay line of the matched filter is reduced, so that the circuit scale of the synchronous circuit can be reduced. However, such a method using partial correlation of spread codes is susceptible to various noise components contained in the received signal, and as a result, another problem arises in that the probability of misjudgment of synchronization timing increases.

[0006]

As described above, in the conventional art, if the correlation is performed by using all one cycle of the spreading code, the circuit scale of the synchronizing circuit including the matched filter is increased, while the spreading code The circuit scale is reduced by using the partial correlation, but there is a problem in that the probability of erroneous determination becomes high and the circuit becomes weak against noise.

The present invention has been made in view of such circumstances, and the first purpose thereof is to reduce the circuit scale,
Moreover, it is an object of the present invention to provide a synchronization circuit and a synchronization method for spread spectrum codes, in which the probability of misjudgment is reduced to improve the noise performance.

A second object of the present invention is to provide a spread spectrum code synchronizing circuit and a synchronizing method capable of accurately detecting the synchronization timing even when the line quality is remarkably deteriorated. .

A third object of the present invention is to prevent the occurrence of erroneous synchronization in the state where the line quality is deteriorated and to shorten the time required for establishing synchronization in the state where the line quality is good. A spread spectrum code synchronization circuit and a synchronization method are provided.

[0010]

In order to achieve the first object, the first invention is to first establish the synchronization of a reference spread code with a received signal which is spread spectrum by a spread code. And a part of the reference spread code are detected, at least one correlation value satisfying a predetermined first condition is selected from the detected correlation values, and then the selected correlation value is selected. The correlation value between the received signal and a part of the reference spread code detected each time the time corresponding to one cycle of the spread code has elapsed from the value detection timing is cumulatively added for a plurality of cycles. It is determined whether or not the predetermined second condition is satisfied, and when it is determined that the second condition is satisfied, the detection timing of the cumulative addition value is recognized as the synchronization timing.

On the other hand, in order to achieve the above-mentioned second object, in the second invention, first, a correlation value between the received signal and a part of the reference spread code is detected, and among the detected correlation values. At least one correlation value satisfying the predetermined first condition is selected from among the received signals, and the received signal detected each time the time corresponding to one cycle of the spreading code elapses from the detection timing of the selected correlation value. And a correlation value with a part of the reference spread code are cumulatively added for a plurality of cycles, and the cumulative addition value is a predetermined second value.
It is determined whether or not the condition is satisfied, and when it is determined that the condition is satisfied, the detection timing of the cumulative addition value is recognized as the synchronization candidate timing. Then, the correlation value between the received signal and the entire one cycle of the reference spreading code is detected based on the recognized synchronization candidate timing, and whether or not the detected correlation value satisfies the predetermined third condition. When it is determined that the correlation value is satisfied, the detection timing of the correlation value is officially recognized as the main synchronization timing.

Further, in order to achieve the above-mentioned third object, a third aspect of the present invention determines whether or not the cumulative addition value satisfies a predetermined second condition, and has the second condition. When the determination is made, it is determined whether the cumulative addition value further satisfies the fourth condition, and when the fourth condition is satisfied, the timing corresponding to the cumulative addition value is changed to the regular synchronization timing. On the other hand, when the fourth condition is not satisfied, the timing corresponding to the cumulative addition value is recognized as the synchronization candidate timing. Then, when the synchronization candidate timing is recognized, the correlation value between the received signal and the entire one cycle of the reference spreading code is detected based on the recognized synchronization candidate timing, and the detected correlation value is detected. Is determined to satisfy the predetermined third condition, and when it is determined to be satisfied, the timing corresponding to the correlation value is recognized as the normal synchronization timing.

[0013]

As a result, according to the first invention, the correlation between the received signal and the reference spread code is detected by the partial correlation. For this reason, the number of stages of the delay line of the matched filter can be as small as the number of stages of the reference spread code used for the partial correlation, and thus the circuit scale can be reduced.

A correlation value satisfying the first condition (for example, a predetermined level or more) is selected from the correlation values detected by the partial correlation, and the correlation value is detected in each subsequent cycle of the reference spreading code. When a plurality of correlation values detected at the same timing as the timing are cumulatively added and the cumulative addition value satisfies a predetermined second condition (level is a certain level or more), detection of the cumulative addition value The timing is recognized as the synchronization timing. For this reason,
As compared with the case of recognizing the synchronization timing only from the correlation value of the partial correlation, the synchronization timing can be recognized more accurately, which improves the noise resistance performance.

On the other hand, according to the second invention, when it is determined that the cumulative addition value obtained by cumulatively adding the correlation values satisfies the predetermined second condition, the cumulative addition value is detected. The timing is not recognized as the immediate synchronization timing but is recognized as the synchronization candidate timing. Then, the correlation value between the received signal and one cycle of the reference spreading code is detected based on this synchronization candidate timing, and the detected correlation value does not satisfy the predetermined third condition (for example, a predetermined level or more). For example, the detection timing of this correlation value is officially recognized as the main synchronization timing. That is, in addition to the process of detecting the synchronization candidate timing by the partial synchronization, the process of confirming the synchronization timing by the total correlation is performed based on the synchronization candidate timing. Therefore, it becomes possible to capture the synchronization timing more accurately as compared with the case where only the detection process by partial synchronization is used. This is particularly effective in a system in which, for example, the line quality is significantly deteriorated and the C / N of the received signal may be deteriorated.

Further, according to the third aspect of the invention, when the cumulative addition value obtained in the synchronization acquisition operation does not satisfy the fourth condition, the process of confirming the synchronization timing using all the correlations of the spread codes is performed. On the other hand, when the fourth condition is satisfied, the process of confirming the synchronization timing is omitted and the synchronization holding operation is directly performed. Therefore, when the line quality is deteriorated, the synchronization timing can be accurately established by the synchronization timing confirmation process. On the other hand, when the line quality is good and the synchronization timing need not be confirmed, synchronization is established in a relatively short time. It becomes possible to do.

[0017]

【Example】

(First Embodiment) FIG. 1 is a circuit block diagram showing the configuration of a digital radio communication apparatus having a spread spectrum code synchronizing circuit according to the first embodiment of the present invention. A radio frequency signal transmitted from a base station (not shown) is transmitted to the antenna 1
After being received at 1, the signal is input to a receiving circuit (RX) 13 via an antenna duplexer (DUP) 12, where high frequency amplification and high frequency filtering processing is performed and then input to a mixer (MIX) 14. In the mixer 14, the radio frequency signal is mixed with the reception local oscillation signal generated from the frequency synthesizer (SYN) 15 and converted into an intermediate frequency signal or a baseband signal, and the frequency converted reception signal is converted into a code synchronization circuit 16 And to the despreading circuit 17.

The code synchronization circuit 16 is a circuit for establishing code synchronization between the received signal and a pseudo noise code (PN code) as a reference spread code, and the synchronization information is notified to the control circuit 30. The despreading circuit 17 performs spectrum despreading processing on the received signal with the PN code generated from the code synchronization circuit 16, and thereby identifies the signal addressed to itself. A digital demodulation circuit (DEM) 18 performs digital demodulation processing on the despread reception signal. As a digital modulation / demodulation method, for example, π /
The 4-shift QPSK method is used.

The demodulated received signal is subjected to error correction decoding processing in an error correction code decoding circuit (CH-COD) 19 and then a voice code decoding circuit (SP-COD) 20.
The voice decoding processing is performed by this, and thereby the digital call signal is reproduced. And this digital call signal is P
After being converted into an analog call signal by the CM code decoding circuit (PCM-COD) 21, it is supplied to the speaker 23 via the receiving circuit 22 and is output from the speaker 23 in a loud voice.

On the other hand, the transmission voice signal output from the microphone 24 is input to the PCM code decoding circuit 21 via the transmission circuit 25, is converted into a digital transmission signal here, and then is transmitted to the voice code decoding circuit 20. Is entered. And
After being voice coded by the voice code decoding circuit 20, it is further error correction coded by the error correction code decoding circuit 19 and then input to the digital modulation circuit (MOD) 26. The digital modulation circuit 26 digitally modulates the encoded digital transmission signal,
This modulated transmission signal is input to the spreading circuit 27 as a secondary modulation circuit.

The spreading circuit 27 performs spread spectrum processing on the modulated transmission signal with a PN code as a spreading code, thereby converting it into a wideband transmission signal. This transmission signal is converted into a radio frequency signal by the mixer 28 and input to the transmission circuit (TX) 29. After being high frequency amplified by this transmission circuit 29, it is transmitted from the antenna 11 to the base station via the antenna duplexer 12. To be done.

The control circuit 30 is provided with, for example, a microcomputer as a main control unit and has a function of comprehensively controlling wireless line connection control, communication control and the like. . Reference numeral 31 denotes a console unit (CU). The console unit 31 includes an operation input section including dial keys and various function keys, a liquid crystal display for displaying a telephone number and various operating states of the device, and a light emission. A display unit such as a diode is arranged.

The code synchronizing circuit 16 is constructed as follows. FIG. 2 is a circuit block diagram showing the configuration. The code synchronization circuit 16 includes a synchronization acquisition circuit 40, a synchronization holding circuit 50, a PN code generator 60, and a switch control circuit 70 and a switch circuit 71 for switching these circuits.

First, the synchronization acquisition circuit 40 includes the correlation detection circuit 4
1, a switching circuit 42, a synchronization candidate selection circuit 43, and an m-cycle counter 44 attached to the synchronization candidate selection circuit 43, and a cumulative addition circuit 45 for cumulatively adding the squared correlation value R ^2. Further, an n-cycle counter 46 provided in association with the cumulative addition circuit 45, a memory 47, a timing counter 48, and a cumulative addition value comparison circuit 49 are provided.

Of these, the correlation detection circuit 43 detects the partial correlation between the received signal and the PN code as the reference spread code, and is constructed as shown in FIG. 3, for example. That is, the received signal is split into two and input to the mixers 411 and 412. At the same time, the mixers 411 and 412 are respectively supplied with local oscillation signals having the same frequency as the reception frequency generated by the local oscillator 413 and then provided with a phase shift difference of π / 2 by the phase shifter 414. Therefore, the mixer 411,
In 412, the received signal is quadrature-detected into baseband I and Q component signals by the local oscillation signal, and the quadrature-detected received signals are respectively matched filters (M
F) Input to 415 and 416.

The matched filters 415 and 416 are composed of, for example, as shown in FIG. 4, a sampling circuit 90, a delay line 91 with a tap for a reception signal, a delay line 92 with a tap for a PN code, and an adder circuit 93. It The received signal is sampled at a predetermined cycle by the sampling circuit 90, and then the delay line 91 with a tap for the received signal is used.
Shift input in series. On the other hand, a part of the PN code generated by the PN code generator 60 is fixedly stored in the tapped delay line 92 for the PN code, and this partial PN code is input in parallel to the adder circuit 93. It In the adder circuit 93, every time the received signal is shifted into the tapped delay line 91 by 1 bit, a parallel output of the received signal and the partial PN stored in the tapped delay line 92 are output.
Addition with the code is performed, and the cumulative addition value is serially shifted and output as a correlation value. Correlation outputs output from these matched filters 415 and 416 are squared in squaring circuits 417 and 418, respectively, and then added to the adder 4.
They are added together at 19 and output as a squared correlation value R ² .

The switching circuit 42 is switched by the switching control signal output from the switch control circuit 70, whereby the squared correlation value R ² output from the correlation detection circuit 41.
Is output to either the synchronization candidate selection circuit 43 or the R ² addition circuit 45.

The synchronization candidate selection circuit 43, in the m cycle period of the PN code set by the m cycle counter 44,
First, the square correlation value R output from the correlation detection circuit 41.
And compared with a preset threshold value ² is extracted or more square correlation value R ² threshold, further the extracted predetermined number signal level in descending order from the square correlation values R ² (e.g. 3 Individual) squared correlation value R ² is selected as the synchronization candidate timing. Then, these synchronization candidate timings are stored in the memory 47 and are supplied to the timing counter 47.

The timing counter 48 outputs a timing signal each time it starts counting time based on each of the selected synchronization candidate timings and measures one cycle of the PN code.

The accumulating circuit 45 is arranged so that the PN code designated by the n-cycle counter 46 is followed by n cycles of the m-cycle period.
During the cycle period, the square correlation value R ² stored in the memory 47 is cumulatively added to the square correlation value R ² output from the correlation detection circuit 41 every time one cycle of the PN code elapses. The timing of the addition is the timing counter 4 described above.
It is set by the timing signal output from 7. Then, when the n-cycle period ends, the cumulative addition circuit 45
Stores the value obtained by the cumulative addition in the memory 47.

The cumulative value comparison circuit 49 compares the cumulative added values stored in the memory 47 with each other, selects the cumulative added value having the highest signal level from among them, and selects the cumulative added value of the selected cumulative added values. The switch control circuit 70 is notified of the timing as the synchronization timing.

The switch control circuit 70 controls the switching circuit 42 to switch in synchronization with the timing signals output from the m-cycle counter 44 and the n-cycle counter 46, and the synchronization timing output from the cumulative value comparison circuit 49. The switch circuit 71 is switched from the synchronization acquisition circuit 40 side to the synchronization holding circuit 5 side in synchronization with the signal. Further, the PN code generation timing by the PN code generator 60 is controlled in synchronization with these switching timings.

Next, the operation of the spread spectrum code synchronization circuit configured as described above will be described with reference to FIG.
When communication is started, first, a synchronization candidate selection period is set. That is, the switch circuit 71 causes the switch circuit 71 to output the synchronization control circuit 4 according to the switch control signal output from the switch control circuit 70.
The switching circuit 4 set to the 0 side and in the synchronization acquisition circuit 40
2 is switched and set to the synchronization candidate selection circuit 43 side.

Then, the received signal is the switch circuit 71.
Is input to the correlation detection circuit 41, and the partial correlation with the PN code generated from the PN code generator 60 is detected in this circuit 41. That is, in the matched filters 415 and 416 in the correlation detection circuit 41, every time the received signal is shifted into the tapped delay line 91 by 1 bit, the received signal and the PN code held in the tapped delay line 92 are converted. A part of the sum is added by the adder circuit 93, and the cumulative addition value is output as a correlation value. This partial correlation detection operation is performed by the PN designated by the m cycle counter 44.
It is performed in the period of m cycles of the code. FIG. 5 shows a case where this m cycle period is set to two cycles of the PN code.

The squared correlation value R ² output from the correlation detection circuit 41 during the m-cycle period is input to the synchronization candidate selection circuit 43 via the switching circuit 42. Then, in this synchronization candidate selection circuit 43, a squared correlation value R ² having a level higher than the threshold value is extracted, and three squared values having a higher level are selected from the extracted plurality of squared correlation values R ^2. The correlation value R ² is selected as the synchronization candidate timing.
Then, the square correlation value R ² selected as the synchronization candidate timing is stored in the memory 47.

Then, when the m cycle period for selecting the synchronization candidate ends, the n cycles of the PN code are continuously generated.
The power correlation value R ² cumulative addition period is set. FIG. 2 shows a case where this n cycle period is set to two cycles.

That is, m from the m period counter 44
When the signal indicating the end of the cycle is output, the switch control circuit 70 outputs a switching control signal, which causes the switching circuit 42 to switch from the synchronization candidate selection circuit 43 side to the cumulative addition circuit 45 side. Then, in the cumulative addition circuit 45, each time the square correlation value R ² as a synchronization candidate stored in the memory 47 has passed one cycle of the PN code and the timing signal is output from the timing counter 48, The square correlation value R ² output from the correlation detection circuit 41 is cumulatively added and stored in the memory 47. When this cumulative addition operation is performed for the period of n cycles, the cumulative value comparison circuit 49 compares the cumulative addition values stored in the memory 47 with each other to select the cumulative addition value having the maximum level. Then, the timing corresponding to the cumulative addition value of the maximum level is used as the synchronization timing.

When the n-cycle period for detecting the maximum level cumulative addition value is completed, the n-cycle counter 46 is completed.
The switch control circuit 70 outputs a switch control signal to the switch circuit 71 in accordance with the count output of the switch circuit 71. As a result, the switch circuit 71 switches from the synchronization acquisition circuit 40 side to the synchronization holding circuit 50 side. Further, at this time, timing information corresponding to the maximum level cumulative addition value detected by the cumulative value comparison circuit 49 is output from the timing counter 48 to PN.
It is supplied to the code generator 60. Therefore, the timing of the PN code generated from the PN code generator 60 is reset in synchronization with the above-mentioned timing information, so that the synchronization holding circuit 50 thereafter carries out the synchronization holding operation based on the reset PN code.

As described above, in the present embodiment, first, the synchronization candidate selection period corresponding to the m period period of the PN code is set,
During this period, the correlation detection circuit 41 performs partial correlation using a part of the PN code, and among the correlation values detected by this partial correlation, three correlation values in descending order of the correlation value among the correlation values above the threshold value. Is selected as the synchronization candidate timing by the synchronization candidate selection circuit 43. Next, a cumulative addition period corresponding to the n cycle period is set, and during this period, the cumulative addition value of each correlation value selected as the synchronization candidate timing is calculated by the cumulative addition circuit 45, and the cumulative addition value of these cumulative addition values is calculated. The cumulative addition value of the maximum level is calculated by the cumulative value comparison circuit 49.
The timing of the selected cumulative addition value is selected as the synchronization timing, and thereafter the synchronization holding circuit 50 holds the synchronization.

Therefore, in this embodiment, since the correlation detection circuit 41 detects the partial correlation of the PN code, the tapped delay line 9 of the matched filters 415 and 416 is used.
1, 92 and the number of stages of the adder circuit 93 can be reduced, whereby the circuit configuration of the matched filters 415, 416 can be downsized, and the circuit scale of the entire synchronous circuit can be downsized. This effect is extremely useful in a mobile communication terminal such as a mobile phone in which miniaturization and weight reduction are one of the most important issues.

Further, among the correlation values obtained by the partial correlation, the correlation value whose level is equal to or higher than the threshold value is set to 3 in descending order.
Since the cumulative addition value of these correlation values is calculated, the cumulative addition value with the highest level is selected from among them, and the timing of this cumulative addition value is used as the synchronization timing. Despite the use of correlation, accurate synchronization acquisition can be performed without causing erroneous determination.

(Second Embodiment) FIG. 6 is a circuit block diagram showing the structure of a spread spectrum code synchronizing circuit according to the second embodiment of the present invention. In the figure, the same parts as those in FIG. 2 are designated by the same reference numerals and detailed description thereof is omitted.

The spread code code circuit of this embodiment is provided with the synchronization circuit 100 in addition to the synchronization acquisition circuit 40 and the synchronization holding circuit 50. The main synchronizing circuit 100 is
The synchronization timing captured by the synchronization capturing circuit 4 is used as a provisional synchronization timing for confirming whether or not the provisional synchronization timing is the correct synchronization timing, and is switched and connected by the switch circuit 81.

That is, when the n-cycle counter 46 of the synchronization acquisition circuit 40 outputs a count-up signal after the end of the n-cycle period, the switch control circuit 80 outputs a switching control signal to the switch circuit 81, which causes The switch circuit 81 switches from the synchronization acquisition circuit 40 to the main synchronization circuit 100. At this time, the cumulative addition value comparison circuit 49 of the synchronization acquisition circuit 40 outputs the cumulative addition value of the maximum level obtained by the synchronization acquisition operation of the synchronization acquisition circuit 40 to notify the main synchronization circuit 100. Further, the timing signal output from the timing counter 48 is given to the PN code generator 60, and the PN code generator 60 resets the generation timing of the reference PN code in synchronization with this timing signal.

The synchronizing circuit 100 uses the received signal and the reference P generated from the PN code generator 60 with reference to the timing corresponding to the notified cumulative addition value of the maximum level.
The correlation with the N code is detected. In this correlation detecting operation, the correlation with the received signal is detected by using one cycle of the reference PN code. When the correlation value obtained in this correlation detection operation is equal to or higher than a predetermined level, the synchronization circuit 100 recognizes that the temporary synchronization timing detected by the synchronization acquisition circuit 40 is a correct synchronization timing, and the switch control circuit. The main synchronization detection signal is output to 80. Then, a switch control signal is output from the switch control circuit 80 to the switch circuit 81, whereby the switch circuit 81 switches from the main synchronization circuit 100 to the synchronization holding circuit 50. Therefore, thereafter, the synchronization holding circuit 50 performs the synchronization holding operation of the main synchronization timing detected by the main synchronization circuit 100.

On the other hand, when the correlation value detected in the synchronization timing confirmation operation does not reach the predetermined level, the synchronization circuit 100 determines that the temporary synchronization timing is incorrect. Then, the cumulative addition value having the second largest level is read from the plurality of cumulative addition values stored in the memory 47 of the synchronization acquisition circuit 40, and the timing corresponding to this cumulative addition value is set as the temporary synchronization timing. The confirmation operation of the synchronization timing is performed using the entire one cycle of the reference PN code. When it is confirmed by this confirmation operation that the temporary synchronization timing is the correct synchronization timing, the main synchronization circuit 100 outputs a main synchronization detection signal to the switch control circuit 80, whereby the switch circuit 81 is switched, and thereafter, Sync holding circuit 50
Shifts to the synchronous holding operation.

Thus, the synchronization timing for the PN code is established. As described above, in the present embodiment, when the maximum level cumulative added value is detected in the synchronization acquisition circuit 40, the switch circuit 81 switches from the synchronization acquisition circuit 40 to the main synchronization circuit 100. A confirmation operation of the timing corresponding to the cumulative addition value of the levels is performed. Then, if it is determined by the confirmation operation that the above timing is correct, the timing is thereafter set as the main synchronization timing, and the synchronization holding operation is performed.

Therefore, according to the present embodiment, the probability of erroneous synchronization is reduced even when used in a system in which the quality of the wireless line is apt to deteriorate, so that highly reliable code synchronization can be performed. You can

(Third Embodiment) In the second embodiment, when the maximum level cumulative addition value is obtained in the synchronization acquisition circuit 40, the synchronization acquisition circuit 40 is switched to the main synchronization circuit 100, and this main synchronization circuit is switched. In 100, it is confirmed whether or not the timing corresponding to the cumulative addition value is correct. That is, the synchronization acquisition circuit 40 is unconditionally switched to the main synchronization circuit 100 to check the synchronization timing. However, depending on the state of the wireless line, the synchronization timing confirmation operation by the synchronization circuit 100 may not always be necessary.

Therefore, in the present embodiment, when switching from the synchronization acquisition circuit 40 to the main synchronization circuit 100, the synchronization acquisition circuit 4
It is determined whether or not the cumulative addition value of the maximum level obtained by 0 is equal to or higher than a predetermined level, and if it is less than the predetermined level, the synchronization acquisition circuit 40 is switched to the main synchronization circuit 100, and the main synchronization circuit 100 The operation for confirming the timing corresponding to the cumulative added value is performed, and when it is equal to or higher than the predetermined level, it is determined that the operation for confirming the synchronization timing by the synchronizing circuit 100 is unnecessary, and the synchronization holding operation by the synchronization holding circuit 50 is performed as it is. I am trying to move to.

With this configuration, the synchronization confirmation operation by the main synchronization circuit 100, which is substantially unnecessary in the state where the quality of the wireless line is good, is omitted, and the code synchronization can be established in a short time. On the other hand, in the state where the quality of the wireless line is deteriorated, it is possible to reduce the problem of erroneous synchronization due to the synchronization confirmation operation by the synchronization circuit 100 and maintain the reliability of code synchronization high.

The present invention is not limited to the above embodiments. For example, in the synchronization acquisition operation, in the first embodiment, the synchronization candidate selection period (the m period of the PN code) and the cumulative addition period (the n period of the PN code) are set to two periods, but other values are set. You may set it. Further, these values of m and n may not be fixedly set but may be variably set according to the state of the wireless line.

Further, in the second embodiment, the synchronizing circuit 100
In the synchronization confirmation operation by P.P., the entire period of the PN code is used to detect the correlation with the received signal.
A part of the N code may be used to detect the correlation with the received signal. Further, the correlation detection operation using a part of the PN code and the correlation detection operation using the entire PN code may be switched depending on the quality of the wireless line.

In addition, the operation procedure of the synchronization acquisition operation by the synchronization acquisition circuit and the synchronization confirmation operation by this synchronization circuit, the configuration of these circuits, the type of system to be applied, the configuration of the wireless communication device, etc. Various modifications can be implemented without departing from the above.

[0055]

As described in detail above, in the first aspect of the invention, when the synchronization of the reference spread code with the received signal spectrum-spread by the spread code is established, first, the received signal and a part of the reference spread code are set. Of the spread code, and at least one correlation value satisfying a predetermined first condition is selected from the detected correlation values, and then the spreading code is detected from the detection timing of the selected correlation value. Of the received signal and a part of the reference spread code are cumulatively added for a plurality of cycles each time the time corresponding to one cycle of the above has passed, and the cumulative addition value satisfies the predetermined second condition. It is determined whether or not it is satisfied, and when it is determined that it is satisfied, the detection timing of the cumulative addition value is recognized as the synchronization timing.

Therefore, according to the present invention, it is possible to provide a synchronization circuit and a synchronization method for spread spectrum codes, in which the circuit scale is reduced and the probability of erroneous determination is reduced to improve the noise resistance performance. .

On the other hand, in the second invention, first, a correlation value between the received signal and a part of the reference spread code is detected, and a correlation value satisfying a predetermined first condition is detected from the detected correlation values. At least one, and then the correlation value between the received signal and a part of the reference spread code detected each time the time corresponding to one cycle of the spread code elapses from the detection timing of the selected correlation value. Is cumulatively added for a plurality of cycles, and it is determined whether or not the cumulative addition value satisfies a predetermined second condition. If it is determined that the second addition condition is satisfied, the detection timing of the cumulative addition value is set to the synchronization candidate timing. Recognize as. Then, the correlation value between the received signal and the entire one cycle of the reference spreading code is detected based on the recognized synchronization candidate timing, and whether or not the detected correlation value satisfies the predetermined third condition. If it is determined that the correlation value is satisfied, the detection timing of the correlation value is officially recognized as the main synchronization timing.

Therefore, according to the present invention, it is possible to provide a synchronization circuit and a synchronization method for a spread spectrum code capable of accurately detecting the synchronization timing even when the line quality is significantly deteriorated.

Further, in the third invention, it is determined whether or not the cumulative addition value satisfies the predetermined second condition, and when it is determined that the second condition is satisfied, the cumulative addition value is further increased. Determine whether the fourth condition is met,
When the fourth condition is satisfied, the timing corresponding to the cumulative addition value is recognized as the normal synchronization timing, while when the fourth condition is not satisfied, the timing corresponding to the cumulative addition value is synchronized. Recognize as a candidate timing. Then, when the synchronization candidate timing is recognized, the correlation value between the received signal and the entire one cycle of the reference spreading code is detected based on the recognized synchronization candidate timing, and the detected correlation value is detected. Is determined to satisfy a predetermined third condition, and when it is determined to be satisfied, the timing corresponding to the correlation value is recognized as a normal synchronization timing.

Therefore, according to the present invention, it is possible to prevent the occurrence of erroneous synchronization in the state where the line quality is deteriorated, and to reduce the time required for establishing the synchronization in the state where the line quality is good. A synchronization circuit and a synchronization method can be provided.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a digital wireless communication device including a spread spectrum code synchronization circuit according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing the configuration of a spread spectrum code synchronization circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit block diagram showing a configuration of a correlation detection circuit in the spread spectrum code synchronization circuit shown in FIG.

4 is a circuit block diagram showing a configuration of a matched filter in the correlation detection circuit shown in FIG.

FIG. 5 is a timing diagram used for explaining the operation of the spread spectrum code synchronization circuit shown in FIG.

FIG. 6 is a circuit block diagram showing a configuration of a spread spectrum code synchronization circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 11 ... Antenna 12 ... Antenna duplexer (DUP) 13 ... Reception circuit (RX) 14, 28 ... Mixer 15 ... Frequency synthesizer (SYN) 16 ... Code synchronization circuit 17 ... Despreading circuit 18 ... Digital demodulation circuit (DEM) 19 ... Error correction code decoding circuit (CH-COD) 20 ... Speech code decoding circuit (SP-COD) 21 ... PCM code decoding circuit (PCM-COD) 22 ... Reception circuit 23 ... Speaker 24 ... Microphone 25 ... Sending circuit 26 ... Digital Modulation circuit (MOD) 27 ... Spreading circuit 29 ... Transmission circuit 30 ... Control circuit 31 ... Console unit (CU) 40 ... Synchronization acquisition circuit 41 ... Correlation detection circuit 42 ... Switching circuit 43 ... Synchronization candidate selection circuit 44 ... m cycle counter 45 ... cumulative addition circuit 46 ... n cycle counter 47 ... memory 48 ... timing counter 49 Cumulative addition value comparison circuit 50 ... Synchronous holding circuit 60 ... PN code generator 70, 80 ... Switch control circuit 71, 81 ... Switch circuit 90 ... Sampling circuit 91 ... Received signal tapped delay line 92 ... PN code tap Delay line 93 ... Adder circuit 100 ... Main synchronizing circuit 411, 412 ... Mixer 413 ... Local oscillator 414 ... Phase shifter 415, 416 ... Matched filter (MF) 417, 418 ... Square circuit 419 ... Adder

Claims (6)

[Claims] 1. The transmission data is modulated, then spread spectrum is transmitted using a spreading code, and the received signal is despread using the same reference spreading code as the spreading code and then demodulated to reproduce the received data. In a spread spectrum code synchronization circuit provided in a wireless communication device, a correlation detection unit for outputting a correlation value between the received signal and a part of the reference spread code, and a correlation value output from the correlation detection unit. From the selecting means for selecting at least one correlation value satisfying the predetermined first condition, and the time corresponding to one cycle of the spreading code elapses from the timing corresponding to the correlation value selected by the selecting means. And a cumulative addition means for cumulatively adding the correlation values output from the correlation detection means for a plurality of cycles and outputting the cumulative addition value. A synchronization timing recognizing unit that determines whether or not the cumulative addition value output from the stage satisfies a predetermined second condition, and if it satisfies, recognizes the timing corresponding to the cumulative addition value as a normal synchronization timing. A spread spectrum code synchronization circuit comprising: 2. A spread spectrum code synchronization method for establishing code synchronization between a received signal spread spectrum by a spread code and a reference spread code, wherein a correlation value between the received signal and a part of the reference spread code is obtained. 1 process, a second process of selecting at least one correlation value satisfying a predetermined first condition from the correlation values obtained in the first process, and a second process selected in the second process. A third step of accumulatively adding a plurality of periods of correlation values between the received signal and a part of the reference spreading code, which is obtained each time a time period corresponding to one period of the spreading code elapses from the timing corresponding to the correlation value. And the cumulative addition value obtained by the third process is the predetermined second value.
And a fourth step of recognizing whether or not the condition of is satisfied and recognizing the timing corresponding to the cumulative addition value as a normal synchronization timing when the condition is satisfied. Method. 3. The transmission data is modulated and then spread spectrum is transmitted using a spreading code, and the received signal is despread using the same reference spreading code as the spreading code and then demodulated to reproduce the received data. In a spread spectrum code synchronization circuit provided in a wireless communication device, a first correlation detecting means for outputting a correlation value between the received signal and a part of the reference spread code, and a correlation output from the correlation detecting means. Selecting means for selecting at least one correlation value satisfying a predetermined first condition from among the values, and a time corresponding to one cycle of the spreading code from the timing corresponding to the correlation value selected by this selecting means And a cumulative addition means for cumulatively adding the correlation values output from the correlation detection means for a plurality of cycles and outputting the cumulative addition value. Synchronization candidate timing recognition for determining whether or not the cumulative addition value output from the adding means satisfies a predetermined second condition, and recognizing the timing corresponding to the cumulative addition value as the synchronization candidate timing when the predetermined second condition is satisfied. Means, second correlation detecting means for obtaining a correlation value between the received signal and all one cycle of the reference spreading code on the basis of the synchronization candidate timing recognized by the synchronization candidate timing recognizing means, and the second correlation detecting means. A synchronization timing recognition means for determining whether or not the correlation value obtained by the detection means satisfies a predetermined third condition, and recognizing the timing corresponding to the correlation value as a normal synchronization timing when the correlation value is satisfied. A spread spectrum code synchronization circuit comprising: 4. A spread spectrum code synchronization method for establishing code synchronization between a received signal spread spectrum by a spread code and a reference spread code, wherein a correlation value between the received signal and a part of one period of the reference spread code. And a second step of selecting at least one correlation value satisfying a predetermined first condition from the correlation values obtained in the first step, and a second step of The correlation values of the received signal and a part of one cycle of the reference spreading code, which are obtained each time the time corresponding to one cycle of the spreading code elapses from the timing corresponding to the selected correlation value, are accumulated for a plurality of cycles. Third to add
And the cumulative addition value obtained by the third process
Is determined and whether the condition corresponding to the cumulative addition value is recognized as a normal synchronization candidate timing when the condition is satisfied, and the synchronization recognized by the fourth process. A fifth step of obtaining a correlation value between the received signal and all one cycle of the reference spreading code with reference to the candidate timing, and the correlation value obtained by the fifth step satisfies a predetermined third condition. And a sixth step of deciding whether or not there is, and recognizing the timing corresponding to the correlation value as a normal synchronization timing when satisfying the above condition. 5. The transmission data is modulated and then spread spectrum is transmitted using a spreading code, and the received signal is despread using the same reference spreading code as the spreading code and demodulated to reproduce the received data. In a spread spectrum code synchronization circuit provided in a wireless communication device, a first correlation detecting means for outputting a correlation value between the received signal and a part of the reference spread code, and a correlation output from the correlation detecting means. Selecting means for selecting at least one correlation value satisfying a predetermined first condition from among the values, and a time corresponding to one cycle of the spreading code from the timing corresponding to the correlation value selected by this selecting means And a cumulative addition means for cumulatively adding the correlation values output from the correlation detection means for a plurality of cycles and outputting the cumulative addition value. Determination means for determining whether or not the cumulative addition value output from the addition means satisfies a predetermined second condition, and the cumulative addition value determined by this determination means to satisfy the second condition Determines whether or not the fourth condition is satisfied, and if the fourth condition is satisfied, the timing corresponding to the cumulative addition value is recognized as the normal synchronization timing, while the fourth condition is satisfied. If the synchronization candidate timing is recognized by the recognizing means, the recognizing means for recognizing the timing corresponding to the cumulative addition value as the synchronization candidate timing when the synchronization candidate timing is not recognized. Second correlation detecting means for obtaining a correlation value with all one cycle of the reference spread code, and the correlation value obtained by the second correlation detecting means satisfies a predetermined third condition. A spread spectrum code synchronization circuit comprising: a synchronization timing recognition unit that determines whether or not the timing corresponds to the correlation value as a normal synchronization timing when the correlation value is satisfied. 6. A spread spectrum code synchronization method for establishing code synchronization between a received signal spectrum spread by a spread code and a reference spread code, wherein a correlation value between the received signal and a part of one period of the reference spread code. And a second step of selecting at least one correlation value satisfying a predetermined first condition from the correlation values obtained in the first step, and a second step of A plurality of cycles of cumulative addition of correlation values between the received signal and a part of one cycle of the reference spreading code, which is obtained each time a time corresponding to one cycle of the spreading code has elapsed from the detection timing of the selected correlation value. And a cumulative addition value obtained by the third process
And a fourth step for determining whether or not the condition of is satisfied, and whether or not the cumulative addition value determined to satisfy the second condition by the fourth step satisfies the fourth condition. If the fourth condition is satisfied, the timing corresponding to the cumulative addition value is recognized as the normal synchronization timing, while if the fourth condition is not satisfied, the cumulative addition value is handled. A fifth step of recognizing the timing to be performed as the synchronization candidate timing, and when the synchronization candidate timing is recognized in the fifth step, based on the recognized synchronization candidate timing,
A sixth step of obtaining a correlation value between the received signal and one cycle of the reference spread code, and it is determined whether or not the correlation value obtained by the sixth step satisfies a predetermined third condition. And a seventh step of recognizing the timing corresponding to the correlation value as a normal synchronization timing when the correlation value is satisfied, the spread spectrum code synchronization method.