JPH0730412A - Pll circuit and tv signal processor using the circuit - Google Patents

Abstract

PURPOSE:To make it unnecessary to adjust the center frequency of a VCO by controlling the frequency of the VCO in the 1st high speed PLL circuit having high frequency by a control signal generated from a low speed PLL circuit. CONSTITUTION:Since a reference control signal generating circuit 4 forms a PLL feedback loop for reference frequency (fos) from a bias circuit 44 to an active filter 41, the phase of the filter 41 is stabilized by a phase difference 90 deg. from the output of a frequency conversion circuit 40 and the circuit 44 generates bias voltage corresponding to the phase difference and sends the bias voltage to respective active filters 41, 31. Thereby a center frequency setting circuit 3 also forms a PLL for the same frequency (fos) as the reference frequency (fos) by a route consisting of bias circuit 23, a VCO 20, a frequency conversion circuit 30, and the active filter 31 and a voltage value outputted from a loop filter 33 controls the low speed PLL circuit so as to maintain it at frequency (fo).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit and a TV signal processing apparatus using the same, and more specifically to a video intermediate frequency signal of a TV image receiving apparatus by pseudo-synchronous detection or P
PLL for generating a video signal by LL synchronous detection or generating a detection reference signal for synchronous detection of an FM audio signal
The present invention relates to a PLL circuit in which the oscillation center frequency (hereinafter referred to as the center frequency) in the VCO free running can be adjusted.

[0002]

2. Description of the Related Art When a video signal is obtained by a TV receiver, it is necessary for the synchronous detection when the video signal is obtained by pseudo-synchronous detection by receiving a signal from an intermediate frequency stage of the image (hereinafter, intermediate frequency stage) or by PLL synchronous detection. A different detection reference signal is generated. In this case, the PLL circuit normally receives the output of the intermediate frequency stage as an external signal and obtains the result of comparison by the phase comparison circuit through an LPF (low pass filter).
The voltage of the (voltage controlled oscillator) is controlled to obtain a predetermined reference signal from the VCO.

[0003]

However, in order to stably control the frequency of the VCO, it is necessary that the oscillation frequency of the VCO at the center of the control range be a predetermined frequency. For example, in pseudo-synchronous detection when a video signal is obtained by a TV receiver, the center frequency thereof needs to match the reference frequency of the intermediate frequency stage. On the other hand, in the intermediate frequency stage, an LC oscillation circuit is often used in a high frequency range of about several tens of MHz or more, and it is common to use an LC oscillation circuit for each circuit due to slight differences in characteristics of elements and ICs. The frequency varies and the free running frequency must be adjusted. Therefore, conventionally, an adjusting circuit for adjusting the center frequency of the VCO to the frequency of the intermediate frequency stage is provided.

Normally, the intermediate frequency stage has a band of about 60 MHz in the NTSC system. Therefore, the VCO frequency is adjusted by an external coil or the like, and the adjustment work is required and the circuit is integrated into an IC. There are drawbacks when it comes to external adjustment parts. An object of the present invention is to solve the above problems of the prior art, and to provide a PLL circuit that does not require adjustment of the center frequency of the VCO. Another object of the present invention is to provide a TV signal processing device capable of unadjusting the TV video signal detection circuit.

[0005]

The feature of the PLL circuit of the present invention is that it is provided with first, second and third PLL circuits,
The first PLL circuit includes a VCO that oscillates at a high frequency,
The second PLL has a phase comparison circuit that compares the phases of the VCO and an external signal, and a control voltage generation circuit that controls the frequency of the VCO according to the comparison result of the phase comparison circuit.
The circuit has a frequency conversion circuit that converts a signal corresponding to the center frequency of the oscillation frequency of the VCO into a low frequency instead of the VCO provided inside, and a first phase shifter that receives the output of the frequency conversion circuit. And a control signal obtained as a result of the phase comparison as a signal for controlling the frequency of the VCO. The third PLL circuit has a reference frequency generating circuit having the same frequency as the low frequency in place of the VCO provided inside, and receives the output of the reference frequency generating circuit. A second phase shifter is provided to compare the output of the reference frequency generating circuit and the output of the second phase shifter, and the control signal obtained as a result of the phase comparison is used as the second phase shifter. vessel A control signal for fixing the phase shift angle, wherein the first phase shifter and the second phase shifter have the same configuration and substantially the same characteristics, and the control signal fixes the phase shift angle of the second phase shifter. Is a control signal for fixing the phase shift angle of the first phase shifter.

[0006]

As described above, in the low frequency range obtained by frequency-converting the center frequency of the VCO, the third P based on the reference frequency is generated.
A control signal for fixing the phase shift angle of the phase shifter is generated by the LL circuit, and the second low speed PL is adjusted by this control signal without adjustment.
The phase shift angle of the phase shifter of the L circuit is fixed. As a result, the low-speed PLL circuit is fixed to a low frequency obtained by frequency-converting the center frequency. Therefore, the VCO center frequency of the first high-speed PLL circuit is controlled by controlling the frequency of the VCO of the first high-speed PLL circuit having a high frequency (in other words, a short cycle) by the control signal generated by the low-speed PLL circuit. Can be controlled to be held in a low speed state (long cycle). That is, the control voltage of the low-speed PLL circuit controls the VCO of the high-speed PLL circuit so that it always matches the center frequency by the control signal of the low-speed PLL circuit when there is no external signal or when the external signal is equal to the center frequency.

On the other hand, the variation in the characteristics of each circuit is caused by the high speed P.
Since the frequency is set to be lower than the frequency of the LL circuit, there is almost no influence as in the case of high frequency. Conversely, the control frequency of the low-speed PLL circuit has dropped to a frequency in the range where the specific variation of the circuit does not affect. Then, the phase difference from the external signal becomes a phase difference with respect to this center frequency in the high frequency region, a control signal corresponding thereto is newly added, and the VCO is PLL controlled, and the center frequency is held in the low frequency region. Such control is automatically performed. This makes the VCO
No need to adjust the free running frequency.

[0008]

1 is a block diagram of an embodiment of a PLL circuit of the present invention, and FIG. 2 is an overall explanatory view of a TV receiver using the PLL circuit of FIG. Reference numeral 1 is a PLL circuit, which is a high-speed PLL circuit that operates in a high frequency region.
A center frequency setting circuit 3 composed of a PLL circuit operating in a low frequency region, and a reference control signal generating circuit 4 composed of a PLL circuit operating in the same low frequency region and a reference frequency. Consists of.

The high-speed PLL circuit 2 is, for example, 58.75.
VCO 20 and VCO that oscillate with a center frequency of MHz
20. The phase comparison circuit 21 receiving the output of 20, the loop filter 22 corresponding to the low-pass filter receiving the comparison result from the phase comparison circuit 21, the signal filtered by the loop filter 22 and the signal filtered by the loop filter 33, respectively. And a bias circuit 23 for generating a control voltage signal for controlling the oscillation frequency of the VCO 20.

The bias circuit 23 adds the respective signals filtered by the loop filters 22 and 33 (or subtracts the signals when the loop filter 22 side is negative) to generate a control voltage for the VCO 20. The signal filtered by the loop filter 33 is oscillated by the VCO 20 with a center frequency of 58.
It becomes a signal for generating the control voltage set to 75 MHz, and the signal filtered by the loop filter 22 is
It becomes a signal for generating a control voltage corresponding to the amount of deviation from the current oscillation frequency in order to synchronize with an external signal.

The center frequency setting circuit 3 receives the signal of the frequency fs from the reference signal oscillator 45, and for the center frequency of the VCO 20, sets it to the frequency fo (= 2M to 3MH).
z) a frequency conversion circuit (which can be a frequency divider) 30 for converting to a low frequency, and an output of this frequency conversion circuit 30,
The cutoff frequency is controlled according to the control signal,
For example, a second-order Butterworth low-pass active filter 31, a phase comparison circuit 32 that receives the output of the frequency conversion circuit 30 and the output of the active filter 31 and compares the phases of these signals, and the comparison result from this phase comparison circuit 32. A loop filter 33 corresponding to the low-pass filter to be received
The output of the loop filter 33 is sent to the bias circuit 23 as a control signal.

The active filter 31 is, for example, 90 ° with respect to the output of the frequency conversion circuit 30 (the signal of the cutoff frequency) by making the cutoff frequency correspond to the frequency of the output of the frequency conversion circuit 30. It is a phase shifter that generates an output having a phase difference (phase delay) of. Therefore, the comparison result of the phase comparison circuit 32 generates a signal having a phase difference of 90 degrees with respect to the input signal having the cutoff frequency when the active filter 31 has an accurate cutoff characteristic. The phase difference here is not limited to 90 degrees and may be a predetermined phase difference set in advance.

The reference control signal generation circuit 4 receives a signal of frequency fs from the reference signal oscillator 45 and converts it into a reference frequency fos having the same frequency as the frequency fo and having almost no frequency fluctuation. A secondary active filter 4 which receives the output of the frequency conversion circuit 40 and whose cutoff frequency is controlled according to a control signal.
1. Output of frequency conversion circuit 40 and active filter 4
1 and a phase comparison circuit 42 for comparing the phases of these signals, a loop filter 43 corresponding to a low-pass filter that receives the comparison result from the phase comparison circuit 42, and an output of the loop filter 43. The bias circuit 4 for generating a feedback control signal such that the cutoff frequency of the secondary active filter 41 becomes fo.
4 and the output of the bias circuit 44 is sent to the secondary active filters 31 and 41. Here, the active filters 31 and 41 are filters having the same configuration and uniform characteristics, and in this case, the bias circuit 44 is such that the active filter 41 has a phase difference of 90 degrees with respect to the input signal of the cutoff frequency fo. A control value for feedback control is generated so as to operate as a phase shifter having.

The operation of the reference control signal generating circuit 4 will be described below.
Since the PLL feedback loop based on the reference frequency fos is formed with respect to 1, the bias circuit 44
With respect to the output of the frequency conversion circuit 40, the phase of the output of the active filter 41 is stabilized with a phase difference of 90 degrees, and a bias voltage (current value is possible) corresponding to the phase difference is generated. This is sent to each of the active filters 41 and 31. As a result, the active filter 4
The filter characteristics of 1 and 31 are the same, and the loop of the center frequency setting circuit 3 is bias circuit 23, VCO 20, frequency conversion circuit 3 with respect to the same frequency fo as the reference frequency fos.
0, a PLL is formed by the route of the active filter 31, and the voltage value (current value is also possible) output from the loop filter 33 is controlled so that this low-speed PLL circuit is maintained at the frequency wave number fo.

On the other hand, the frequency wave number fo is obtained by frequency-converting the center frequency of the output of the VCO 20, so that the voltage value output from the loop filter 33 has the oscillation frequency of the VCO 20 in the high-speed PLL circuit 2 as the center frequency. It becomes the value to maintain. Here, it is important to note that the frequency fs generated by the reference signal oscillator 45 rarely varies depending on the manufactured IC, and the characteristics of the active filters 41 and 31 are the same within the same IC. Since each frequency conversion circuit, the loop filter, the bias circuit, and the like handle a low frequency that is 1/10 or less of the frequency of the high-speed PLL circuit 2, there is no fluctuation that requires adjustment. is there.
As a result, the phase shift angle of the active filter 31, which is the phase shifter, with respect to the frequency fo can be unadjusted and the filter characteristic can be fixed. Therefore, the center frequency setting circuit 3 of the low-speed PLL
Becomes stable PLL control with respect to the frequency fo. Therefore, the voltage value output from the loop filter 33 is the VC of the high-speed PLL circuit 2 even if it is not adjusted.
The control value is sufficient to set O20 to the center frequency.

FIG. 2 shows a TV having the PLL circuit 1 shown in FIG.
Denoting a receiver, 51 is an antenna,
Reference numeral 52 is a tuner, and 53 is an amplifier circuit (IFAMP) at the intermediate frequency stage described above. 54 is a video detection circuit,
55 is an audio detection circuit, 56 is a video signal processing circuit, 5
Reference numeral 7 is an audio amplifier circuit (audio AMP), 58 is a cathode ray tube, and 59 is a speaker.

Here, the VCO 20 of the PLL circuit 1 of FIG.
Is sent to the video detection circuit 54 as a reference signal for pseudo-synchronous detection, and the IFAM received by the video detection circuit 54.
The video intermediate frequency signal from P53 is detected. As a result, a video signal is extracted, and this is processed by a video signal processing circuit 56 including a so-called monitor circuit and applied to the cathode ray tube 58. In addition, the VCO of the PLL circuit 1
The output of 20 is sent to the voice detection circuit 55 as a reference signal for PLL synchronous detection, where the FM voice is demodulated. Then, it is amplified by the audio AMP 57 and added to the speaker 59.

As described above, the circuit used as the phase shifter may be any circuit, but a circuit that can be easily integrated into an IC is preferable. Further, the phase shift angle is not limited to 90 degrees, and any phase may be fixed as long as the phase is fixed with respect to the conversion frequency fo. In the embodiment, the high-speed PLL circuit is converted into the low-frequency PLL circuit, but the conversion frequency may be converted to a low frequency so that adjustment is unnecessary, and is limited to 2 to 3 MHz of the embodiment. is not.

[0019]

As can be understood from the above description, according to the present invention, the high speed first PLL circuit and the low speed second and third PLL circuits are provided, and the center frequency of the VCO is controlled. A control signal for fixing the phase shift angle of the phase shifter is generated by the third PLL circuit based on the reference frequency in the frequency-converted low frequency region, and the control signal causes the phase shifter of the second low-speed PLL circuit without adjustment. The phase shift angle of is fixed.
This fixes the low-speed PLL circuit to a low frequency obtained by frequency-converting the center frequency. Then, the control of the VCO frequency of the first high-speed PLL circuit having a high frequency is controlled by this low-speed PLL
By controlling with the control signal generated in the circuit, the first high speed P
The center frequency of the VCO of the LL circuit can be held in a low speed state. As a result, the control voltage of the low-speed PLL circuit causes the VCO of the high-speed PLL circuit to operate at a low-speed PL when there is no external signal or when the external signal is equal to the center frequency.
It is controlled by the control signal of the L circuit so as to always match the center frequency, and the adjustment of the VCO free running frequency becomes unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a PLL circuit of the present invention.

FIG. 2 is an overall explanatory diagram of a TV receiver using the PLL circuit of FIG.

[Explanation of symbols]

 1 PLL circuit, 2 high speed PLL circuit, 3 center frequency setting circuit, 4 reference control signal generation circuit, 20 VCO, 21, 31, 41 phase comparison circuit, 22, 33, 43 loop filter, 23, 44 bias circuit, 35 reference Oscillator.

Claims (3)

[Claims] 1. A first, second, and third PLL circuit, wherein the first PLL circuit includes a VCO that oscillates at a high frequency, and a phase comparison circuit that compares the phases of this VCO and an external signal. A control voltage generation circuit for controlling the frequency of the VCO in accordance with the comparison result of the phase comparison circuit,
The LL circuit uses the VC instead of the VCO provided inside.
An output of the frequency conversion circuit is provided which has a frequency conversion circuit for converting a signal corresponding to the oscillation center frequency of the oscillation frequency of O into a low frequency, and which receives the output of the frequency conversion circuit. And a phase comparison between the output of the first phase shifter and a control signal obtained as a result of the phase comparison is sent to the control voltage generation circuit as a signal for controlling the frequency of the VCO. Third PL
The L circuit has a reference frequency generating circuit having the same frequency as the low frequency in place of the VCO provided therein, and a second phase shifter for receiving the output of the reference frequency generating circuit is provided to generate the reference frequency. Comparing the phase of the output of the circuit and the output of the second phase shifter, the control signal obtained as a result of the phase comparison being a control signal for fixing the phase shift angle of the second phase shifter, The first phase shifter and the second phase shifter have the same structure and substantially the same characteristics, and the control signal for fixing the phase shift angle of the second phase shifter is a shift signal of the first phase shifter. A PLL circuit used as a control signal for fixing the phase angle. 2. A VCO that oscillates at a predetermined frequency, and this VCO
A phase comparison circuit that receives the output of CO and compares the phase of this with an external signal, a low-pass filter circuit that receives the output of this phase comparison circuit, and an output of this low-pass filter circuit as a first input The VCO in response to the first and second inputs
PLL loop circuit including a control voltage generation circuit that applies a control voltage for controlling the oscillation frequency of the VCO to the VCO, and a frequency conversion that receives the output of the VCO and converts the oscillation center frequency of the VCO to a frequency lower than that frequency. Circuit, a first phase shifter for receiving an output of the frequency conversion circuit and generating an output of a predetermined phase difference according to a first control signal, an output of the first phase shifter and the frequency conversion A center frequency setting circuit including a phase comparison circuit that compares the phase with the output of the circuit, and a low-pass filter circuit that receives the output of this phase comparison circuit and applies this output as the second input to the control voltage generation circuit. A frequency conversion circuit for frequency-converting the reference frequency signal to the low frequency, and a second circuit for receiving the output of the frequency conversion circuit
For generating an output of a predetermined phase difference according to the control signal of
, A phase comparison circuit for comparing the phases of the output of the second phase shifter and the output of the frequency conversion circuit, a low-pass filter circuit for receiving the output of the phase comparison circuit, and this low-pass filter. A control signal that causes the second phase shifter to generate a signal having a predetermined phase difference according to the output of the filter circuit is sent to the first and second phase shifters as first and second control signals. A PLL circuit including a control signal generation circuit, wherein the first and second phase shifters have substantially the same characteristics. 3. A TV signal processing apparatus for receiving a reference signal from a PLL circuit to obtain a video signal from a video intermediate frequency signal by pseudo-synchronous detection or PLL synchronous detection, wherein the PLL circuit includes a VCO oscillating at a predetermined frequency, A phase comparison circuit that receives the output of this VCO and compares the phase of this with an external signal, a low-pass filter circuit that receives the output of this phase comparison circuit, and the output of this low-pass filter circuit as a first input. A PLL loop circuit including a control voltage generation circuit that applies a control voltage for controlling the oscillation frequency of the VCO to the VCO according to first and second inputs, and an oscillation center frequency of the VCO that receives the output of the VCO A frequency conversion circuit for converting the frequency to a frequency lower than that frequency, and receiving the output of this frequency conversion circuit and responding to the first control signal. A first phase shifter that generates an output of a constant phase difference, a phase comparison circuit that compares the phase of the output of this first phase shifter with the output of the frequency conversion circuit, and the output of this phase comparison circuit A center frequency setting circuit including a low-pass filter circuit that receives the output as the second input to the control voltage generation circuit, a reference signal generation circuit, and a signal of the reference signal generation circuit to the low frequency. A frequency converting circuit for converting, a second phase shifter for receiving an output of the frequency converting circuit and generating an output of a predetermined phase difference according to a second control signal, and an output of the second phase shifter. And a low-pass filter circuit for receiving the output of the phase comparison circuit, and the second phase shifter according to the output of the low-pass filter circuit. Predetermined phase difference A control signal generating circuit for sending the control signal set to be generated to the first and second phase shifters as the first and second control signals, and the characteristics of the first and second phase shifters are A TV signal processing device characterized in that they are substantially equal.