JPH0730422A - Sampling clock generation circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if a DC voltage is superimposed on an AC input signal, it is not affected by it and generates an A / D conversion clock having a frequency n times (n ≧ 2) that of the input signal. Sampling clock generation circuit. [Structure] A high-pass filter that cuts a DC voltage superimposed on an input signal, a low-pass filter for anti-aliasing, a waveform shaper that forms a square-wave voltage with a duty ratio of 50%, an output of the waveform shaper, and a self-contained oscillator. A PLL circuit that outputs a sampling clock having a frequency n times that of the input signal in phase synchronization with the / n frequency division output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock generation circuit, and more specifically, to an A / D input signal
When the converter performs digital conversion, a sampling clock having a frequency n times that of the same signal is generated to generate A / D.
The present invention relates to a sampling clock generation circuit provided to a converter.

[0002]

2. Description of the Related Art An example of a conventional device is shown in FIG. The sampling clock generation circuit 1 includes, for example, a low pass filter 2
And a waveform shaper 3 and a PLL circuit 4. The low-pass filter 2 removes a noise component having a frequency of twice or more contained in the input signal, and prevents a folding error from occurring during A / D conversion. The waveform shaper 3 is composed of, for example, a zero cross comparator, and shapes the sine wave input signal applied from the low pass filter 2 into a square wave with a duty ratio of 50%.

The PLL circuit 4 divides the free-running oscillation frequency of an oscillator (not shown) into 1 / n and sets the oscillation frequency so that the divided signal is in phase with the square wave signal input from the waveform shaper 3. Control. When the phases are synchronized, the oscillation frequency of the PLL circuit 4 becomes n times the input signal frequency, and this signal is supplied to the A / D converter 5 as a sampling clock. The A / D converter 5 digitally converts the input signal at the timing of this clock and sends the data to the signal processing unit 6. The signal processing unit 6 performs processing specified by the device on the input data.

[0004]

The above-mentioned conventional sampling clock generation circuit has a relatively simple structure, and
The operation is also reliable for normal input signals. But,
Inconvenience occurs when a DC component or the like is superimposed on the input signal.

An example thereof is shown in FIG. 6A is an example in which a noise voltage and a positive DC voltage are superimposed on the input signal, for example. When such a signal is applied to the filter 2, the noise voltage having a relatively high frequency is removed, but the DC voltage cannot be removed, and the output waveform of the filter 2 is as shown in (B) of FIG. become. Therefore, the output waveform of the waveform shaper 3 becomes a square wave with an unbalanced duty ratio as shown in (C) of FIG.

In this case, since the duty ratio of the output waveform of the oscillator in the PLL circuit 4 is generally set to about 50%, the phase of the signal waveform obtained by dividing the frequency by 1 / n is a waveform of (c). If it is attempted to synchronize (lock in) with the phase of, the synchronization may become unstable or may become impossible depending on the degree of duty cycle imbalance. When synchronization is impossible, a signal obtained by dividing the free-running oscillation frequency of the oscillator by 1 / n serves as the sampling clock, as shown in (d) of FIG. 6A, and therefore has no relation to the frequency of the input signal. .

The example of FIG. 6B is the case where the level of the input signal is smaller than the positive DC voltage superimposed on the same signal. In this example, the zero-crossing comparator of the waveform shaper 3 swings to the positive side as shown in (C) of FIG. 6B, and synchronization becomes impossible. Therefore, the PLL circuit 4 does not operate normally, the sampling clock is fixed to the H level (or the L level shown by the broken line) as shown in FIG. 6B, (d), and the sampling is stopped.

When the sampling clock becomes a signal of 1 / n of the free-running oscillation frequency as described above, for example, for an input signal having a relatively low frequency, the number of sampling data in one wave period increases, and the memory of the signal processing unit, etc. May overflow and the number of sampling data for one wave period may be insufficient for an input signal having a relatively high frequency. In addition, if the sampling is stopped, naturally sampling is impossible.

By the way, whether or not the DC voltage is superposed on the signal input to the apparatus and its magnitude are generally influenced by the state of the signal supply source side. Therefore, in order to avoid the above-mentioned problems, it is necessary to check the presence or absence of the DC voltage on the apparatus side by other means each time, but it is extremely troublesome.

The present invention has been made in consideration of the above circumstances, and an object thereof is to always obtain a sampling clock proportional to n times the frequency of an input signal without the need to check the presence or absence of a DC voltage. It is to provide a sampling clock generation circuit.

[0011]

As described above, the DC voltage superimposed on the input signal is an unnecessary component for generating the sampling clock. Therefore, the gist of the present invention is to provide a high-pass filter for removing a DC component in the signal input section of the sampling clock generation circuit.

[0012]

By providing the above means, the DC voltage superimposed on the input signal is removed, and the voltage output from the waveform shaper becomes a square wave signal with a duty ratio of 50%. Therefore P
In the LL circuit, the phase period of the 1 / n frequency-divided signal of the oscillation frequency and the square wave signal becomes possible, and the sampling clock having a frequency n times as high as the input signal is obtained from the PLL circuit.

[0013]

FIG. 1 shows an embodiment of the present invention. In the figure, a sampling clock generation circuit 1a includes, for example, a high-pass filter 2a for removing a DC voltage superimposed on an input signal, a low-pass filter 2, a waveform shaper 3, and a PLL that are configured almost the same as the unit of the conventional device. And a circuit 4.

The operation of each unit will be described with reference to FIG. FIG. 2A shows a waveform of an input signal on which, for example, a positive DC voltage is superimposed. When this input signal is applied to the high pass filter 2a, its output is shown in FIG.
As shown in (b), the waveform has a DC voltage component removed. The output of the high-pass filter 2a is added to the low-pass filter 2 in the next stage, the noise component is removed and the original waveform of the input signal is obtained as shown in FIG.
Join in.

The waveform shaper 3 includes the low pass filter 2 described above.
The signal applied from is shaped into a square wave with a duty ratio of 50% by a zero cross comparator and output to the PLL circuit 4. This output waveform is shown in FIG.

The PLL circuit 4 sets the phase of the square wave signal applied from the waveform shaper 3 and the oscillation frequency of the internal oscillator to 1 / n.
Then, the oscillation frequency is controlled so that the phase of the 1 / n frequency-divided signal is synchronized with the phase of the square wave signal. In the phase locked state, the fundamental frequency of the square wave signal, that is, the fundamental frequency of the 1 / n frequency division signal matches the frequency of the input signal. The 1 / n frequency-divided signal at this time is shown in FIG. 2E, and the oscillation signal of the internal oscillator having a frequency n times that of the frequency-divided signal is shown in FIG. The signal shown in FIG. 2F is used as a sampling clock for the A / D converter 5.

FIG. 3 shows another embodiment of the sampling clock generation circuit to which the present invention is applied. In this embodiment, a switch S is provided on the input side of the low pass filter 2, and when the switch S is connected to the contact a side, the output of the high pass filter 2a is added to the low pass filter 2 and the switch S is connected to the contact b. When connected to the side, the input signal is directly added to the low-pass filter.

That is, when the switch S is connected to the contact a side, the sampling clock generating circuit 1a shown in FIG.
When the contact b is connected, the configuration is the same as that of the conventional sampling clock generation circuit 1 shown in FIG. Therefore, normally, for example, when the switch S is connected to the contact a to sample the input signal and it is known in advance that the DC voltage is not superimposed on the input signal,
The switch is connected to the contact b side for sampling.

When it is not clear whether or not the DC voltage is superimposed on the input signal, for example, the signal processing unit 6 is provided with data sampled by connecting the switch to the contact a side and sampled by connecting the switch to the contact b side. It is also possible to determine the presence / absence of a DC voltage by collecting the data and checking whether both data are the same. In the embodiment of FIGS. 1 and 3, the high pass filter 2a and the low pass filter 2 may be replaced with each other.

Further, another embodiment of the present invention is shown in FIG. The sampling clock generation circuit 1c in this embodiment includes, for example, a bandpass filter 2c, a waveform shaper 3, and a PLL circuit 4. Here, the bandpass filter 2c has the functions of the highpass filter 2a and the lowpass filter 2 shown in FIG. 1 or 3 in one unit, and simplification of the device configuration is achieved.

[0021]

As described above in detail, the sampling clock generation circuit according to the present invention is not affected by a DC component superposed on an AC input signal and is always affected by a frequency n times that of the input signal. A proportional sampling clock can be generated, and the configuration is relatively simple.

Therefore, when it is applied to an analog / digital converter of an electronic device that handles AC signals of various frequencies, the usability of the device can be greatly improved. Further, the structure is relatively simple, and a unit having a special function is not required, so that the range of use is wide.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a sampling clock generation circuit to which the invention is applied.

FIG. 2 is a waveform diagram for explaining the operation of the sampling clock generation circuit to which the invention is applied.

FIG. 3 is a block diagram showing a modified embodiment of the sampling clock generation circuit to which the invention is applied.

FIG. 4 is a block diagram showing an electrical configuration of another embodiment of the sampling clock generation circuit to which the invention is applied.

FIG. 5 is a block diagram showing an electrical configuration of a conventional device.

FIG. 6 is a waveform diagram for explaining the operation of the conventional device.

[Explanation of symbols]

 1a Sampling clock generation circuit 1b Sampling clock generation circuit 1c Sampling clock generation circuit 2 Low pass filter 2a High pass filter 2c Band pass filter 3 Waveform shaper 4 PLL circuit 5 A / D converter S switch

Claims (3)

[Claims] 1. An AC input signal is multiplied by n (n ≧) of the signal.
Generate a sampling clock having the frequency of 2),
In a sampling clock generation circuit for supplying the generated clock to an A / D converter that digitally converts the input signal, a high-pass filter that receives the AC input signal and removes a DC voltage component superimposed on the signal, and the high-pass filter From the AC signal transmitted by the low-pass filter, which removes a harmonic voltage component at least twice the frequency of the input signal to transmit the fundamental wave component voltage, and a fundamental wave component voltage of the input signal transmitted by the low-pass filter. Waveform shaper for forming a square wave voltage with a duty ratio of 50%, and an oscillator, and the phase and the square wave voltage input from the waveform shaper by dividing the oscillation frequency of the oscillator by 1 / n PL for synchronizing and providing the oscillation output of the oscillator as a sampling clock to the A / D converter A sampling clock generation circuit comprising: an L circuit. 2. A change-over switch is provided on the input side of the low-pass filter for adding to the low-pass filter either the AC signal sent by the high-pass filter or the AC signal input to the high-pass filter. The sampling clock generation circuit according to claim 1. 3. An AC input signal is multiplied by n (n ≧) of the signal.
Generate a sampling clock having the frequency of 2),
A sampling clock generation circuit that supplies the generated clock to an A / D converter that digitally converts the input signal, receives the AC input signal, removes an AC voltage component superimposed on the signal, and includes the AC voltage component. A bandpass filter that removes a harmonic voltage component that is at least twice the frequency of the input signal and sends the fundamental wave component voltage of the same input signal, and a fundamental wave component voltage of the input signal that is sent by the bandpass filter. Waveform shaper for forming a square wave voltage with a duty ratio of 50%, and an oscillator, and the phase and the square wave voltage input from the waveform shaper by dividing the oscillation frequency of the oscillator by 1 / n And a PLL circuit for synchronizing the oscillation output of the oscillator as a sampling clock to the A / D converter. Sampling clock generation circuit, characterized in that.