JPH0731777B2 - Automatic equalizer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic equalizer for automatically equalizing a reproduction signal from a recording medium when recording / reproducing a digital signal.

2. Description of the Related Art Conventionally, when a digital signal is recorded / reproduced, there is a problem that a peak shift occurs due to deterioration of transmission characteristics in a recording / reproduction system to increase an error in a reproduced digital signal. An equalization circuit is used to compensate for the deterioration of transmission characteristics. As the deterioration of the transmission characteristic, the deterioration of the high frequency component is particularly large, and particularly, as the equalization circuit, an equalization circuit that compensates for the deterioration of the high frequency component is used.

However, the transmission characteristics of the recording / reproducing system fluctuate according to the variations in the characteristics of the constituent elements. For example, in a magnetic recording / reproducing system, there are variations in the characteristics of the magnetic head, magnetic tape, etc., and variations in the characteristics due to variations in the space between the magnetic head and the magnetic tape.

Problems to be Solved by the Invention As described above, when there is a change in the transmission characteristic of the recording / reproducing system, if the equalization characteristic of the equalization circuit remains unchanged, the transmission characteristic of the equalization circuit changes according to the change. There may be cases where the compensation is insufficient.

Means for Solving the Problems The present invention is an equalization circuit that equalizes a reproduction signal from a recording medium on which a digital signal is recorded, and the equalization amount can be controlled by an external control signal. Two equalizer circuits having different equalization amounts, two waveform shaping circuits for waveform-shaping the reproduced signals from these equalizer circuits to obtain reproduced digital signals, and polarity reversal times of these reproduced digital signals are predetermined. Two counting circuits that count only the number of the parts within the range for a certain period, and an equalization amount that controls the equalization amounts of the two equalization circuits according to the two count values obtained by these counting circuits. A control signal generation circuit that generates a selection control signal that controls the control signal and the selection circuit, and a reproduction digital signal that is controlled by the selection control signal and that is output from two waveform shaping circuits is selected to output an optimum reproduction digital signal. This is an automatic equalizer using a selection circuit.

Action The reproduced signal from the recording medium is equalized differently by two equalization circuits having different equalization amounts. Further, the waveform is shaped by the waveform shaping circuit to obtain two reproduced digital signals. The polarity reversal time of these reproduced digital signals is
Compared with the recorded digital signal, it fluctuates due to various factors in the recording / reproducing system. The count value obtained by counting only a portion within the predetermined range of the polarity inversion time for a certain period of time indicates the degree of equalization superiority or inferiority, and the count values corresponding to the two reproduced digital signals are obtained from the two counting circuits. The control signal generation circuit generates an equalization amount control signal according to the magnitude relation of these count values, and supplies the equalization amount control signal to the two equalization circuits to control the equalization amount, so that equalization is optimized. Controlled by.
Further, a selection control signal corresponding to the magnitude relation is also generated and given to the selection circuit. In accordance with this selection control signal, the selection circuit selects and outputs the digital signal having the better equalization among the two reproduced digital signals.

As a result of the above operation, a reproduced digital signal that is optimally equalized is automatically obtained at the output of the selection circuit.

Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention. Reference numeral 1 is a magnetic head for obtaining a reproduction signal from a magnetic recording medium on which a digital signal is recorded, 2 and 3 are equalization circuits for equalizing the reproduction signal from the magnetic head 1, and 4 and 5 are reproduction signals from the equalization circuit. A waveform shaping circuit for shaping the waveform of the reproduced digital signal to obtain a reproduced digital signal, 6 and 7 are counting circuits for counting only a portion within a predetermined range of the polarity reversal time of the reproduced digital signal for a certain period of time, and 8 is a counting circuit 6, 7 Equalization circuit 2, 3 according to the count value
Control signal generation circuit for generating an equalization amount control signal for controlling the equalization amount and a selection control signal for controlling the selection circuit 9, and 9 is controlled by the selection control signal. A selection circuit for inputting the reproduction digital signal and selecting the reproduction digital signal that is more optimally equalized is a reproduction digital signal output terminal 10 for outputting the reproduction digital signal.

Next, before describing the operation of one embodiment of the present invention, the operation of the process of obtaining a digital signal to be recorded and a reproduced digital signal from a magnetic recording medium will be described.

FIG. 2 is a waveform diagram showing the waveform of this process. (A) shows the value of the recording digital signal at each time, and (b) shows the waveform of the recording digital signal. In this example, the waveform of the recorded digital signal is such that the polarity is inverted at the bit period T when it is "0" and the polarity is inverted at 1 / 2T when it is "1".
Digital information is transmitted due to the difference in the polarity inversion time. (C) is a waveform of the re-reproduced signal reproduced from the magnetic recording medium by the magnetic head, and has a peak (minimum or maximum) at a portion corresponding to the extreme reversal time point of the recorded digital signal due to the differential characteristic of the magnetic head. The waveform is as shown. Further, the peak shift of ΔT occurs due to the deterioration of the high frequency component of the recording / reproducing system. (D) shows the waveform of the reproduced signal obtained by equalizing the reproduced signal by the equalizing circuit, and the equalizing circuit compensates for the deterioration of the high frequency component, and the waveform has no peak shift. (E) is a waveform obtained by integrating the reproduction signal after this equalization, and is a waveform converted so that the peak portion becomes zero level. By passing this signal through a limiter, as shown in (f), The reproduced digital signal is reproduced.

If the equalization is not sufficient, the polarity inversion time of the reproduced digital signal does not have the same value as that of the recorded digital signal, but changes by the peak shift. Further, the polarity inversion time also varies due to noise generated in the recording / reproducing system. FIG. 3 is a diagram showing each polarity reversal time of the reproduced digital signal and the number of occurrences within a fixed time.
It becomes the maximum at 1 / 2T, and becomes smaller as it deviates from this value. Depending difference polarity inversion time is either 1 / 2T is T, it is possible to identify the digital information, T _M in the figure
Indicates the degree of margin of this discrimination. Below this
T _M is called time margin. Figure 4 shows that equalization is insufficient or
In the figure showing the case where the S / N ratio is bad, the time margin T _M is zero, which means that there are cases where this discrimination cannot be made.

As described above, since this time margin T _M changes according to the optimal degree of equalization, if this T _M is measured and the equivalent amount of the equalization circuit is controlled so that this T _M becomes maximum, It becomes possible to automatically specialize.

In the present invention, another value that is easier to measure than T _M is used instead of T _M. FIG. 5 is a diagram for explaining this value, but the number N of occurrences of T _{1 to} T ₂ (the number of shaded portions in the figure) including 3 / 4T which is the identification boundary time of digital information is used. However,
T ₁ is larger than 1 / 2T and T ₂ is smaller than T. Since this number N also changes according to the time margin T _M , it can be used as a value indicating the optimum degree of specialization.

Next, the operation of the embodiment shown in FIG. 1 will be described. The signal recorded on the magnetic recording medium is reproduced by the magnetic head 1 and given to the equalizing circuit 2 and the equalizing circuit 3. These equivalent circuits are cosine equalization circuits, and this frequency gain characteristic is Becomes Here, is the frequency, m is the maximum gain frequency, and K is the equalization amount. This characteristic is shown in FIG.
The gain becomes maximum, and the gain Gm at that time changes depending on the equalization amount K. That is, this K corresponds to the compensation amount of the high frequency component. The equalization amount K can be controlled by an equalization amount control signal given from the outside, and FIG. 7 shows the relationship between the equalization amount control signal level V and the equalization amount K.

As shown in the figure, the characteristics of these equalization circuits are different. The equalization amount of the equalization circuit 3 is larger than that of the equalization circuit 2.
Kd is big. Therefore, two equalized reproduction signals are obtained from the outputs of the equalization circuit 2 and the equalization circuit 3, and are given to the waveform shaping circuit 4 and the waveform shaping circuit 5, respectively.

Waveform shaping is performed in these waveform shaping circuits, and two reproduced digital signals are obtained. Further, these reproduced digital signals are given to the counting circuit 6, the counting circuit 7, and the selection circuit 9.

The counting circuit counts the number of occurrences (the number of shaded portions in FIG. 5) in which the polarity inversion time of the reproduced digital signal is in the range of T _{1 to} T ₂ described above, and the count signal is sent to the control signal generating circuit 8. Is output. The details of this counting circuit will be described later.

The control signal generation circuit 8 generates an equalization amount control signal for controlling the equalization amount of the equalization circuit 2 and the equalization circuit 3 according to these count values and outputs it to these equalization circuits. In the equalization circuit, the equalization amount control signal is controlled to optimize the equalization amount. Further, the control signal generation circuit 8 generates a selection control signal and supplies it to the selection circuit 9. The selection circuit 9 performs selection control by this selection control signal, and selects one of the two reproduced digital signals which has a better equalization and outputs it to the reproduced digital signal output terminal 10.

Next, the detailed configuration and operation of the control signal generation circuit 8 will be described. FIG. 8 is a block diagram of this control signal generating circuit. 11 and 12 are input terminals for inputting the count signals from the counting circuits 6 and 7, 13 is a magnitude comparison circuit for comparing the magnitudes of the count values of these count signals and outputting a comparison signal according to the result, 14 Is a selection control signal output terminal that outputs this comparison signal as a selection control signal, 15 is a displacement amount register that holds the displacement amount, 16 is an addition / subtraction circuit that adds and subtracts the displacement amount and the equalization amount, and 17 is the equalization amount. Equalization amount register to hold, 18 is a DA converter that obtains the equalization amount control signal by converting the equalization amount signal from the equalization amount register to digital-analog, 19 is the equalization amount control that outputs the equalization amount control signal A signal output terminal, 20 is a clock signal generation circuit that generates a clock signal, 21 is a count reset signal output terminal that outputs a count reset signal that resets the count of the counting circuit, and 22 is a count hold signal that holds the count of the counting circuit. Output count Rudo is a signal output terminal.

Next, the operation will be described. The counting signals from the counting circuits 6 and 7 are input to the magnitude comparison circuit via the counting signal input terminals 11 and 12. The magnitude comparison circuit 13 compares the magnitudes of the count values of these count signals, and outputs a comparison signal according to the result. For example, when the count value from the counter circuit 6 is N _{1 and the} count value from the counter circuit 7 is N ₂ , an “H” level signal is provided when N ₂ is greater than N _1, and an “L” level signal is provided when it is equal to or less than N _1.
Output level signal. This comparison signal is given to the selection control signal output terminal 14 and the addition / subtraction circuit 16.

The adder / subtractor circuit 16 adds and subtracts the equalization amount from the equalization amount register 17 and the displacement amount from the displacement amount register 15 to obtain the next equalization amount and supplies it to the equalization amount register 17. On the other hand, the equalization amount register 17 is supplied with a clock signal from the clock generation circuit 20, and the value of the equalization amount register is updated to the equalization amount from the addition / subtraction circuit 16 by this clock signal.

The operation of the adder / subtractor circuit 16 is controlled by the comparison signal from the magnitude comparison circuit 13, and this comparison signal is at the "H" level (N ₂ >
When N ₁ ), the subtraction operation is performed and "L" level (N ₂ ≤ N ₁
In case of), the addition operation is performed. Count value as a result
The equalization amount of the equalization amount register is increased or decreased in units of displacement according to the magnitude of N ₁ and N ₂ . Next, the equalization amount of the equalization amount register 17 is given to the DA converter 18, digital-analog converted, and output to the equalization amount control signal output terminal 19 as an equalization amount control signal.

Next, the operation of shifting to the optimum equalization state will be described. As described above, the count value N is a value indicating the optimum degree of equalization, and becomes the minimum when the equalization is optimum. FIG. 9 is a diagram showing the relationship between the count value N and the equalization amount K. If the equalization amount when the count value N becomes the minimum is Km, it will be small even if the equalization amount K becomes larger than Km. Even so, the count value increases. Therefore, as the initial state, the initial value of the equalization amount K may be larger or smaller than Km.

FIG. 10 is a diagram when the initial equalization amount is larger than the optimum equalization amount Km. In this case, N ₂ > N ₁ , so the addition / subtraction circuit
16 performs a subtraction operation, and the equalization amount decreases and changes to the optimum value Km. FIG. 11 is a diagram when the initial equalization amount is smaller than the optimum equalization amount Km. At this time, N ₂ <N ₁ , so the addition / subtraction circuit 16 performs addition operation, and the equalization amount is Increased optimum value Km
Change to. As described above, the equalization amount is controlled to be the optimum amount Km regardless of the initial equalization amount.

A count reset signal for resetting the count of the counting circuit and a count hold signal for holding the count are also generated from the clock signal generation circuit 20 in FIG. ,
It is output to the count hold signal output terminal 22.

The above is a detailed description of the control signal generation circuit of FIG. 8. Next, the detailed configuration and description of the counting circuits 6 and 7 will be described.
FIG. 12 is a block diagram showing the configuration of this counting circuit.
In the figure, 23 is a reproduction digital signal input terminal for inputting a reproduction digital signal, 24 is a delay circuit, 25 is an inverter, 26 is an AND circuit, 27 and 28 are monostable multivibrators (hereinafter referred to as monomulti), 29 and 30 are AND circuits, 31 is a counter, 32 is a register, 33 is a count signal output terminal that outputs a count signal, 32 is a count reset signal input terminal that inputs a count reset signal, and 35 is a count that inputs a count hold signal. Hold signal input terminal.

The next operation will be described. FIG. 13 is a diagram showing the waveform of each signal in FIG. 12, but the reproduced digital signal as shown in (f) is input to the delay circuit 24, AND circuits 26, 29 via the reproduced digital signal input terminal. It In the delay circuit 24, the time T
_The signal (g) delayed by _D is obtained, and the inverter 25, AND
Given to circuit 29. Further, the inverter 25 obtains the phase-inverted signal (h). Next, in the AND circuit 26, the signal (f) and the signal (h) are ANDed, and the signal (i) is output to the output. Similarly, the AND circuit 29 also obtains the signal (j) at its output. This signal i is a signal having pulses P ₁ , P ₂ ... At the rising edge of the reproduced digital signal (f), and signal (j) is at the trailing edge of pulses Q ₁ , Q ₂
Is a signal having. The signal (i) triggers the monomulti 27, and at its output the signal (k) is obtained. The pulse width of this signal (k) is T _1, which is a constant value determined by the time constant of the monomulti 27. Furthermore, this signal (k) triggers the monomulti 28, and at its output the signal (l) is obtained,
Given to the D circuit 30. The pulse width T ₃ of this signal (k) is also a constant value determined by the time constant of the monomulti 28.

In the AND circuit 30, among the pulse signals Q ₁ , Q ₂ ... Of the signal (j), only the pulse signal (Q _{1 in} this example) in which the signal (l) is in the high level period is gated, and the signal (m ) Is obtained.
The timings of the pulse signals Q ₁ and Q ₂ are determined by the polarity reversal times t ₁ and t ₂ of the reproduced digital signal (f), and as a result, the polarity reversal times T _{1 to} T ₂ (T ₂ = T _{2 1} + T ₃ )
One pulse will be output only when it is in between. Next, this signal (m) is given to the counter 31 and counted. On the other hand, the counter 31 has its count value reset by the count reset signal, and the counter is reset after a certain period of time.
The count value of 31 is set in the register 32 by the count hold signal and held until the next set. Then, the count value of this register 32 is used as a count signal as a count signal output terminal.
Output to 33.

The above is a description of one embodiment of the present invention. In this embodiment, an example of a cosine equalization circuit was described as an equalization circuit, but it is similarly possible if it is a controllable equalization circuit. . In addition, the polarity inversion time is T as a recording digital signal.
, And 1 / 2T (T is a bit period), only two kinds of signals have been described, but the same is possible by counting the portion of the time range including the identification boundary time.

EFFECTS OF THE INVENTION According to the present invention, optimum equalization is automatically performed with respect to variations in transmission characteristics of a recording / reproducing system, and reliability is improved. Moreover, the adjustment of the equalization circuit is not required, and the productivity is improved, and the effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an automatic equalizer of the present invention, FIG. 2 is a waveform diagram for explaining a process of reproducing a recorded digital signal and a reproduced digital signal, and FIGS. FIG. 6 is an explanatory view for explaining a part of the principle of the present invention, FIG. 6 is an explanatory view for explaining the frequency gain characteristic of the equalization circuit in FIG. 1, and FIG. 7 is an equalization amount and equalization of the equalization circuit. FIG. 8 is a block diagram of the control signal generating circuit, FIGS. 9 to 11 are explanatory diagrams for explaining the operation of the control signal generating circuit, and FIG. 12 is a counting circuit. A block diagram and FIG. 13 are waveform diagrams of respective parts of the counting circuit of FIG. 2,3 ... Equalization circuit, 4,5 ... Waveform shaping circuit, 6,7 ... Counting circuit, 8 ... Control signal generation circuit, 9 ... Selection circuit.

Claims (1)

[Claims] 1. An automatic equalizer for automatically optimally equalizing a reproduced signal from a recording medium when recording and reproducing a digital signal, wherein the equalization amount can be controlled by an external control signal. , Two equalizing circuits having different equalization amounts, two waveform shaping circuits for waveform shaping the reproduced signals from these equalizing circuits to obtain a reproduced digital signal, and a polarity inversion time of these reproduced digital signals is predetermined. Two counting circuits that count only the number of the parts within the range for a certain period, and an equalization amount that controls the equalization amounts of the two equalization circuits according to the two count values obtained by these counting circuits. Control signal and control circuit for controlling the selection circuit Control signal generation circuit for issuing a control signal and a control signal controlled by the control signal, select the reproduced digital signals from the two waveform shaping circuits and output the optimum reproduced digital signal You Automatic equalizer being characterized in that includes a selection circuit.