JPH07320406A - Signal reproducing apparatus and signal reproducing method - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a reproducing apparatus capable of digitally detecting a pilot signal superimposed on a digitally modulated signal and realizing a large amount of processing by software processing having a relatively low processing speed. . When detecting the pilot signal component from a digital modulation signal, the modulation signal is converted into an A / D converter 10
Detection means (203, 205, 208, for detecting the level of the pilot signal component from the output A / D converted in 9
209, 204, 214, 219, 225), and the pilot signal superimposed on the digital modulation signal can be accurately detected only by the digital signal processing circuit, and the operating frequency after the sampling means is the same as that of the reproducing means. Since the processing is performed in synchronization, the processing can be performed by software, and the load on the software can be extremely reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reproducing device and a signal reproducing method, and more particularly to reproducing a digital modulated signal containing a pilot signal component of a predetermined frequency from a recording medium and detecting a pilot signal component in the reproduced signal. The present invention relates to a device and a reproducing method.

[0002]

2. Description of the Related Art In recent years, a digital VTR has been actively developed due to the progress of digital magnetic recording / reproducing technology.
Even in this kind of digital VTR, the conventional analog VT
Similar to R, it is necessary to perform tracking control at the time of reproduction, and various tracking control methods have been proposed.

Among them, a method of superposing a predetermined pilot signal component at the time of digitally modulating a digital signal data sequence to be recorded and performing tracking control using this pilot signal at the time of reproduction is drawing attention.

FIG. 7 shows a digital VT using this kind of method.
It is a figure which shows schematic structure of the recording system of R. In the figure, ch1,
Each of ch2 is attached to a rotating drum with a phase difference of 180 °, and a rotary head for recording a digital modulation signal on a magnetic tape T which is a recording medium, and T is a magnetic tape.

The operation will be described below.

The video signal input from the terminal 1 is supplied to a digital recording signal processing circuit 2, which performs high-efficiency coding and error correction coding of the video signal, along with audio data and other auxiliary data. A digital data string is formed according to the recording data format.

This digital data string is further supplied to the digital modulation / pilot addition circuit 3. The circuit 3 is
Digital modulation such as 24-25 conversion to give data redundancy is applied to the data string from the processing circuit 2, and a pilot signal component is added by utilizing this redundancy.

Specifically, for example, for each 24-bit data, the leading bits of "1" and "0" are added to the beginning and the other 2
5-bit data is formed, and these are output as bit streams. Then, each of these bit streams is NRZI modulated. Furthermore, from the two types of NRZI-modulated bit streams, the DC component, f1
The (first pilot signal frequency) component and the f2 (second pilot signal frequency) component are extracted, and the sum of these components is calculated. This sum is added to the cumulative value of the past sums, and for each bitstream,
Form an accumulated value. Then, these two types of accumulated values are compared with each other, and the 25-bit bit stream having the smaller accumulated value is selected and output. The bit stream output in this case is a bit stream in which the DC, f1, and f2 components are suppressed.

Here, by superimposing (for example, subtracting) a predetermined pattern signal on the extracted DC component, the bit stream has a frequency component for the pattern signal. Therefore, by setting the frequencies of the predetermined pattern signal to the desired frequencies f1 and f2, the pilot signal component of the desired frequency is superimposed on the modulated digital bit stream.

For example, the bit rate of the bit stream is fb, and the frequency f1 of the first pilot signal is fb.
/ 90, the frequency f2 of the second pilot signal is fb / 1
If it is defined as 20, two types of D signals in which a pattern signal that repeats in a 90-bit cycle or a 120-bit cycle is detected
It can be realized by subtracting from the C component.

The digital modulation bit stream thus obtained is supplied to the switching circuit 4 as a digitally modulated recording signal, and the head switching pulse (HSW) formed in accordance with the rotation phase of each rotary head ch1 and ch2 is alternately used for the head ch1. , Ch2. The heads ch1 and ch2 rotate with a phase difference of 180 °, alternately trace on the magnetic tape T, and sequentially form a number of parallel helical tracks to record the digitally modulated recording signal.

FIG. 2 shows an example of a recording pattern on the magnetic tape T. As shown in the figure, pilot signals are superimposed on every other track formed on a large number of helical tracks,
The pilot signal having the frequency f1 and the pilot signal having the frequency f2 are alternately superposed in a 4-track cycle.
In such a recording pattern, for example, a pattern signal having frequency components of f1 and f2 is alternately subtracted from the DC component during the recording period of the head ch1, and the pattern signal is subtracted during the recording period of the head ch2. It can be realized by not performing it.

FIG. 9 is a block diagram showing a structural example of a conventional reproducing system for reproducing the magnetic tape T recorded in the recording format as shown in FIG.

The modulated signals alternately reproduced by the heads ch1 and ch2 are input to the head switching circuit 9 via the reproduction amplifiers 7 and 8. In the circuit 9, the reproduction signal switched by the HSW from the drum rotation detection circuit 15 to be a continuous signal is input to the digital signal reproduction processing circuit 10, the f1 detection circuit 12, and the f2 detection circuit 13, respectively. In the digital signal reproduction processing circuit 10, digital demodulation processing, error correction processing, high-efficiency encoding decoding processing, and the like are performed, and the reproduced information data (video data) is output to the output terminal 11.

The f1 detection circuit 12 and the f2 detection circuit 13 are respectively configured by analog band pass filters, and the pilot signal components extracted by these circuits 12 and 13 are supplied to the tracking control circuit 16, respectively. The tracking control circuit 16 detects the level of the detection circuits 12 and 13 and then takes the difference between the detection outputs. Here, if the tracking control is performed on the head ch2 so as to reproduce the self-recording track, the track on which the pilot signal is not superposed is traced, but at this time, the f1 component and the f2 component are respectively from the adjacent tracks. can get. Here, if the difference between these pilot signal components is calculated, a signal indicating a tracking error for the head ch2 can be obtained. Since the tracking error signal is not obtained while the head ch1 is tracing, the tracking control circuit 16 samples and holds the immediately preceding tracking error signal during this period. In addition, since the polarity of the tracking error signal is inverted every two track periods,
The above-mentioned difference value will be appropriately inverted in synchronization with HSW.

The tracking control signal thus obtained is supplied to the capstan control circuit 17 to control the transport of the magnetic tape T so that each head traces a desired track.

[0017]

However, in the conventional apparatus of this type, each pilot signal is detected by the analog band pass filter, and most of them are externally attached to the digital VTR which is mostly composed of a digital processing circuit. An analog circuit had to be prepared, which required a large component space. Further, a harmonic component is generated by the detection circuit in the subsequent stage of the bandpass filter, and a lowpass filter or the like must be prepared to remove it, which makes it difficult to arrange the circuit efficiently.

Therefore, it is an object of the present invention to detect a pilot signal superimposed on a digital modulation signal as described above with a digital circuit, and moreover, a reproducing apparatus and method suitable for converting many parts of the circuit into software. Is in the place of providing.

[0019]

In one embodiment, a signal reproducing apparatus of the present invention comprises reproducing means for reproducing a digital modulated signal containing a pilot signal component of a predetermined frequency from a recording medium, and the modulated signal. A to A / D conversion
/ D conversion means, detection means for detecting the level of the pilot signal component from the output of the A / D conversion means, and sampling for sampling the output of the detection means with a clock having a frequency corresponding to the operating frequency of the reproduction means. It is configured to include means.

With the above configuration, the pilot signal component contained in the digital modulation signal can be detected without using an analog circuit. Further, since the sampling is performed by the clock having the frequency according to the operating frequency of the reproducing means, the control cycle of the other reproducing operation and the detecting cycle are synchronized with each other, which facilitates the soft aerization of this portion and the relatively low speed. It became possible to process by the processor of.

[0021]

Various embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings.

FIG. 1 is a diagram showing a schematic structure of a reproducing system of a digital VTR as one embodiment of the present invention. In this embodiment, the recording apparatus shown in FIG. The video signal shall be reproduced from the tape T.

In the figure, the same elements as those in FIG. 9 are designated by the same reference numerals. The output (digital modulation signal) from the head switching circuit 9 is supplied to the integration equalizer 107. Here, since the recording signal is convoluted with the transfer function of electromagnetic conversion to change the phase and amplitude characteristics, the integral equalizer 107 performs integral equalization in order to make the phase and frequency characteristics a cosine roll-off characteristic. . The output of the integration equalizer 107 is supplied to an AGC (automatic gain control) circuit 108,
Here, the amplitude of the reproduction signal is adjusted to a constant amplitude value.

The reproduced modulated signal output from the AGC circuit 108 is input to the A / D (analog / digital) converter 109, and is sampled / quantized by a clock formed by a PLL circuit 111 described later. This A / D converter 10
The output of 9 is quantized into m bits (m is an integer of 2 or more), but considering the Viterbi decoding circuit 110 in the subsequent stage, about 6 bits will be necessary. The m-bit digital data is supplied to the PLL circuit 111, and the PLL circuit 111 uses the m-bit digital data to generate a clock signal synchronized with the reproduction modulation signal. Here, if the bit rate of the bit stream is fb as described above, the frequency of this clock is also fb.

The m-bit modulated signal which has been discretely quantized by the A / D converter 109 is decoded by the Viterbi decoding circuit 110 and becomes a bit stream. This bit stream is supplied to a digital reproduction signal processing circuit 114, digitally demodulated by the circuit 114 to be data of 24 bits per word, and further subjected to error correction processing and high efficiency decoding processing, etc. to obtain the original information. The data (video data) is restored. The restored information data is output from the terminal 115.

On the other hand, m output from the A / D conversion circuit 109
The bit modulation signal is input to each of the f1 detection circuit 112 and the f2 detection circuit 113 in the ATF detection circuit 130.
These detection circuits 112 and 113 digitally extract and detect the f1 and f2 components from the quantized reproduced modulation signals, respectively, as described later, and input them to the subsequent microprocessing unit (MPU) 140 as data.

Here, the MPU 140 performs the function corresponding to the tracking control circuit and the capstan control circuit as shown by the dotted line in FIG. 1, and controls the rotation of the capstan motor. The speed of the rotation of the capstan motor 120 is detected by the capstan FG circuit 123,
FG with a frequency corresponding to the rotation speed of the capstan from 3
A pulse is output. Further, the rotation speed of the drum motor 123 that rotates the drum on which the rotary heads ch1 and ch2 are mounted is also detected by the drum PG circuit 15, and from the circuit 14, when the drum reaches a specific phase, for example, two rotations per rotation. PG pulses are output one by one. These FG circuits 121,
The FG pulse and PG pulse output from the PG circuit 15 are input to the MPU 140, respectively. Further, as described later, the PG pulse is also input to the ATF detection circuit 130, and f1
The output timing of the values of the component and f2 component is determined.

FIG. 2 is a flow chart for explaining the operation of the MPU 140, and the tracking control operation of this embodiment will be described below using this flow chart.

The tracking control is performed by the f1 component and f2 reproduced when the head ch2 is in the reproducing state as described above.
Achieved by comparing the components to the MPU14
At 0, for example, an ATF timing is provided every time the heads ch1 and ch2 make one rotation, and a tracking error signal is formed. That is, in step S1 in FIG.
The PU 140 sets the ATF timing after a predetermined period from the input of the PG pulse, detects whether it is the ATF timing, and if it is the ATF timing, the step S2.
In step S3, the f1 detection value and the f2 detection value are fetched.

In step S4, it is determined whether the internal variable X is 0 or not. Here, X is a variable that repeats "1" and "0" each time the ATF timing arrives.
h1 is a variable for reversing the polarity of the tracking error signal by reversing the generation direction of the pilot signals f1 and f2 for each rotation of the drum with respect to the tracking target track which is mainly traced. When X is "0", the tracking error data TE is obtained in step S5.
Is calculated from f1 (f1 detection value) -f2 (f2 detection value),
When X is "1", the tracking error data TE is obtained from f2 (f2 detection value) -f1 (f1 detection value) in step S7. After that, in steps S6 and S8, the variable X
Is switched to prepare for the next detection, the capstan control data (CC) is updated in step 12, and the process returns to step S1.

In step S9, the arrival of the capstan FG pulse is detected, and when the FG pulse arrives, the process proceeds to step S10,
The period (interval) from the immediately preceding FG pulse is measured. Next, in step S11, the capstan speed control data (SE) is updated so that this interval becomes a predetermined period, and the process proceeds to step S12 to update CC. Actually, it is considered that the integration processing corresponding to the low-pass filter in the analog circuit is performed at the time of updating SE or TE, but this explanation is omitted in this flowchart. In step S12, the updated SE or TE is used to add a predetermined coefficient k ₁ . Capstan control data CC is obtained by multiplying k ₂ and further adding them, and this data CC is read as a control signal of the capstan motor 120.

Next, the f1 detection circuit 112 in FIG.
A specific configuration example of the f2 detection circuit 113 will be described. FIG. 3 is a diagram showing a configuration example of a digital detection circuit that can be used as these circuits 112 and 113.

In FIG. 3, the reproduction modulation signal quantized to m bits described above is input to the input terminal 201, and the digital band pass filter (BPF) 202 causes the band of f1 to be changed as shown in FIG. 5 (A). Only the components are extracted.
In this way, the signals from which unnecessary noise and the spectrum of the digitally modulated bit stream data have been removed are input to the latch circuits 203 and 208, which are decimating means, respectively. Here, decimating is to reduce the sampling rate in the signal processing system,
This is a process of thinning out a signal from a digital signal sequence at a desired cycle. That is, it corresponds to sub-sampling the digital data.

The clock of frequency fb from the PLL circuit 111 is input from the clock generation circuit 210, and this clock is divided by the (2 / N) frequency divider circuit 211 to obtain a frequency twice the frequency f1 (2fb / N) clock is obtained. This clock is further divided by 1/2
The frequency is divided by 15 to form a clock whose frequency is f1 (fb / N). Here, the circuit of FIG. 1 is used for detecting the f1 component, and the latch frequency at the time of digitizing is set to f1. Here, as described above, f1 = fb
If it is / 90, the frequency division ratio of the frequency divider 211 is 1/45.

On the other hand, similarly, the clock of the frequency fb from the clock generation circuit 210 is delayed by the delay device 212 to f1 (f
(1/9) so that the frequency of the frequency-divided output becomes f1 by the (1 / N) frequency divider 213 (1/9).
0) Divide. As a result, the operating phases of the latch circuits 203 and 208 differ by 1/4 cycle of f1.

In this example, re-sampling (sub-sampling) is performed so that the Nyquist frequency becomes f1 / 2 as described above.
It will be done. Here, considering re-sampling of the pilot signal f1 at the frequency f1, for example, when the sampling timing has a phase difference of ¼ cycle of f1 with respect to the peak value of the pilot signal, re-sampling is performed. The output, that is, the decimated output, may be completely zero. Therefore, in the present embodiment, the input pilot signal is decimated by a phase having a quadrature relationship (a phase shifted by 90 °), so that FIG.
As shown in (1), the detected spectrums are folded back in cycles of DC and an integral multiple of f1, respectively.

As described above, the amplitudes of the specific frequency components of the input signal can be obtained by decimating the latch circuits 203 and 208 with the clocks in the orthogonal relationship. Here, in the decimated state only, the positive and negative signs are still added depending on the input pilot signal and the timing of the latch, so the magnitude of the vector cannot be obtained.

Therefore, in this embodiment, the latch circuit 203
The output of the latch circuit 208 is switched by the switch 209 in synchronization with the clock from the frequency divider 211 and is input to the square detection circuit 204. This square detection circuit 204
Or the output component of the clutch circuit is switched by the switch 214 in synchronization with the clock from the frequency divider 211 and output. The output of this switching is latched by the latch circuits 216 and 217 at the above-mentioned ATF timing by the clock fpg according to the above-mentioned PG pulse inputted from the terminal 218.

The outputs of the latch circuits 216 and 217 are
It is input to the adder 225. In this way, the result of adding the squares of the components latched by the latch circuits 203 and 208 is obtained from the adder 225 at the ATF timing, and this addition output is input to the squarer 206. The squarer 206 takes the square root of the output of the adder 205 to obtain the magnitude of the vector of the f1 signal component. The output of the squarer 206 is input to the MPU 140 via the terminal 207 as f1 value data.

As described above, in consideration of operating the circuits subsequent to the decimating circuit by using the clock divided for decimating, and further taking in data to the MPU 140, the latch circuits 216 and 217 and subsequent circuits are controlled by the MPU 140. It is operated with the clock fpg synchronized with the ATF timing. FIG. 4C is a diagram showing the frequency characteristic of the detection result output from the square circuit 206.

By configuring as described above, the squaring circuit having a relatively large circuit scale can be shared by the components latched (decimated) in two phases, and the circuit scale can be kept relatively small. You can Further, the operation timing of the latch circuits 216 and 217 and thereafter is determined in consideration of the operation of the MPU 140. Therefore, in the present embodiment, the latch circuit and the subsequent parts are configured by hardware, but it can be easily incorporated into the software processing in the MPU 14 described in the flowchart of FIG.

The above description has explained the configuration when the circuit of FIG. 3 is used for detecting the pilot signal f1, but when it is used for detecting the pilot signal f2, the division ratio is changed and the clock of the frequency f2 is changed. Figure 3 if formed
It goes without saying that the above circuit can be used for f2 detection as well.

FIG. 5 shows the f1 detection circuit 112 and f2 of FIG.
It is a figure which shows the other Example of this invention applicable to the detection circuit 113. 5, the same components as those in FIG. 3 are designated by the same reference numerals. In FIG. 5, reference numerals 238 and 239 denote latch circuits that latch the two outputs from the switch 214 with the output clocks of the frequency dividers 215 and 213, respectively. The outputs of these latch circuits 238 and 239 are added by the adder circuit 205. . The output of the adder circuit 205 is further latched by the latch circuit 226 at the above-mentioned clock fpg. In this way, the detection output synchronized with the above-mentioned ATF timing is processed by the MPU 140 according to the flowchart of FIG.

As described above, also in the circuit of FIG. 5, as in the circuit of FIG. 3, pilot signals such as f1 and f2 can be digitally detected, and the detection output thereof coincides with the operation timing of the MPU 140. The processing of can be realized by software.

FIG. 6 shows the f1 detection circuit 112 and f2 of FIG.
It is a figure which shows the other Example of this invention applicable to the detection circuit 113. 6, the same components as those in FIG. 3 are denoted by the same reference numerals. In FIG. 6, reference numeral 219 denotes an absolute value detection circuit, and the output of the switch 209 described above is supplied to the absolute value detection circuit 219. Here, the absolute-valued components are extracted by the switch 214 and input to the adder 205 via the latch circuits 238 and 239 to obtain the DC component. This DC component is further latched by the latch circuit 226.
Is latched by the clock fpg and matched with the ATF timing. However, the added DC component is supplied to the terminal 207 via the digital low-pass filter 236 in order to remove other noise components. Here, the digital low-pass filter itself has a better S / N
The cost can be reduced by omitting it unless it is necessary to obtain the C component.

As described above, in the embodiment of the present invention,
All can be configured by digital circuits, especially a pilot signal detection device and tracking control device that can perform most of the processing by the MPU can be configured, and since no analog circuit is used, the device can be practically downsized. , The compatibility with other digital devices has also been improved. Also, 2
Since the detection circuit is shared for the decimated outputs in three different phases, low power consumption is possible.

Further, a part of this detection circuit, that is, the latch circuits 216, 217, 226 and thereafter can be constructed in the MPU by software as it is. In this case, the operation cycle of the software follows the clock fpg. Since the cycle becomes extremely slow, the capacity of the ROM can be significantly reduced.

In the above embodiment, the frequency division ratio for decimating, the number of quantization bits of the digital modulation signal, the clock generation method, etc. can be changed as appropriate.

[0049]

As described above, according to the present invention, in detecting the pilot signal component of the predetermined frequency from the digital modulation signal, the pilot signal is output from the A / D conversion means for A / D converting the modulation signal. Since the sampling means for detecting the level of the signal component and sampling the detected output with a clock having a frequency corresponding to the operating frequency of the reproducing means is provided, the pilot signal superimposed on the digital modulated signal can be accurately processed by the digital signal processing circuit. It can be detected only. Further, since the operating frequency after the sampling means is synchronized with the operation of the reproducing means, it can be processed by software, and the load on the software can be made extremely small.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a reproducing system of a digital VTR as an embodiment of the present invention.

FIG. 2 is a flow chart for explaining the operation of the MPU in FIG.

FIG. 3 is a diagram showing a configuration example of a pilot signal detection circuit of FIG. 1.

FIG. 4 is a diagram for explaining a frequency band handled in each part of FIG.

5 is a diagram showing another configuration example of the pilot signal detection circuit of FIG. 1. FIG.

FIG. 6 is a diagram showing still another configuration example of the pilot signal detection circuit of FIG. 1.

FIG. 7 is a diagram showing a schematic configuration of a recording system of a known digital VTR.

8 is a diagram showing a magnetic tape-shaped recording pattern by the DVTR of FIG. 7. FIG.

9 is a D diagram for reproducing the recording pattern of FIG. 7;
It is a block diagram showing an example of composition of a reproducing system of a VTR.

[Explanation of symbols]

 ch1, ch2 rotary head 10, 114 digital reproduction signal processing circuit 12 f1 detection circuit 13 f2 detection circuit 16 tracking control circuit 107 integration equivalent circuit 108 AGC circuit 109 A / D converter 110 Viterbi decoder 111 PLL circuit 112 f1 detection circuit 113 f2 detection circuit 130 ATF detection circuit 140 MPU (microprocessing unit) 201 digital bandpass filter 203, 208, 216, 217, 226 latch circuit 204 square circuit 205, 225 addition circuit 206 square circuit 210 clock generation circuit 211, 213, 215 Frequency divider 212 Delay circuit 219 Absolute value detection circuit 236 Digital low-pass filter

Claims (7)

[Claims] 1. A reproducing means for reproducing a digital modulated signal containing a pilot signal component of a predetermined frequency from a recording medium, an A / D converting means for A / D converting the modulated signal, and an output of the A / D converting means. And a sampling means for sampling the output of the detecting means with a clock having a frequency corresponding to the operating frequency of the reproducing means. 2. The signal reproducing apparatus according to claim 1, further comprising means for restoring the main information signal superimposed on the modulated signal by using the output of the A / D converting means. 3. The signal reproducing apparatus according to claim 2, wherein the A / D conversion unit A / D converts the modulated signal into a plurality of bits and inputs the A / D converted signal into a Viterbi decoder in the restoration unit. 4. The signal reproducing apparatus according to claim 1, further comprising control means for controlling the relative position of the reproducing means and the recording medium by using the output of the sampling means. 5. The signal reproducing apparatus according to claim 1, wherein the reproducing means includes a rotary head, and the clock has a frequency relating to a rotation cycle of the rotary head. 6. The detecting means includes decimating means for sub-sampling the output of the A / D converting means, and the frequency of the clock is lower than the sub-sampling frequency by the decimating means.
The signal reproducing device according to any one of 1. 7. A digital modulated signal containing a pilot signal component of a predetermined frequency is reproduced from a recording medium, the reproduced modulated signal is A / D converted, and the level of the pilot signal component is converted from the A / D converted output. A signal reproducing method characterized by detecting and sampling the detected level with a clock having a frequency according to a reproducing operation cycle.