JPH07336400A - Digital signal transmission system and transmitter and receiver used therefor - Google Patents

Abstract

(57) [Abstract] [Purpose] When a signal such as a video signal is digitally transmitted, the quality of the received signal is prevented from being suddenly deteriorated even if the reception condition is deteriorated, and the circuit configuration of the transmitter and the receiver is simplified. . [Structure] The transmitting side performs coding with different error correction capabilities according to the priority of the input signal, multiplexes these signals, performs digital modulation to generate a transmitting signal, and digitally demodulates at the receiving side. Even if the reception condition is deteriorated by separating and decoding the received signal later, the sudden deterioration of the quality of the received signal is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission system for transmitting digital signals such as digital video signals and the like. Even if the C / N ratio (carrier power to noise power ratio) is deteriorated, the reception quality or reception is improved. The present invention relates to a digital transmission system in which image quality is less likely to deteriorate sharply, and a transmission device and a reception device used therein.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional error correction code circuit and error shown in "Theoretical bit error rate characteristic of soft decision Viterbi decoding" (Technical Report of the Institute of Electronics and Communication Engineers, CS 80-126, 1980), for example. FIG. 3 is a block diagram showing a digital transmission system using a correction decoding circuit, in which 901 is an error correction coding circuit, 905 is a digital modulation circuit, 906 is a digital demodulation circuit, and 902 is an error correction decoding circuit.

Next, the operation will be described. FIG. 9 shows a transmission system that includes an error correction code circuit before modulating a digital signal, and demodulates and decodes the signal on the receiving side to make it resistant to errors due to noise received on a transmission line or the like. However, the error correction code circuit 901 uses an error correction code having one kind of error correction capability for all input data, and 902 uses 90
It is an error correction decoding circuit having one type of error correction decoding capability according to 1.

In the above document, a convolutional encoder is used as the error correction coding circuit and a Viterbi decoder is used as the error correction decoding circuit.

[0005]

Since the conventional digital transmission system is constructed as described above, when the received C / N is deteriorated and exceeds a certain threshold value, for example, when a video signal or the like is digitally transmitted. There is a problem peculiar to the digital transmission system that the image quality deteriorates sharply. This situation is shown in Figure 1.
It shows in 0.

The present invention has been made to solve the above problems, and a digital signal transmission system in which a received image is not rapidly deteriorated even when a reception C / N is deteriorated, a transmitter used therefor, and An object is to provide a receiving device.

[0007]

A digital signal transmission system according to claim 1 of the present invention is a transmission system for transmitting a plurality of input signal sequences having different priorities, wherein the transmission side assigns priority to the signal sequences. Accordingly, error correction codes having different error correction capacities are applied to all or part of the signal sequence, multiplexed by a time division multiplexing circuit (hereinafter referred to as "multiplexer"), and then a transmission signal is generated by a digital modulation circuit, On the reception side, the digital demodulation circuit demodulates the received signal by the transmission signal, separates it by a demultiplexer, and then performs error correction decoding on all or part of the separated signal sequence.

According to a second aspect of the present invention, a digital signal transmitting apparatus is provided with an error correction code circuit for correcting error correction codes having different correction capabilities for all or some of them according to the priority of a plurality of input signal sequences. The digital modulation circuit generates a transmission signal after multiplexing with a multiplexer.

Further, a digital signal transmitting apparatus according to a third aspect of the present invention comprises an interleave circuit after the multiplexer.

According to a fourth aspect of the present invention, the digital signal receiving apparatus demodulates the received signal by the digital demodulation circuit and separates the demodulated signal by the demultiplexer,
The error correction decoding circuit performs error correction decoding on all or part of the separated signal sequence.

Further, a digital signal receiving apparatus according to a fifth aspect of the present invention comprises a deinterleave circuit before the demultiplexer.

[0012]

In the digital signal transmission system according to the first aspect of the present invention, after the transmission side performs error correction code having different error correction capabilities on all or part of the input signals according to the priority of the plurality of input signals. , Multiplex and perform digital modulation to generate a transmission signal, the reception side digitally demodulates the reception signal by the transmission signal, separates the reception signal, and then performs error correction decoding on all or part of the signal sequence. Therefore, the error resilience ability varies depending on the priority of the signal, and the received signal does not suddenly deteriorate even if the received C / N decreases on the receiving side.

Further, in the digital signal transmitting apparatus according to the second aspect of the present invention, the error correction code circuit uses an error correction code circuit in which all or part of the error correction capability is different depending on the priority of the plurality of input signals. After the signal is applied, the signal is multiplexed by the multiplexer and digitally modulated by the digital modulation circuit to generate the transmission signal. Therefore, the higher the priority of the input signal is, the higher the correction capability of the signal, which is the signal to which the error correction code is applied, is generated.

Furthermore, in the digital signal transmitting apparatus according to the third aspect of the present invention, since the interleave circuit is provided after the multiplexer, the circuit configuration of the transmitting apparatus can be simplified.

Further, in the digital signal receiving apparatus according to the fourth aspect of the present invention, the received signal is demodulated by the digital demodulation circuit, the demodulated signal is separated by the demultiplexer, and the whole or a part of the separated signal sequence. On the other hand, since error correction decoding is performed by the error correction decoding circuit, the error resilience ability varies depending on the priority of the signal, and the received signal does not deteriorate rapidly even if the received C / N decreases.

Further, in the digital signal receiving apparatus according to the fifth aspect of the present invention, since the deinterleave circuit is provided before the demultiplexer, the circuit configuration of the receiving apparatus can be simplified.

[0017]

【Example】

Example 1. 1 is a block diagram showing a digital signal transmission system according to a first embodiment of the present invention. In the figure, the input signal 1, the input signal 2 and the input signal 3 have higher priority in this order, and 101 is a Reed-Solomon (hereinafter referred to as RS) (255, 23) as an error correction code circuit for the input signal 1.
9) Code circuit, similarly 102 is RS (255, 243)
A code circuit, 103 is an RS (255, 247) code circuit,
104 is a multiplexer, 105 is a QPSK modulation circuit,
106 is a QPSK demodulation circuit, 107 is a demultiplexer, 108 is an RS (255, 239) decoding circuit as an error correction decoding circuit for the output signal 1, and 109 is R
S (255,243) decoding circuit, 110 is RS (25
5, 247) Decoding circuit, which outputs output signal 1, output signal 2, and output signal 3 corresponding to input signal 1, input signal 2, and input signal 3.

Next, the operation will be described. Input signal 1,
The input signal 2 and the input signal 3 have different priorities, and are digital data corresponding to, for example, a low frequency component signal, a middle frequency component signal, and a high frequency component signal of a digital video signal. These input signals are in the order of priority,
RS (255, 239) coding circuit 101, RS
(255, 243) code circuit 102, RS (255, 2)
47) The error correction coding is performed by the coding circuit 103. R
The S (255, 239) coding circuit 101 blocks the input bit string for each 239 symbols, adds 16-symbol check bits thereto, and outputs a total of 255 symbols. However, one symbol is 1 byte, that is, 8 bits.
This code has an error correction capability capable of correcting 8 out of 255 symbols. Similarly, the RS (255, 243) coding circuit 102 blocks the input bit string for every 243 symbols, adds check symbols of 12 symbols to this, and outputs a total of 255 symbols. This code has an error correction capability capable of correcting 6 out of 255 symbols. R
The S (255,247) coding circuit 103 blocks the input bit string for every 247 symbols, adds check symbols of 8 symbols to this, and outputs a total of 255 symbols. This code has an error correction capability of correcting 4 out of 255 symbols. Since the higher the priority of the input signal is, the higher the error correction capability is, the higher the RS coding is,
An input signal with a higher priority has a higher error resilience capability. Next, the multiplexer 104 time-division-multiplexes the error-correction-encoded input signal as described above. That is, the multiplexer 104
The outputs of the above three encoders are input in parallel to, and these signals are rearranged using a memory or the like and output in series. Therefore, the output of the multiplexer is a continuous series of digital data. Then, the multiplexed signal is a four-phase phase modulation (hereinafter referred to as QPSK modulation) circuit 105.
Is modulated by and is output to the transmission path as a transmission wave. Here, the transmission line is, for example, a satellite line or the like, and in general, disturbance such as noise is added to the transmitted wave.

As described above, the transmission wave encoded and modulated on the transmission side is affected by noise on the transmission line, and the QPS on the reception side.
It is demodulated by the K digital demodulation circuit 106. The operation on the receiving side is the reverse of the operation on the transmitting side. That is, the demodulated one series of digital data is demultiplexed by the demultiplexer 107.
Divided by. The divided signals are RS
(255, 239) Decoding circuit 108, RS (255, 2)
43) The error correction decoding is performed by the decoding circuit 109 and the RS (255, 247) decoding circuit 110, and the output signal 1, the output signal 2, and the output signal 3 corresponding to the input signal 1, the input signal 2, and the input signal 3 are output. To be done. For example, it is a low frequency component signal, a middle frequency component signal, and a high frequency component signal of the video signal. For the reason described above, an output signal having a higher priority is more resistant to an error due to noise, so that even if the reception C / N is deteriorated, the output signal 1, the output signal 2, and the output signal 3 are not deteriorated at the same time. The output signal of low frequency gradually deteriorates. For example, when a video signal is received, the received image does not suddenly deteriorate, but begins to deteriorate from a high-frequency component signal of low priority, and gradually deteriorates in the order of a middle-frequency component signal and a high-frequency component signal. This state is shown in FIG. For example, when receiving a video signal, all output signals do not suddenly deteriorate,
Degradation starts from the high-frequency component signal having a low priority, and the intermediate-frequency component signal and the high-frequency component signal gradually deteriorate in stages. Then, by determining the error rate of each output signal, etc., the output signals that cannot be reproduced are sequentially discarded, and the reproducible output signals are displayed, so that abrupt deterioration of the received image can be prevented.

Example 2. FIG. 3 is a block diagram showing a transmitting device according to the second embodiment of the present invention. In the figure, the input signal 1, the input signal 2, and the input signal 3 have higher priority in this order,
Reference numeral 301 denotes a convolutional code circuit having a constraint length of 7 and a coding rate of 1/2 as an error correction code circuit for the input signal 1, and similarly 3
02 is a convolutional code circuit with constraint length 7 and coding rate 3/4,
Reference numeral 303 denotes a convolutional code circuit having a constraint length of 7 and a coding rate of 7/8 (however, the convolutional code of the coding rates of 3/4 and 7/8 is a punctured code having a coding rate of 1/2), and 304 denotes these. A multiplexer for time-division multiplexing three types of signals, 30
Reference numeral 5 is a QPSK modulation circuit for digital modulation.

Next, the operation will be described. Input signal 1,
The input signal 2 and the input signal 3 have different priorities, and are digital data corresponding to, for example, a low frequency component signal, a middle frequency component signal, and a high frequency signal of a digital video signal. These input signals are subjected to error correction codes by a convolutional coding circuit 301 with a coding rate of 1/2, a convolutional coding circuit 302 with a coding rate of 3/4, and a convolutional coding circuit 303 with a coding rate of 7/8, respectively, in order of priority. Be converted.
A convolutional code with a coding rate of 1/2 outputs 2 bits of output data that is error correction coded for 1 bit of input data. Similarly, a convolutional code with a coding rate of 3/4 outputs 4 bits for an input of 3 bits, and a convolutional code with a coding rate of 7/8 outputs 8 bits for an input of 7 bits. The smaller the coding rate, the larger the redundancy for error correction, and the higher the error correction capability. In this way, convolutional coding with higher error correction capability is performed for input signals with higher priorities, so that input signals with higher priorities have higher error resilience capabilities. Next, the multiplexer 304 time-division-multiplexes the error-correction-coded input signal as described above. That is, the outputs of the above three encoders are input in parallel to the multiplexer 304, and these signals are rearranged using a memory or the like and output in series. Therefore, the output of the multiplexer 304 is a continuous series of digital data. Then, the multiplexed signal is modulated by the QPSK modulation circuit 305 and output as a transmission wave to the transmission line. Here, the transmission line is, for example, a satellite line or the like, and in general, disturbance such as noise is added to the transmitted wave.

Example 3. FIG. 4 is a block diagram showing a receiving device according to the third embodiment of the present invention. In the figure, 40
Reference numeral 6 is a QPSK demodulation circuit for digitally demodulating a received signal, 407 is a demultiplexer for separating multiplexed signals, and 408, 409 and 410 are error correction codes applied on the transmission side. Viterbi decoding circuit for decoding convolutional code of rate 1/2, coding rate 3/4
Viterbi decoding circuit for decoding the convolutional code of
A Viterbi decoding circuit for decoding a / 8 convolutional code.

Next, the operation will be described. A signal affected by noise or the like on the transmission path or the like is demodulated by the QPSK demodulation circuit 406. The demodulated one-series digital signal is separated by the demultiplexer 407. The separated signals are respectively Viterbi decoding circuits 408, 409, 41.
The error correction decoding is performed by 0, and the output signal 1, the output signal 2, and the output signal 3 respectively corresponding to the input signal 1, the input signal 2, and the input signal 3 on the transmission side are output, and the priority is high in this order. For example, a low frequency signal, a middle frequency signal, and a high frequency signal of the video signal. Since the signal with higher priority is subjected to error correction decoding with higher correction capability, the output signal with higher priority is less susceptible to noise. Therefore, even if the reception C / N is deteriorated, the output signal 1, the output signal 2, and the output signal 3 are not deteriorated at the same time, and the output signals with lower priority are gradually deteriorated. FIG. 5 shows the relationship between the received C / N and the bit error rate for each output signal. For example, when receiving a video signal, all output signals do not suddenly deteriorate, but start to deteriorate from the high-frequency component signal of low priority, and gradually deteriorate to the middle-frequency component signal and high-frequency component signal in stages. To do. Then, by determining the error rate of each output signal, etc., the output signals that cannot be reproduced are sequentially discarded, and the reproducible output signals are displayed, so that abrupt deterioration of the received image can be prevented.

Example 4. FIG. 6 is a block diagram showing a transmitting device according to the sixth embodiment of the present invention. In the figure, the input signal 1, the input signal 2, and the input signal 3 have higher priority in this order,
Reference numeral 601 denotes R as an error correction code circuit for the input signal 1.
S (255,239) code circuit, 602 is RS
(255, 243) code circuit, 603 is RS (255,
247) a coding circuit, 604 is a multiplexer for time division multiplexing these three types of input signals, 606 is an interleave circuit for interleaving the multiplexed signals, and 605 is a QPSK modulation circuit for digital modulation.

Next, the operation will be described. Input signal 1,
The input signal 2 and the input signal 3 have different priorities, and are digital data corresponding to, for example, a low frequency signal, a middle frequency signal, and a high frequency signal of a digital video signal. These input signals are RS
(255, 239) code circuit 601, RS (255, 2)
43) Error correction coding is performed by the coding circuit 602 and the RS (255, 247) coding circuit 603. RS (255,
239) The coding circuit 601 blocks the input bit string for each 239 symbols, adds check symbols of 16 symbols to this, and outputs a total of 255 symbols. However, 1
A symbol is 1 byte or 8 bits. This code is 2
It has an error correction capability that can correct 8 out of 55 symbols. Similarly, the RS (255, 243) coding circuit 602 blocks the input bit string for each 243 symbols, adds check symbols of 12 symbols to this, and outputs a total of 255 symbols. This code has an error correction capability capable of correcting 6 out of 255 symbols. RS (255,
247) The coding circuit 603 blocks the input bit string for every 247 symbols, adds check symbols of 8 symbols to this, and outputs a total of 255 symbols. This code has an error correction capability of correcting 4 out of 255 symbols. In this way, since RS coding with higher error correction capability is performed for an input signal with a higher priority, an input signal with a higher priority has a higher error resilience capability. Next multiplexer 6
Reference numeral 04 time-division-multiplexes the error-correction-coded input signal as described above. That is, the outputs of the above three encoders are input in parallel to the multiplexer 604, and these signals are rearranged using a memory or the like and output in series. Therefore, the output of the multiplexer is a continuous series of digital data. Then, the multiplexed signal is interleaved by the interleave circuit 606 in order to cope with a burst error. FIG. 7 shows the configuration of the interleave circuit. As shown in this figure, in order to make the data writing direction and the data reading direction orthogonal to each other, the unit of the number of bits that the modulation circuit can transmit in one transmission symbol (for example, in the case of the QPSK modulation circuit, two bits are transmitted in one symbol). Even if burst-like noise is received on the transmission line, it can be dealt with as a random error by deinterleaving after demodulation. Further, there is an advantage that the number of interleaving circuits can be saved by interleaving after being multiplexed, as compared with interleaving each of the three sequences before multiplexing. The interleaved signal is modulated by the QPSK modulation circuit 605 and output to the transmission line as a transmission wave. Here, the transmission line is, for example, a satellite line or the like, and in general, disturbance such as noise is added to the transmitted wave.

Example 5. FIG. 8 is a block diagram showing a receiving device according to the fifth embodiment of the present invention. In the figure, 80
6 is a QPSK demodulation circuit for digitally demodulating the received signal, 811 is a deinterleave circuit for deinterleaving the signal interleaved on the transmission side,
807 is a demultiplexer for separating signals multiplexed on the transmission side, and 808, 809, and 810 are respectively
The error correction code RS (255, 2
39) RS (255, 239) decoding circuit for decoding code, RS (25, 239) RS (25 for decoding code)
5, 239) decoding circuit and RS (255, 239) decoding circuit for decoding RS (255, 239) code.

Next, the operation will be described. A signal affected by noise or the like on the transmission path or the like is demodulated by the QPSK demodulation circuit 806. The demodulated one-series digital signal is sent to the deinterleave circuit 811. This makes it possible to deal with the burst-like error received on the transmission line or the like as a random error. Further, by providing the deinterleave circuit before being separated by the demultiplexer, there is an advantage that the number of deinterleave circuits can be saved as compared with the case where the deinterleave circuit is provided for each of the three series of signals after the demultiplexer. The deinterleaved signal is separated by the demultiplexer 807. The separated signals are decoded and output by RS decoding circuits 808, 809, and 810, respectively. This output signal has the highest priority in the order of output signal 1, output signal 2, and output signal 3. Since a signal with a higher priority is subjected to error correction decoding with a higher error correction capability, an output signal with a higher priority is less susceptible to noise. Therefore, even if the reception C / N is deteriorated, the output signal 1, the output signal 2, and the output signal 3 are not deteriorated at the same time, and the output signals of low priority are gradually deteriorated. For example, when receiving a video signal, all output signals do not suddenly deteriorate, but start to deteriorate from high-frequency component signals with low priority,
The mid-range component signal and the high-range component signal are gradually deteriorated in a pure manner.
Then, by judging the error rate of each output signal, etc., the output signals which cannot be reproduced are sequentially cut off,
By displaying the reproducible output signal, it is possible to prevent a sharp deterioration of the received image.

However, in all the above-mentioned embodiments, in order to match the timing of the multiplexer on the transmitting side and the demultiplexer on the receiving side, it is necessary to add a synchronization word after the multiplexer on the transmitting side and detect this on the receiving side. Good. Here, the synchronization word is required to have an error resilience capability equal to or higher than the codeword having the most correction capability among at least three types of error correction coding circuits.

[0029]

Since the present invention is constructed as described above, it has the following effects.

According to the digital signal transmission system of the first aspect of the present invention, compared with the conventional digital transmission system,
Even if the received C / N deteriorates on the receiving side, the received signal does not suddenly deteriorate.

According to the second aspect of the present invention, there is provided a transmitter for generating and transmitting coded signals having different error resilience capabilities according to input signal sequences having different priorities.

Further, according to the digital signal transmitting apparatus of the present invention, the interleaving circuit for coping with the burst error is provided after the input signal is multiplexed, thereby simplifying the circuit configuration of the transmitting apparatus. it can.

Further, according to the digital signal receiving apparatus of the fourth aspect of the present invention, it is possible to obtain the receiving apparatus in which the received signal does not rapidly deteriorate even if the received C / N deteriorates.

Further, according to the digital signal receiving apparatus of the fifth aspect of the present invention, the circuit configuration of the receiving apparatus is simplified by providing the deinterleave circuit for dealing with the burst error before separating the received signal. Can be converted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital signal transmission system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a reception C / N pair transmission efficiency according to the digital signal transmission system in the first embodiment of the present invention.

FIG. 3 is a block diagram showing a transmitting device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a receiving device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a received C / N-to-bit error rate by the receiving device according to the third embodiment of the present invention.

FIG. 6 is a block diagram showing a transmitting device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an interleave circuit according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a receiving device according to a fifth embodiment of the present invention.

FIG. 9 is a block diagram showing a conventional digital signal transmission system.

FIG. 10 is a diagram showing a reception C / N pair transmission efficiency according to the conventional digital signal transmission system.

[Explanation of symbols]

101,601 RS (255,239) coding circuit, 1
02,602 RS (255,243) coding circuit, 10
3,603 RS (255,247) coding circuit, 10
8,808 RS (255,239) decoding circuit, 10
9,809 RS (255,243) decoding circuit, 11
0,810 RS (255,247) decoding circuit, 301
Convolutional code circuit with code rate 1 / 2-constraint length 7, 30
2 code rate 3 / 4-convolutional code circuit with constraint length 7 3
03 Code rate 7 / 8-Convolutional code circuit with constraint length 7
408 Coding rate 1 / 2-Viterbi decoding circuit for convolutional code with constraint length 7; 409 Coding rate 3 / 4-Viterbi decoding circuit for convolutional code with constraint length 7; 410 Coding rate 7
/ 8-8 Viterbi decoding circuit for convolutional code with constraint length 7
04, 304, 604 multiplexer, 107, 40
7,807 Demultiplexer, 606 Interleave circuit, 811 Deinterleave circuit, 105, 30
5,605 QPSK modulation circuit, 106,406,80
6 QPSK demodulation circuit, 901 Error correction code circuit, 9
02 error correction decoding circuit, 905 digital modulation circuit, 906 digital demodulation circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04L 1/00 F 27/22 H04N 1/41 Z 7/24

Claims (5)

[Claims] 1. In a transmission method for digitally transmitting a plurality of input signal sequences having different priorities, on the transmitting side, an error correction code having different error correction capability depending on the priority of the signal sequences is used for all or all of the signal sequences. It is applied to a part and then multiplexed to make a plurality of signal sequences into one sequence, and then digital modulation is performed to generate a transmission signal, and the reception side digitally demodulates the reception signal by the transmission signal and A digital signal transmission system characterized by performing error correction decoding on all or part of a signal sequence after separation after separating the signals. 2. Depending on the priority of a plurality of input signal sequences,
A digital signal transmitting apparatus characterized in that an error correcting code having different correction ability is applied to all or part of it by an error correcting code circuit, multiplexed by a multiplexer, and a transmission signal is generated by a digital modulating circuit. 3. The digital signal transmitting apparatus according to claim 2, wherein an interleaving circuit is provided after the multiplexer to perform the interleaving after the signals are multiplexed. 4. A digital demodulation circuit demodulates a received signal, a demultiplexer separates the demodulated signal, and an error correction decoding circuit performs error correction decoding on all or part of the separated signal sequence. Characteristic digital signal receiving device. 5. The digital signal receiving apparatus according to claim 4, wherein the demultiplexing circuit is provided before the demultiplexer to perform deinterleaving before separating the demodulated signal.