JPH0736680A - Parallel program development support device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a parallelized program development support device that automatically detects a possible parallelization part in a program and notifies it [Configuration] Development support for a well-known compiler 1 The device 2 is connected. In other words, the program analysis unit 4 is shared, the program analysis unit 4 divides the program into predetermined blocks, and the analytic tree generation unit 13 detects a block dependency and generates a tree structure. Since it can be seen that the blocks that are branched by the tree formation and have no dependency relationship with each other can be processed in parallel, they are detected by the block entry unit 14, and each block name, line number of the program and other related blocks are detected. Table is created and stored in the secondary storage unit 15. The display data creation unit 16 extracts parallelizable blocks having no dependency relationship based on the data stored in the secondary storage unit, and outputs at least information regarding the parallelizable blocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel program development support device.

[0002]

2. Description of the Related Art Conventionally, when creating a parallelized program for high-speed processing of an application or the like, a programmer had to be prepared in advance in consideration of parallelization. In many cases, programs are created without being aware of parallelization, but in such cases, when attempting to parallelize after creation, the programmer modifies the program for parallelization while reviewing the entire program list by himself.・ It has to be created, and its work is complicated. Moreover, the larger the capacity of the program, the more difficult it is to detect where parallelization is possible.

Some compilers automatically perform parallelization, but it is also necessary to create a program so that the compiler can be compiled in advance, and the applicable range is narrow and lacks versatility.

The present invention has been made in view of the above background, and an object of the present invention is that even a program created by a programmer without being aware of parallelization can be parallelized. It is an object of the present invention to provide a parallelized program development supporting device capable of supporting program development by automatically detecting a certain place and notifying it.

[0005]

In order to achieve the above-mentioned object, the parallelized program development supporting apparatus according to the present invention comprises a block dividing means 4 for dividing a given program into blocks for performing predetermined processing. , An analysis tree generating means 13 for detecting a dependency relationship of the blocks divided by the block dividing means and generating a tree structure, and an output portion of the analysis tree generating means, and at least an existing portion of a program part constituting each block, A means 14 for associating information of a parent block and a child block to which the block is connected and storing the same in a storage means 15, and parallelization having no mutual dependence on the basis of the associated information stored in the storage means. Extract possible blocks and output at least information about the parallelizable blocks It was constructed from the stage 16..

[0006]

When the program is input to the block dividing means,
Divide into blocks that perform predetermined processing there,
The divided blocks are sent to the analysis tree generation means 13 to detect mutual dependency relationships / connection relationships and generate a tree structure. By forming a tree, the connection relationship of each block becomes clear, and if there is a block that branches from a certain block and has no dependency on each other, it can be seen that the blocks can be processed in parallel. To store. Then, the means for outputting information reads out the data stored in the storage means, extracts parallelizable blocks having no dependency relationship, and outputs at least information on the parallelizable blocks. Then, the programmer or the like can easily recognize the parallelizable part in the series of programs by looking at the output information, and therefore, the parallelization programming is performed based on the parallelization information. Become.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a parallelized program development supporting apparatus according to the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows the overall configuration of an embodiment of the present invention.
As shown in the figure, a parallelized program development support device 2 of the present invention is connected to a known compiler 1. That is, the compiler 1 generates a source language (source code) (when partially expanded, it is also converted into a program written in a current resource word that can be processed by the compiler) The output of the precompiler 3 (atomic program) is sent to the program analysis module 4, and the character string of the source program given here is divided into lexical units of a meaningful basic unit and is permitted as an atomic language. It is designed to check whether or not it is a syntax, and to perform a syntax analysis such as what kind of hierarchical structure the sentence has.

Then, the result of the syntax analysis is sent to the semantic analysis unit 5 in the next stage, and the semantic correctness is checked based on the result of the syntax analysis in the next stage, and if the variable is declared, Information such as the name and type of the variable is registered in the symbol table, and when the executable statement is recognized, the content of the executable statement is specified, the variables used in the statement are checked, and the corresponding After generating the internal format, the semantic analysis result is sent to the optimization unit 6.

The optimization unit 6 checks the given internal format and the like, eliminates redundant processing, and improves the intermediate language so as to enable generation of instructions having a faster execution speed and a smaller target program. It has become. Then, the result of each of the above processes is given to the code generator 7 at the final stage,
It is designed to be converted into a target code such as assembly language or machine language. In addition, each of the above-mentioned modules 3 to 7
Is the same as a conventionally known compiler, and detailed description of the function of each unit is omitted.

Next, the development support device 2 will be described in detail.
In this example, the program analysis module 4 is included, and predetermined processing is performed based on the analysis result output from the program analysis module 4. Then, for convenience of explanation, the internal configuration of the program analysis module 4 will be described.

As shown in FIG. 2, the program analysis unit 4
Is composed of a global block dependency analysis unit 11 that analyzes a global block and a small block dependency analysis unit 12 that analyzes a small block. Here, a global block is a large block in which, for example, when a plurality of programs are combined to generate one new program, the unit of each program before the combination is a global block, and the function and file name change. It is a unit. A small block is a unit that can execute a certain process, such as a part forming one loop or a range covered by an if conditional statement.

In the global block dependency analysis unit 11, specifically, the file dependency analysis unit 11a detects "file", "function", and "jump" in the program and divides them into units to divide them. Set as global block. Then, the function dependence analysis unit 14 refers to the variable existing in each global block to detect the dependency between the global blocks.

The small block dependency analysis unit 12 has a syntax analysis unit 12a and a lexical analysis unit 12b, and performs the above-described syntactic analysis and lexical analysis for each given global block to detect the dependency relationship between the small blocks. To do. In addition, the block is divided into small blocks in parallel with the processing. This division processing is performed for each branch instruction. That is, a program is scanned to detect a branch instruction, and in principle, one branch instruction to the next branch instruction up to one constitutes a small block. However, in the case of a nested structure in which another loop exists within one loop, the outermost frame becomes a unit of a small block.

The output of the program analysis section 4 is given to the analysis tree generation section 13. The analysis tree generation unit 13 includes a built-in block level division unit 13
With a, a tree in which each block is a node is generated based on the given dependency between the small blocks, and a level value is set for each small block. As for this level value, the small block at the top of the tree is set to 1, and thereafter, the level value is incremented every time a branch occurs. Therefore, even if a plurality of blocks (block 3 and block 7) are connected in series (not branched) as shown in FIG. 3,
They are set to the same level value. Further, when a certain block (block 4) is branched into a plurality of blocks (block 5 and block 6), the plurality of blocks are also at the same level.

Further, the analytic tree generation unit 13 has a block correction unit 13b, and performs block integration processing based on the block structure divided into levels by the block level division unit 13a. Specifically, the blocks connected in series are integrated and redefined as a new single block. That is, to explain according to the example of FIG. 3, for example, level 1 block 1 and block 2
Are integrated and defined as a new block (block A). Then, this definition is made by the line number of the source program. By performing such block correction, the tree structure shown in FIG. 3 is redefined as shown in FIG.

The redefinition is performed in order to clarify the blocks (modules) that can be processed in parallel and the blocks (modules) that cannot be processed in parallel. That is, for example, block 3 and block 4 shown in FIG. 3 should be processed after block 2, and since there is no dependency such as variable reference between them, they can be executed in parallel. means. Similarly, since there is no dependency between block 7 and block 4, parallel processing is possible, but block 7 is processed after block 3, and whether parallel processing is possible immediately with block 4 or not. May be difficult to judge. Especially when the program capacity is increased and the tree structure is complicated. However, as shown in FIG. 4, it is possible to more easily determine whether or not parallel processing is possible in the tree structure that is integrated and redefined.

On the other hand, the result of the block correction thus sent is sent to the block entry unit 14 of the next stage, and the block entry table (see FIG. 5) is created based on the tree structure given here, and the secondary entry is made. Storage unit 15
Stored in. Specifically, the entry table generation unit 14a detects the dependency of each block, and the level value of the block, the block name (redefined), and the line number of the source program (defined by the block correction unit 13b). , And a table of parent block names and child block names that have a connection relationship (dependency relationship) with the block. Then, the table thus created is stored in the secondary storage unit 15 via the writing unit 14b.

Further, the table data stored in the secondary storage unit 15 is read out by the display data creating unit 16 and converted into parallelization information, that is, a block dependency graph (tree shown in FIG. 4) and parallelized. The line number of the source program of the convertible block is extracted and output to an output device such as a display device or a printer (not shown). As a result, the program creator or the like can easily recognize a block (module) that can be parallelized based on the output information, and can perform parallelization processing on the source program based on the information. A predetermined correction process is applied to the. In other words, by executing this device for a program created without paying attention to parallelization, it is possible to automatically detect points that can be parallelized.
Development support is provided to reduce the labor and time required to develop parallel programs.

By incorporating such a function in the debugger, the debugging efficiency is improved. It can also be used for performance evaluation of parallel compilers. Furthermore, since the dependency relation and parallel information of the program are displayed on the dedicated user interface, it effectively functions for training of program structure analysis and parallel programming.
That is, by inputting a program created in consideration of parallelization to this device, the parallel state can be easily recognized visually with a tree structure, so that the parallelized programming performed by itself can be evaluated.

[0020]

As described above, in the parallelized program development supporting apparatus according to the present invention, the blocks (predetermined modules of the program) which can be parallelized are automatically detected, and outputs such as display are output. That is, since the locations that are difficult to detect and can be parallelized are automatically extracted, the time and labor required for development can be reduced. Further, when the means for integrating the predetermined blocks divided by the block dividing means is provided, the connection status of each block becomes clearer, and the development support efficiency of parallel programming increases.

[Brief description of drawings]

FIG. 1 is a block diagram showing a preferred embodiment of a development support device according to the present invention.

FIG. 2 is a block diagram showing an internal structure of a development support device of the present embodiment.

FIG. 3 is a diagram illustrating an operation of a block level division unit of an analysis tree generation unit.

FIG. 4 is a diagram illustrating an operation of a block level correction unit of an analysis tree generation unit.

FIG. 5 is a diagram showing an example of a data structure of a table stored in a secondary storage unit.

[Explanation of symbols]

2 parallelization program development support device 4 program analysis unit (block division unit) 13 analysis tree generation unit 13a block level division unit 13b block correction unit 14 block entry unit (means for storing in storage means) 15 secondary storage unit (storage means) ) 16 Display data creation unit (means for outputting information)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshinori Mogi 10 Ouron Co., Ltd. 10 Hanazono Dodocho, Ukyo-ku, Kyoto City, Kyoto Prefecture

Claims (2)

[Claims] 1. A block dividing unit that divides a given program into blocks that perform a predetermined process, and an analysis tree generating unit that detects a dependency relationship of blocks divided by the block dividing unit and generates a tree structure. A means for receiving the output of the analysis tree generation means, associating at least the existence location of the program part constituting each block and the information of the parent block and the child block to which the block is connected, and storing the information in the storage means; Based on the associated information stored in, parallelizable program development support including means for extracting parallelizable blocks having no mutual dependency and outputting at least information on the parallelizable blocks apparatus. 2. The analysis tree generation means comprises block correction means for detecting a connection relation of the divided blocks, integrating blocks connected in series and redefining as a new block. The parallelized program development support device described in.