JPH0736695B2 - Power failure detection circuit - Google Patents
Power failure detection circuitInfo
- Publication number
- JPH0736695B2 JPH0736695B2 JP63149681A JP14968188A JPH0736695B2 JP H0736695 B2 JPH0736695 B2 JP H0736695B2 JP 63149681 A JP63149681 A JP 63149681A JP 14968188 A JP14968188 A JP 14968188A JP H0736695 B2 JPH0736695 B2 JP H0736695B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- circuit
- timer circuit
- terminal
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001514 detection method Methods 0.000 title claims description 15
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Landscapes
- Power Conversion In General (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はスイッチング電源回路に関し、特に交流電源入
力用スイッチング電源回路の停電検出回路に関する。TECHNICAL FIELD The present invention relates to a switching power supply circuit, and more particularly to a power failure detection circuit for an AC power supply input switching power supply circuit.
従来、この種の停電検出回路はスイッチング電源の出力
電圧を検出しており、入力交流電源停電後、出力電圧を
検出し、パルス幅制御回路の機能を停止させ、スイッチ
ング電源の機能を停止する動作を行う。Conventionally, this kind of power failure detection circuit detects the output voltage of the switching power supply.After the input AC power supply fails, the output voltage is detected, the function of the pulse width control circuit is stopped, and the function of the switching power supply is stopped. I do.
上述した従来の停電検出回路は、入力交流電源停電がス
イッチング電源の保持時間を越えると出力電圧の低下を
検出して停止するが、その後直ちに入力交流電源が復旧
すると、スイッチング電源も直ちに復旧するようになっ
ているので、スイッチング電源停止後、所定のリセット
時間を必要とするシステムのイニシャルリセット回路の
タイマー回路が完全にリセットを終らず、システムが誤
動作する欠点がある。The above-mentioned conventional power failure detection circuit detects the output voltage drop when the input AC power failure exceeds the holding time of the switching power supply and stops, but when the input AC power is restored immediately thereafter, the switching power supply is also immediately restored. Therefore, there is a drawback that the timer circuit of the initial reset circuit of the system, which requires a predetermined reset time after the switching power supply is stopped, does not completely reset and the system malfunctions.
本発明の停電検出回路はブリッジダイオードの正端子に
レベル検出回路と電源回路とを接続し、前記レベル検出
回路の出力端子を第１のタイマー回路の入力端子に接続
し、前記第１のタイマー回路の出力端子に第２のタイマ
ー回路の入力端子を接続し、前記電源回路の出力正端子
に前記第１のタイマー回路および前記第２のタイマー回
路の電源正端子と互いに直列接続された抵抗およびフォ
トカプラの発光素子とを接続し、前記第２のタイマー回
路の出力端子に前記フォトカプラの発光素子のカソード
端子を接続し、前記第１のタイマー回路および前記第２
のタイマー回路の電源負端子および前記レベル検出回路
を前記ブリッジダイオードの負端子に接続した構成であ
る。In the power failure detection circuit of the present invention, the level detection circuit and the power supply circuit are connected to the positive terminal of the bridge diode, the output terminal of the level detection circuit is connected to the input terminal of the first timer circuit, and the first timer circuit is connected. An input terminal of a second timer circuit is connected to an output terminal of the resistor, and a positive output terminal of the power supply circuit is connected in series with a positive power supply terminal of the first timer circuit and the second power supply circuit of the second timer circuit. The light emitting element of the coupler is connected to the output terminal of the second timer circuit, and the cathode terminal of the light emitting element of the photocoupler is connected to the first timer circuit and the second timer circuit.
The power supply negative terminal of the timer circuit and the level detection circuit are connected to the negative terminal of the bridge diode.
本発明においては、交流電源入力スイッチング電源の入
力交流電源停電時間がスイッチング電源の出力保持時間
を越えると出力電圧の低下を検出してスイッチング電源
を停止させ、スイッチング電源停止後、直ちに入力交流
電源が復旧した場合でも第１のタイマー回路は入力交流
電源復旧後クリアされるが、第２のタイマー回路は保持
され、システムのイニシャルリセット回路のタイマー回
路が完全にリセットを終えた後にスイッチング電源を起
動させる。In the present invention, when the input AC power interruption time of the AC power input switching power supply exceeds the output holding time of the switching power supply, the switching power supply is stopped by detecting the decrease of the output voltage, and immediately after the switching power supply is stopped, the input AC power supply is Even when restored, the first timer circuit is cleared after the input AC power is restored, but the second timer circuit is retained and the switching power supply is started after the timer circuit of the system initial reset circuit has completely reset. .
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
一実施例を示す第１図、第２図および第３図を参照する
と、レベル検出回路20は電圧分圧抵抗2,3から成る。第
１のタイマー回路30および第２のタイマー回路40はCMOS
M/M素子10を用いて構成し、抵抗５および抵抗６とコ
ンデンサ７およびコンデンサ８とは時定数を設定する。
電源回路50は抵抗４およびコンデンサ９から構成され
る。続いて、この停電検出回路の動作を説明すると、入
力光流電源13はブリッジダイオード１により全波整流さ
れ、レベル検出回路20により第１のタイマー回路30の入
力トリガ電圧とする。第１のタイマー回路30の素子M/M1
は入力トリガ電圧のスレシユホールドレベルＶTHを検出
し抵抗５およびコンデンサ７により設定する時間T1経過
後、出力をハイ“H"レベルにして第２のタイマー回路40
を駆動する。この時間T1は入力交流電源13の停電後、ス
イッチング電源が出力電圧を保持することが可能な時間
に設定する。第２のタイマー回路40は第１のタイマー回
路30の信号を受けて抵抗６およびコンデンサ８により設
定する時間T2の関、出力を“H"レベルにしてフォトカプ
ラ12の発光素子を駆動し、フォトカプラ12の発光素子に
接続されたスイッチング電源の制御回路60を一時的に停
止させてスイッチング電源を停止させる。このとき、時
間T2は、システムのイニシャルリセット回路のタイマー
回路の放電に必要な時間に設定する。Referring to FIG. 1, FIG. 2 and FIG. 3 showing an embodiment, the level detecting circuit 20 comprises voltage dividing resistors 2 and 3. The first timer circuit 30 and the second timer circuit 40 are CMOS
It is configured by using the M / M element 10, and the time constants of the resistors 5 and 6 and the capacitors 7 and 8 are set.
The power supply circuit 50 is composed of a resistor 4 and a capacitor 9. Next, the operation of this power failure detection circuit will be described. The input light current power supply 13 is full-wave rectified by the bridge diode 1, and the level detection circuit 20 uses it as the input trigger voltage of the first timer circuit 30. Element M / M1 of the first timer circuit 30
Detects the threshold level V TH of the input trigger voltage and sets the output to the high “H” level after the elapse of time T 1 set by the resistor 5 and the capacitor 7.
To drive. This time T 1 is set to a time at which the switching power supply can maintain the output voltage after the power failure of the input AC power supply 13. The second timer circuit 40 receives the signal from the first timer circuit 30, sets the output to the “H” level for the time T 2 set by the resistor 6 and the capacitor 8, and drives the light emitting element of the photocoupler 12. The control circuit 60 of the switching power supply connected to the light emitting element of the photocoupler 12 is temporarily stopped to stop the switching power supply. At this time, the time T 2 is set to the time required for discharging the timer circuit of the initial reset circuit of the system.
以上説明したように本発明によれば、入力交流電源停電
後、スイッチング電源が出力電圧を保持することが可能
な時間をおいてスイッチング電源を停止させ、スイッチ
ング電源が停止後、直ちに入力交流電源が復旧しても、
システムが正常に動作するようにシステムのイニシャル
リセット回路のタイマー回路の放電に必要な時間はスイ
ッチング電源を停止させておくことにより、停電復旧
後、安定にシステムを動作できる効果がある。As described above, according to the present invention, after an input AC power supply power failure, the switching power supply is stopped after a period in which the switching power supply can hold the output voltage, and immediately after the switching power supply is stopped, the input AC power supply is Even if it is restored,
Since the switching power supply is stopped for the time required for discharging the timer circuit of the initial reset circuit of the system so that the system operates normally, there is an effect that the system can be operated stably after the power failure is restored.
第１図及び第２図は本発明の構成図、第３図は同実施例
の動作を説明するための図である。 １……ブリッジダイオード、20……レベル検出回路、30
……第１のタイマー回路、40……第２のタイマー回路、
50……電源回路、60……スイッチング電源の制御回路。1 and 2 are configuration diagrams of the present invention, and FIG. 3 is a diagram for explaining the operation of the embodiment. 1 ... Bridge diode, 20 ... Level detection circuit, 30
...... First timer circuit, 40 ...... Second timer circuit,
50: Power supply circuit, 60: Switching power supply control circuit.
Claims (1)
回路と電源回路とを接続し、前記レベル検出回路の出力
端子を第１のタイマー回路の入力端子に接続し、前記第
１のタイマー回路の出力端子に第２のタイマー回路の入
力端子を接続し、前記電源回路の出力正端子に前記第１
のタイマー回路および前記第２のタイマー回路の電源正
端子と互いに直列接続された抵抗およびフォトカプラの
発光素子とを接続し、前記第２のタイマー回路の出力端
子に前記フォトカプラの発光素子のカソード端子を接続
し、前記第１のタイマー回路および前記第２のタイマー
回路の電源負端子および前記レベル検出回路を前記ブリ
ッジダイオードの負端子に接続したことを特徴とする停
電検出回路。1. A level detection circuit and a power supply circuit are connected to a positive terminal of a bridge diode, an output terminal of the level detection circuit is connected to an input terminal of a first timer circuit, and an output of the first timer circuit. The input terminal of the second timer circuit is connected to the terminal, and the first positive terminal is connected to the output positive terminal of the power supply circuit.
The timer circuit and the power supply positive terminal of the second timer circuit are connected to the resistor and the light emitting element of the photocoupler connected in series, and the cathode of the light emitting element of the photocoupler is connected to the output terminal of the second timer circuit. A power failure detection circuit, wherein terminals are connected to each other, and the power supply negative terminals of the first timer circuit and the second timer circuit and the level detection circuit are connected to a negative terminal of the bridge diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149681A JPH0736695B2 (en) | 1988-06-17 | 1988-06-17 | Power failure detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149681A JPH0736695B2 (en) | 1988-06-17 | 1988-06-17 | Power failure detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01318542A JPH01318542A (en) | 1989-12-25 |
| JPH0736695B2 true JPH0736695B2 (en) | 1995-04-19 |
Family
ID=15480496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63149681A Expired - Fee Related JPH0736695B2 (en) | 1988-06-17 | 1988-06-17 | Power failure detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736695B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5304253B2 (en) * | 2009-01-05 | 2013-10-02 | パナソニック株式会社 | Cooker |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62152372A (en) * | 1985-12-25 | 1987-07-07 | Nec Corp | Power source device |
-
1988
- 1988-06-17 JP JP63149681A patent/JPH0736695B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01318542A (en) | 1989-12-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |