JPH0736701A - Program execution device - Google Patents

Abstract

(57) [Summary] [Object] To provide a program execution device capable of preventing the complexity when switching a plurality of software and reducing the cost of the entire device by eliminating circuit waste. [Structure] The program execution apparatus according to the present exemplary embodiment includes a program execution unit 10, a transfer program / data identification unit 11, a transfer source storage unit 12, a transfer destination storage unit 18, and a search program storage unit 23. Search program storage 2
The program execution unit 10 that has executed the search program stored in 3 stores only the program or data specified by the transfer program / data specifying unit 11 from the plurality of transferred programs or data.
2 is searched, and the searched program or data is transferred to the transfer destination storage unit 18 by executing the transfer program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program execution device for a game device or the like, which selects and executes a plurality of programs and data as appropriate.

[0002]

2. Description of the Related Art Conventionally, a home-use game machine has a game machine body composed of a processor and hardware such as RAM forming a work area used by the processor, and a ROM cassette electrically connected to the game machine body. It consists of In the ROM cassette, one type of game software is stored in the ROM as a game program and game data used for the game program. Therefore, if the user wants to play multiple types of games, prepare a ROM cassette in which each game software is installed, insert the ROM cassette of the desired game into the connector of the game machine body, and Just run the software.

FIG. 15 is a conceptual diagram when a plurality of types of games are played on the above-mentioned home-use game machine. As described above, when the user inserts an arbitrary ROM cassette into the connector of the game machine body, the processor in the game machine body executes the game program and data in the ROM cassette. This allows the user to enjoy any game.

In the conventional video game consoles for business use, airplanes and control simulators for various vehicles, ROM and RAM for storing programs and data, and hardware including mechanical parts such as control sticks and operating levers,
There was a one-to-one correspondence with software that uses this hardware. Therefore, when changing the software, it is necessary to replace the ROM storing the software such as programs and data for each board.

Further, a part of the conventional commercial video game machine is provided with a plurality of program boards which can be operated separately in one housing, and one of the program boards is selected and used. was there. In such an arcade video game machine, the configuration other than the program board, that is, only the input / output circuits such as the display device and the operation panel are shared. Therefore, when one game is selected by the user, the corresponding program board and the input / output circuit are electrically connected, and the game processing by this program board is executed.

[0006]

By the way, the above-mentioned R
In a home-use game machine using an OM cassette, in order to use software for a plurality of games, a ROM cassette must be prepared and replaced for each software, which complicates the operation and reduces the cost of the entire device. There was a problem of this.

Further, in the above-mentioned arcade game machine or the like in which the hardware and the software are in a one-to-one correspondence,
Since exchanging software requires time and effort equivalent to remodeling the entire apparatus, it is almost impossible to execute plural pieces of software.

Further, in the arcade game machine capable of executing a plurality of software by having a plurality of program boards, the parts other than the input / output device are provided for each software, so that the duplicated components are In many cases, there was a problem that the circuit was wasted. Particularly, a simulator for a three-dimensional image requires considerably expensive hardware because of the complexity of image processing and the required processing speed.

Therefore, the present invention was created in view of the above point, and an object thereof is to prevent complications when switching a plurality of software and to eliminate the waste of the circuit of the entire apparatus. An object is to provide a program execution device that reduces costs.

[0010]

In order to solve the above-mentioned problems, a program execution apparatus of the present invention is a transfer source that stores a plurality of transferred programs or data and a transfer program for performing transfer processing. A storage means, a transfer destination storage means for transferring the transferred program or data and storing the transferred program or data as a transfer program or data, and a transfer target from a plurality of transferred programs or data stored in the transfer source storage means. Transfer program / data specifying means for specifying one or more programs or data to be
Stored in the search program storage means and a search program storage means for storing a search program for searching the storage area of the transfer source storage means for one or a plurality of programs or data specified by the data specification means to be transferred. By executing the retrieved program, one or more programs or data to be transferred identified by the transfer program / data identification means are retrieved, and the transfer program stored in the transfer source storage means is searched. Program execution means for transferring the retrieved one or more programs or data to the transfer destination storage means by executing the program or data after the transfer stored in the transfer destination storage means. It is characterized by performing a predetermined process.

[0011]

The transfer source storage means stores at least one of a plurality of transferred data or programs and a transfer program, and only one or a plurality of programs or data specified by the transfer program / data specifying means ( The specified program or data is
In addition to the case of only one of the program and the data, both the program and the data may be specified simultaneously) are transferred to the transfer destination storage means.

When a program or data is transferred from the transfer source storage means to the transfer destination storage means, the program execution means executes the search program stored in the search program storage means to identify the one specified. Alternatively, a plurality of programs or data are searched.

Next, the program execution means executes the transfer program stored in the transfer source storage means. Then, the transferred program or data in the transfer source storage means searched by the search operation described above is transferred to the transfer destination storage means.

In this way, the transfer source storage means stores the transfer program together with the transferred program or data, and after the program or data to be transferred is searched, the transfer program is executed to store the transfer destination. Transfers programs or data to the means. Therefore, it is necessary to store programs or data corresponding to a plurality of software in the transfer source storage means, transfer only those to be executed to the transfer destination storage means, and perform processing using the transferred programs or data. As a result, it becomes possible to execute a plurality of software by using the transfer destination storage means common to the plurality of software.

In the present invention, since the software is executed after the data or programs corresponding to the plurality of software are transferred to the transfer destination storage means as necessary, the hardware for switching the plurality of software It is not necessary to replace the above, and the complexity of the operation can be avoided. In addition, since a common transfer destination storage means is used when executing a plurality of software, it is possible to eliminate a redundant part of hardware and reduce circuit waste. Further, since the software is executed by using the transfer destination storing means, the circuit does not become unnecessarily complicated. Further, even when the ROM is changed to change the program or data, it is convenient because it can be done collectively.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(1) Overall Configuration and Operation of Embodiment FIG. 1 is a diagram showing a schematic configuration of a program execution device of an embodiment to which the present invention is applied. This figure shows a partial configuration of a home / commercial video game machine or a flight simulator for airplanes and various vehicles.

The program execution apparatus shown in FIG. 1 includes a program execution unit 10, a transfer program / data identification unit 11,
The transfer source storage unit 12, the transfer destination storage unit 18, and the search program storage unit 23 are included.

The program execution unit 10 is composed of a central processing unit (CPU), and executes a predetermined game calculation by executing a game program or data, for example.

The transfer source storage unit 12 stores the transfer program 1
4, the transferred program 15 and the transferred data 16 are stored. The transferred program 15 and the transferred data 16 are programs and data corresponding to each of a plurality of types of software, and are provided by the number corresponding to the type of game or simulation operation. The transfer program 14 is a program for transferring at least one of the transferred program 15 and the transferred data 16 into the transfer destination storage unit 18, and a plurality of transferred programs 1
5, a plurality of data are provided for each of the transferred data 16.

The transfer destination storage unit 18 is for storing the transferred program 15 and the transferred data 16 stored in the transfer source storage unit 12 after the transfer. The transferred program 15 and the transferred data 16 transferred from the transfer source storage unit 12 are stored in the transfer destination storage unit 18 as the transfer program 21 and the transfer data 22. Also,
At the time of transferring the program, the transfer program 14 is also transferred correspondingly and stored in the transfer destination storage unit 18 as the transfer program 20.

The search program storage unit 23 includes a plurality of transferred programs 15 stored in the transfer source storage unit 12,
A search program for searching for a program or data to be transferred from the transferred data 16 is stored. This search program is read and executed by the program execution unit 10.

The transfer program / data specifying unit 11 specifies the transferred program 15 and the transferred data 16 to be transferred from the transfer source storage unit 12 to the transfer destination storage unit 18. As a method of specifying, for example, an identification code (ID) consisting of numbers or alphabets is assigned to each program or data, and the identification code is designated. Further, the number of programs and data to be specified may be one or more, and the programs and data to be transferred may be specified at the same time.

Next, the operation of transferring a program or data in the program execution apparatus of this embodiment having such a configuration will be described. It should be noted that the transfer source storage unit 12 stores a plurality of transferred programs 15 and a plurality of transferred data 16 corresponding to a plurality of software in advance. For example, arbitrary software is selected according to an instruction from the player. Then, consider the case where only the corresponding programs and data are executed.

First, the program execution unit 10 reads out and executes the search program stored in the search program storage unit 23 to thereby receive the transferred program 15 or the transferred data 16 specified by the transfer program / data specifying unit 11. From the transfer source storage unit 12. The transferred program 15 or the transferred data 16 specified by the transfer program / data specifying unit 11
May be one or plural, and the transferred program 15 and the transferred data 16 may be specified and searched at the same time.

Next, the program execution unit 10 executes the transfer program 14 stored in the transfer source storage unit 12 to retrieve the transferred program 15 or the transferred data 16 retrieved by the above-described retrieval operation. The transfer operation of storing the transfer program 21 or the transfer data 22 in the transfer destination storage unit 18 is performed.

After that, the program execution unit 10 executes the transfer program 21 transferred to the transfer destination storage unit 18 and stored therein, or by executing a predetermined program using the transfer data 22, so that the player Execute the specified software.

The transfer program 14 described above is
In addition to using the one stored in the transfer source storage unit 12, a transfer program 14 is prepared corresponding to the program or data to be transferred, and the transfer program 14 corresponding to the program or data to be transferred is also prepared. Also, after the transfer of the transfer program 14 is completed, the remaining program or data may be transferred by executing the program (transfer program 20) stored in the transfer destination storage unit 18. Good.

As described above, in the present embodiment, the transfer source storage unit 12 stores a plurality of transferred programs 15 or transferred data 16 corresponding to a plurality of software, and searches only the one to be executed. Transfer destination storage unit 18
Have transferred to. Therefore, the program execution unit 10 uses the transfer program 2 stored in the transfer destination storage unit 18 after the transfer.
By executing 1 or the transfer data 22, it is possible to execute a predetermined game calculation or simulation process.

Therefore, even when a plurality of pieces of software are selectively executed, only the program or data to be transferred from the transfer source storage section 12 to the transfer destination storage section 18 need be retransferred. It is possible to prevent complexity when switching between. Further, since the program execution unit 10 only needs to execute the transfer program data stored in the common transfer destination storage unit 18, it is possible to minimize the overlapping circuit configuration and eliminate the waste of the circuit. You can

(2) Specific Structure When Applied to Driving Simulator FIG. 2 is a diagram showing a specific structure of the simulator when the program execution device shown in FIG. 1 is applied to a driving simulator. The simulator shown in the figure is
CPU board 24, ROM board 26, CPU board 2
8, DSP board 30, PGN (polygon) board 3
2, an OBJ (object) board 34, a CRT (cathode ray tube) 36, and an I / O CPU board 38.

The CPU board 24 performs calculations such as character coordinate calculation and action pattern setting in this simulator. For example, in a driving simulator for learning in which a plurality of vehicles appear as oncoming vehicles, the CPU board 24 causes the processing such as steering wheel data, accelerator, and brake to actually run the vehicle of the player and the absolute coordinate space of this vehicle. Coordinate calculation of
Controls oncoming vehicles and calculates coordinates of oncoming vehicles in absolute coordinate space.

FIG. 3 is a diagram showing a detailed structure of the CPU board 24. The CPU board 24 shown in FIG.
PU 40, reset circuit 42, I / O port 44, BO
OTROM46, WORK RAM47, PROGR
AM48, backup RAM49, shared RAM50,
It is configured to include a communication IC 52.

The CPU 40 is, for example, a 16-bit CPU, and has a BOOT ROM 46 or a PROG RAM.
Predetermined processing is performed by reading and executing the program stored in 48.

The BOOT ROM 46 is the CPU 40
Stores in PROG RAM 48 a search program for searching the address on the ROM 62 of the program for transferring the program for the time being in order to properly transfer the predetermined simulation data and the program in order to properly transfer the program. As described above, this search program is read and executed by the CPU 40.

The WORK RAM 47 is the ROM board 2
6 stores a comparison table showing the correspondence between the numbers of the plurality of simulation software stored in the ROM 62 and the addresses of the ROM 62 in which each software is stored.

The PROG RAM 48 is a memory for transferring and storing a program (simulation program) retrieved by executing the retrieval program. The program stored in the PROG RAM 48 is read and executed by the CPU 40. Thus, a predetermined simulation calculation is performed. Note that this simulation program is a C that functions as a master.
This is for operating the PU 40, and in the case of the driving simulator for learning, it includes a function of controlling the entire story of learning as well as setting the driving scene and driving conditions.

The backup RAM 49 is for storing the last software number when this simulator was operated before, and is a non-volatile memory (EE).
PROM). That is, every time the software to be used is changed, the software number is stored in the backup RAM 49, and the contents are retained when the power is turned off. Therefore, by reading the contents of the backup RAM 49 next time, the software that was operating before can be known.

The shared RAM 50 is used for exchanging data such as calculation results between the CPU 40 and a CPU 54, which will be described later, in the CPU board 28, and is composed of, for example, a dual port RAM.

The reset circuit 42 inputs a reset signal to the CPU 40 when the simulator device is activated. When this reset signal is input to the CPU 40, C
The PU 40 is adapted to read and execute the search program stored in the BOOT ROM 46.

The I / O port 44 is for outputting a reset signal to a CPU 54 in the CPU 28, which will be described later. When a predetermined data or address is input from the CPU 40 to the I / O port 44, a reset signal is output from the I / O port 44.

The communication IC 52 is the I / O CPU board 3
This is for inputting / outputting predetermined communication data to / from. Details of the exchanged communication data will be described later.

The CPU 40 described above uses the I / O port 4
4, BOOT ROM46, WORKRAM47, PR
OG RAM 48, backup RAM 49, shared RA
It is connected to the M50 and the communication IC 52 via the address bus 40a and the data bus 40d. Also, shared RA
The M50 is connected to a later-described CPU 54 in the CPU board 28 via an address bus 54a and a data bus 54d.

The CPU board 28 shown in FIG. 2 mainly controls the DSP board 30, the PGN board 32, and the OBJ board 34 to control the video output to the CRT 36. The operation is started when the reset signal output from the I / O port 44 is released.

FIG. 4 is a diagram showing a detailed configuration of the CPU board 28. The CPU board 28 shown in FIG.
PU 54, I / O port 56, BOOT ROM 58,
It is configured to include a WORK RAM 59 and a PROG RAM 60.

The CPU 54 is composed of, for example, a 32-bit CPU. In general, enormous amount of data processing is required for image processing. Therefore, the CPU 54 is the CPU described above.
A CPU having a higher performance than that of the CPU 40 in the board 24 is used. The CPU 54 has a structure other than that, that is, an I / O port 56, a BOOT ROM 58, and a WORKR.
AM59, PROG RAM60 and address bus 54a
And a data bus 54d, so that data and addresses can be input and output. Also, CP
A reset signal output from the I / O port 44 in the CPU board 24 is input to U54. Therefore, the CPU 54 does not operate while the reset signal is input, and the CP 54 is not activated until the reset signal is released.
U54 starts operation.

The BOOT ROM 58 is the CPU described above.
The program corresponds to the BOOT ROM 46 in the board 24, and is a program for the time being to prepare an operating environment for properly transferring a predetermined simulation program and data stored in a ROM 62 described later in the ROM board 26. Store a search program to search for a program to transfer.

The WORK RAM 59 is the ROM board 2
6 stores a comparison table showing the correspondence between the numbers of the plurality of simulation software stored in the ROM 62 and the addresses of the ROM 62 in which each software is stored.

In the PROG RAM 60, the CPU 54 is B
This is a storage destination when a predetermined simulation program searched by executing the search program in the OOT ROM 58 is transferred. After storing the simulation program in the PROG RAM 60, the CPU 54 reads out the stored program and controls the video output when performing a predetermined simulation process. It should be noted that this simulation program is for operating the CPU 54 as a slave CPU of the CPU 40, and in the case of a training driving simulator, includes a function of controlling individual movements such as an appearing automobile and a human action pattern. I'm out.

The I / O port 56 is a DSP (digital signal processing device) 6 to be described later in the DSP board 30 when a predetermined address or data is input from the CPU 54.
The reset signal is output to No. 4.

The ROM board 26 shown in FIG. 2 is for storing all the software corresponding to a plurality of games, and includes the CPU board 24 and the CP described above.
It is accessible from both of the U boards 28.

FIG. 5 is a diagram showing a detailed structure of the ROM board 26. The ROM board 26 shown in FIG.
Dual port ROM with system input / output terminals
62 is included.

The ROM 62 is a CP in the CPU board 24.
The bus is connected to the address bus 40a and the data bus 40d connected to the U40, and also to the address bus 54a and the data bus 54d connected to the CPU 54 in the CPU board 28. For example,
The ROM 62 is for storing a plurality of types of simulation software each including display data for 6 screens, and has a capacity of 32 Mbytes.
The ROM 62 having such a large capacity is generally composed of a plurality of elements.

FIG. 6 is a diagram showing a specific example in the case where the ROM 62 is constructed by using a plurality of elements. In the figure,
ROM 62-1L to 62-16L and 62-1U to 6
Each of 2-16U is a ROM of 1M bit, 2M bit or 4M bit, and each has a data structure of 8 bits. Therefore, when handling 16-bit data by the 16-bit CPUs 40 and 54 as in the present embodiment, two of these ROMs are combined and accessed simultaneously.

In the configuration shown in FIG. 6, the lower 8 bits of the 16-bit data are stored in the ROM marked "L", and the upper 8 bits of the 16-bit data are stored in the ROM marked "U". Store a bit. Specifically, the ROM 62-
Taking 1 as an example, the lower 8 bits of 16-bit data are stored in the ROM 62-1L, and the other upper 8 bits are stored in the ROM 62-1U. When the ROM 62 is accessed by the CPU 40 or 54,
By simultaneously accessing these two ROMs 62-1L and 62-1U, 16-bit data is read and written.

Further, the DSP board 30 shown in FIG. 2 performs data processing such as coordinate conversion such as perspective conversion of a three-dimensional display object for each display screen.
The operation is started when the reset signal output from the / O port 56 is released.

FIG. 7 is a diagram showing a detailed configuration of the DSP board 30. The DSP board 30 shown in FIG.
SP64, BOOT ROM66, PROG RAM6
8, shared RAM 70, and point RAM 72. In the simulator of this embodiment,
Six display screens are used in one simulation software, and it is assumed that the DSP board 30 also has six display screens corresponding to the number of display screens. This also applies to the PGN board 32, the OBJ board 34, and the CRT 36. For example, in simulation software in which a player operates his / her own vehicle, it is possible to display a total of 6 screens on the front surface (front glass) of the vehicle, the left and right side surfaces, the left and right side mirrors, and the rear mirror.

The DSP 64 is for processing image data composed of 16 bits, for example. Also, D
The reset signal output from the I / O port 56 in the CPU board 28 is input to the SP 64. Therefore,
While this reset signal is being input, the DSP 64 does not operate, and when this reset signal is released D
SP64 starts operation.

In the BOOT ROM 66, the DSP 64 is D
Since a program for initializing the SP board 30 is stored and has nothing to do with the gist of the present invention, detailed description thereof will be omitted.

The PROG RAM 68 has three display screens.
The dual port RAM is used to store a program (including initial data transferred to the point RAM 72) that calculates the vertex coordinates and the like of the three-dimensional display object. This program is CPU board 28
ROM 6 in the ROM board 26 by the CPU 54 in the
It is transferred from 2.

The shared RAM 70 is composed of a dual port RAM which the DSP 64 and the CPU 54 in the CPU board 28 can separately access, and is used for exchanging data between these processors.

The point RAM 72 is for storing the X, Y, Z coordinates of the three-dimensional display object before perspective transformation, which are necessary for polygon processing. This point RAM7
2 is P when the simulator is started or reset
The initial data transferred to the ROG RAM 68 is transferred.

The above-described DSP 64 has a configuration other than that,
That is, BOOT ROM 66, PROG RAM 6
8. The shared RAM 70 and the point RAM 72 are connected to each other via the address bus 64a and the data bus 64d so that data and addresses can be input / output. Further, the PROG RAM 68 and the shared RAM 70 are connected to the address bus 54a and the data bus 54b connected to the CPU 54 described above, and are capable of inputting / outputting data and addresses.

The PGN board 32 shown in FIG. 2 is for performing polygon processing based on the perspective-transformed X, Y, Z coordinates of the three-dimensional display object calculated by the DSP board 30 described above. is there.

FIG. 8 is a diagram showing a detailed configuration of the PGN board 32. The PGN board 32 shown in the figure includes a polygon processing circuit 74, a line RAM 76, and a point RA.
It is configured to include an M78 and a line buffer 80.

The polygon processing circuit 74 is connected to the DSP board 3
The calculation of the contour line and the intersection coordinates of the contour line and the scanning line for display are performed based on the vertex coordinates of the polygon and the accompanying data supplied from 0, and the processing is performed to paint the space between the calculated intersection points with predetermined color data. To do.

The line RAM 76 is for storing contour line data for each polygon of the three-dimensional display object displayed on each display screen at the start of the simulation operation. Further, after the new contour line of the polygon is calculated by the polygon processing circuit 74, the calculated contour line data is stored in the line RAM 76.

The point RAM 78 stores the coordinate data necessary for the contour line calculation for each polygon and functions as a work area for the polygon processing circuit 74.

The line buffer 80 is for storing the color data between the intersections calculated by the polygon processing circuit 74 in scanning line units. This line buffer 80
The data stored in is output to the pallet controller 94, which will be described later, in the OBJ board 34 as display data.

The OBJ board 34 shown in FIG. 2 is for creating data of a display object to be actually displayed on the CRT 36 in pixel units.

FIG. 9 is a diagram showing a detailed structure of the OBJ board 34. The OBJ board 34 shown in the figure includes a drawing controller 82, an OBJ RAM 84, and a CG RA.
M86, CG ROM 88, frame buffer 90, display controller 92, palette controller 94, palette RAM 96, latch 98, D / A converter 100
It is configured to include.

The drawing controller 82 is an OBJ RAM.
The data stored in 84 is read, and the CG RAM 86 or CG ROM is read based on the read data.
Address 88. 2 in OBJ RAM84
The coordinate data of the three-dimensional display object and the CG (character generator) code corresponding to this display object are stored, and the drawing controller 82 reads the CG code at a predetermined position in the marking screen.
And this CG code is CG RAM86 or C
The address is input to the G ROM 88, and the corresponding CG data is output from the CG RAM 86 or the CG ROM 88.

The frame buffer 90 is for storing the image data of the entire display screen in dot units.
When the display data is stored in the frame buffer 90, the address is specified by the drawing address output from the drawing controller 82 described above, and the drawing data output from the display controller 92 is stored in the address. Further, when reading data from the frame buffer 90, addressing is performed by the display address output from the display controller 92, and the data stored at the address is read as display data.

The palette controller 94 displays the display data of the two-dimensional display object read from the frame buffer 90 and the display data of the three-dimensional display object input from the line buffer 80 in the PGN board 32, which has the highest priority. Output selectively. The palette RAM 96 receives display data output from the palette controller 94 as an address, and outputs actual color data corresponding to the input display data.

The latch 98 temporarily holds the color data output from the palette RAM 96, and then the D / A converter 1
The held data is input to 00. The D / A converter 100 is for converting the input color data into an RGB signal, and the converted RGB signal together with the synchronization signal output from the display controller 92 are shown in FIG.
Is output to the CRT 36 shown in FIG. Therefore, the CRT 36 connected to the OBJ board 34 displays two-dimensional and three-dimensional display objects according to the progress of the simulation operation.

The I / O CPU board 3 shown in FIG.
Reference numeral 8 is for performing data processing relating to an operation instruction from the player, and is adapted to send data according to the operation of the player to the CPU board 24.

FIG. 10 shows the I / O CPU board 38.
It is a figure which shows the detailed structure of. I / O CP shown in the figure
The U board 38 includes a CPU 102, a reset circuit 104,
It includes a PROG ROM 106, a RAM 108, an I / O port 110, a communication IC 112, and an operation panel 114.

The CPU 102 is composed of a 16-bit CPU. Since the CPU 102 is used only for processing the input data, its content is relatively simple, and a CPU having a relatively low speed is used as compared with the CPUs 40 and 54 described above. This CPU 102 is a PROG
It is connected to the ROM 106, PROG RAM 108, I / O port 110, communication IC 112 via the address bus 102a and the data bus 102d, and can input / output data and addresses. Also, CPU
The reset signal output from the reset circuit 104 is input to 102, and is reset by this reset signal when the operation is started.

The PROG ROM 106 is the CPU 102.
Stores in advance programs and data for operating. Further, the PROG RAM 108 is the CPU 10
2 serves as a work area for operating.

The I / O port 110 has an operation panel 114.
It is for inputting / outputting data between and. The I / O port 110 is used for the data bus 102 when a predetermined address is input via the address bus 102a.
Operation panel 1 that captures data input via d
Output to the 14 side. Alternatively, this I / O port 110
When a predetermined address is input via the address bus 102a, the input data is input from the operation panel 114 side and is output to the data bus 102d.

The operation panel 114 includes a ten-key switch and a 7-segment LED. The ten-key switch can receive an instruction from the player, and the LED displays the current operation status to the player. It is supposed to be possible.

The communication IC 112 serves as an interface for inputting / outputting data between the I / O CPU board 38 and the CPU board 24. After reading the operation status of the ten-key switch on the operation panel 114, the CPU 102 sends data according to this operation status to the CPU board 24 via the communication IC 112. In addition, the CPU 102
After receiving the data related to the operation instruction sent from the CPU board 24 via the communication IC 112, the I
LED in the operation panel 114 via the / O port 110
The predetermined display is performed.

(3) Specific Operation When Applied to Driving Simulator Next, in the driving simulator having the above-described configuration, prior to the start of the operation, the program and the data corresponding to the software executed immediately before are automatically executed. A specific operation of this embodiment for transferring from the ROM 62 in the ROM board 26 to the RAM in various boards will be described.

In this embodiment, the following RAMs are required to set a program or data at the time of startup.

PROG RAM 48 (CPU board 2
4) PROG RAM 60 (CPU board 28) PROG RAM 68 (DSP board 30) Point RAM 72 (DSP board 30) Line RAM 76 (PGN board 32) CG RAM 86 (OBJ board 34) Pallet RAM 96 (OBJ board 34) The number in parentheses indicates the type of board on which each RAM is mounted.

The programs or data to be transferred to the above-mentioned RAMs are stored in the ROM in the ROM board 26.
The data is stored in 62, and the transfer is performed prior to the execution of the simulation processing. In addition, the software number executed immediately before is the CPU board 24.
It is stored in the internal backup RAM 49, and the stored software number is read at the time of startup.

FIG. 11 is a diagram showing a storage state of programs or data stored in the ROM 62. FIG. 9A shows the storage state of the program transferred by the CPU 40. As shown in the figure, a capacity of $ 040000 ($ represents a hexadecimal number) bytes is prepared for this program area, and a program or data to be transferred is identified at the address up to $ 40. The ID code for this purpose and the software number for specifying the type of software to be implemented are included. And $
PROG RAM 48 at addresses after 000004
Stores programs to be transferred to.

Similarly, FIG. 9B shows the storage state of the program transferred by the CPU 54. $ As this storage area
The point that 04000 bytes are prepared and the leading $
The addresses up to 40 include the ID code and the software number as in the case of FIG. In addition,
This program has PROG RAM60 and PR
A program transferred to the OG RAM 68 is included.

Further, FIG. 7C shows a storage state of data required for polygon processing. In this case, as shown in the figure, a total capacity of $ 100,000 bytes is prepared, and the addresses up to $ 40 at the head include the ID code and software number corresponding to the polygon processing related data. Note that the data related to polygon processing includes the point RAM 72 and the line RA described above.
It includes various data transferred to M76.

Further, FIG. 9D shows the storage state of various data related to objects. As the storage area in this case, a capacity of $ 080000 bytes is prepared,
Addresses up to $ 40 include the ID code and software number corresponding to the object-related data. This object-related data includes various data transferred to the CG RAM 86 and the palette RAM 96 described above.

FIG. 12 is a diagram showing a concrete address map when the various programs and data shown in FIG. 11 are stored in the ROM 62.
The case where a program and data corresponding to each piece of simulation software are stored is shown.

As shown in FIGS. 12A and 12B, programs and data corresponding to software numbers 1, 2, 3, and 4 are stored in order from the head address.

If each of FIGS. 11A to 11D is stored in two ROMs (one ROM is associated with each of the lower and upper bits of 16-bit data), 1 A total of eight ROMs are required to store one simulation software. Therefore,
The whole of FIGS. 12A and 12B can be stored in 32 ROMs in total. In this way, by separately providing ROMs for storing each program or data type, even if any program or data is changed, only the corresponding ROM needs to be replaced. It becomes easy to change the program, etc. After the development and design of the simulation software is completed and the final program or data is determined, a large-capacity ROM is used by using only one set of upper bits and lower bits as shown in FIG. , (B) may be collectively stored.

Next, the ROM 6 having the above-mentioned stored contents
A specific operation when a program or data transfer from 2 to each RAM will be described.

In the present embodiment, when the simulator device is started up, the software that has been executed immediately before (for example, urban driving (1), urban driving (2), high speed driving, driving on driving school course) 4 simulation software for use in the ROM 62) is automatically read out and transferred to each RAM according to the procedure described below.

(3a) Program Transfer Operation to PROG RAM 48 When the program is preliminarily transferred to PROG RAM 48 at startup (3a-1 described later), the CPU 40
In the program execution unit 10 shown in FIG.
M46 is the transfer program / data specifying unit 11 and the search program storage unit 23, and the ROM 62 is the transfer source storage unit 1
2, the PROG RAM 48 corresponds to the transfer destination storage unit 18, respectively.

Further, at the time of the returning operation (3a-3 described later), P
When the program is transferred to the ROG RAM 48, the CPU 40 causes the program execution unit 10 shown in FIG.
In addition, the backup RAM 49 is stored in the transfer program / data specification unit 11, the ROM 62 is stored in the transfer source storage unit 12, and
The OG RAM 48 corresponds to the transfer destination storage unit 18 and the search program storage unit 23, respectively.

13 to 15 are diagrams showing an operation procedure when the CPU 40 transfers a program. FIG.
14 is an operation (preliminary transfer operation) procedure for transferring a program required for transfer, and FIG. 14 is an operation (corresponding table creation operation) procedure for associating a software number with an address where the program of this software is stored. However, FIG. 15 shows an operation (return operation) procedure for actually transferring the software program that was executed immediately before.

PROG will be described below with reference to these figures.
Details of the program transfer to the RAM 48 will be described.

(3a-1) Preliminary Transfer Operation First, the preliminary transfer operation will be described with reference to FIG.

The CPU 40 executes the search program stored in the BOOT ROM 46 to generate P
ROM 6 of the program to be transferred to ROG RAM 48
Search the storage address in 2. It should be noted that the program transferred in the preliminary transfer operation may include at least a program for creating a comparison table for actually transferring the program in a later-described return operation. Therefore, in this case, the software number can be any
The ID code pointing to the program executed by the PU 40 is searched.

Specifically, the CPU 40 which has executed the search program sets the search address in the head block of the ROM 62 (step 100). As shown in FIG. 12, each program or data is $ 040000.
Since it is stored in units of storage areas that are integer multiples of
If this $ 040000 is regarded as one block and only the data stored near the beginning of each block is looked at, it means that the ID code shown in FIG. It is possible to significantly reduce the search time as compared with the case where the search is performed in order.

Next, the CPU 40 determines whether or not there is an ID code of the program to be transferred by checking the head portion of the block whose head address is the set search address (step 101). The ID of the program you want to transfer near the set search address
If there is a code, the CPU 40 makes a positive determination,
The process moves to step 104 and subsequent steps, which will be described later.

If there is no ID code, the CPU 40 makes a negative decision and sets the search address to the start address of the next block (step 102). And C
The PU 40 determines whether or not all blocks have been searched (step 103). If all blocks have not been searched, a negative determination is made, and the processing from step 101 onward is repeated. If the processing (search) of step 101 is completed for all blocks, an affirmative decision is made in step 103, and the processing returns to step 100 to repeat the processing.

When the affirmative judgment is made in step 101 (when the ID code of the CPU 40 is present), the CPU 40 next jumps to the specific address Pa1 in the searched block and starts from this specific address. The stored program is executed (step 104). For example, the program jumps to the address $ 000040 shown in FIG. 11A and executes the program after this specific address stored in the ROM 62.

Next, the CPU 40 transfers the contents of the retrieved block to the PROG RAM 48 (step 10).
5). A transfer program for transferring the program itself to the PROG RAM 48 is included in the head portion of the program stored after the specific address in the ROM 62, and the address $ 0000 shown in FIG.
The entire program is transferred to the PROG RAM 48 by executing the program after 40.

Next, the CPU 40 jumps to the specific address Pa2 of the PROG RAM 48 for which the program transfer is completed (step 106), and the transfer is completed for PR.
The execution of the program stored in the OGRAM 48 is started (step 107). In this way, PROGR
The preliminary transfer operation is completed by performing the program transfer to the AM 48.

(3a-2) Comparison Table Creating Operation Next, the comparison table creating operation will be described with reference to FIG.

In the above-mentioned 107, the PROG RAM
CPU 4 which has started execution of the program transferred to 48
The value 0 again sets the search address in the first block of the ROM 62 (step 200).

Next, the CPU 40 determines whether or not there is the ID code of the CPU 40 itself by checking the head portion of the block whose head address is the set search address (step 201). Applicable ID
If there is a code, the CPU 40 makes a positive determination and W
The search address set in step 200 is written in the ORK RAM 47 (step 202). In addition, WOR
The storage area of the K RAM 47 is divided for each software number, and the software number and the search address are stored in association with each other.

When a negative determination is made in step 201 (when the ID code of the CPU 40 itself is not included in the block) or when the writing of the search address is completed in step 202, the next CPU
40 sets the search address to the start address of the next block (step 203). Then, the CPU 40
It is determined whether or not all blocks have been searched (step 204). If all blocks have not been searched, a negative determination is made, and the processing from step 201 onward is repeated. When the process (search) of step 201 is completed for all blocks, an affirmative decision is made in step 204, and the process returns to the next return operation. (3a-
3) Return Operation Next, the return operation will be described with reference to FIG.

First, the CPU 40 is a backup RAM.
The software number stored in 49 is read and inquired (step 300). As described above, the software number stored in the backup RAM 49 is the software number executed immediately before, and by knowing this number, the restoration operation becomes possible.

Next, the CPU 40 sets the address Pa3 of the ROM 62 corresponding to the inquired software number to WOR.
Search and read the K RAM 47 (step 30)
1). Then, the program jumps to the read address Pa3 (step 302) and executes the program of the corresponding software stored in the ROM 62 (the program of the software executed immediately before) (step 3).
03). As a result, the program of the corresponding software stored in the ROM 62 is transferred to the PROG RAM 48.

When the transfer of the program to the PROG RAM 48 is completed, the CPU 40 then proceeds to the PROG R
It jumps to the specific address Pa4 of the AM 48 and executes the program whose transfer has been completed (step 304).

Next, the CPU 40 writes the software number inquired in step 300 into the shared RAM 50 (step 305), and then I / O toward the CPU 54.
The reset signal output from the port 44 is released (step 306).

After that, the program and data are transferred by the CPU 54 (details will be described later), and the CPU 40
Waits for the transfer end signal from the CPU 54 (step 3
07), start the simulation operation.

(3b) PROG RAM 60 and PRO
Program Transfer Operation to G RAM 68 When the transfer operation by the CPU 40 described above is completed, FIG.
When the reset signal is released in step 306, the CPU 54 is activated and the transfer of the program and data is started.

When the CPU 54 is activated, the PROG RAM
When the program is preliminarily transferred to 60 (3b-1 to be described later), the CPU 54 causes the program execution unit 10 shown in FIG. 1, the BOOT ROM 58 causes the transfer program / data identification unit 11 and the search program storage unit 23, R
The OM 62 stores the PROG RAM 60 in the transfer source storage unit 12.
Corresponds to the transfer destination storage unit 18, respectively.

Further, at the time of the returning operation (3b-2 described later), P
When the program is transferred to the ROG RAM 60, the CPU 54 causes the program execution unit 10 shown in FIG.
In addition, the shared RAM 50 has the transfer program / data specifying unit 1
1, the ROM 62 in the transfer source storage unit 12, PROG R
The AM 60 corresponds to the transfer destination storage unit 18 and the search program storage unit 23, respectively.

16 and 17 are diagrams showing an operation procedure when the CPU 54 transfers a program. Figure 1
The operation procedure (preliminary transfer operation and comparison table creating operation) for associating the program required for transfer with 6 and the corresponding program are shown in FIG. The transfer operation (return operation) procedure is shown.

(3b-1) Preliminary Transfer Operation and Comparison Table Creation Operation First, the preliminary transfer operation and comparison table preparation operation will be described with reference to FIG.

When the reset signal is released, the CPU 54
By executing the search program stored in the BOOT ROM 58, the storage address in the ROM 62 of the program to be transferred to the PROG RAM 60 is searched.

Specifically, the CPU 54 executing the search program sets the search address in the head block of the ROM 62 (step 400), and checks the head portion of the block whose head address is the set search address. By doing so, it is determined whether or not there is an ID code of the program to be transferred (step 401). I of the program you want to transfer near the set search address
If there is a D code, the CPU 54 makes an affirmative decision, and proceeds to the processing of step 404 and subsequent steps which will be described later.

If there is no ID code, the CPU 54 makes a negative decision and sets the search address to the start address of the next block (step 402). And C
The PU 54 determines whether or not all blocks have been searched (step 403). If all blocks have not been searched, a negative determination is made, and the processing from step 401 onward is repeated. When the processing (search) of step 401 is completed for all blocks, an affirmative decision is made in step 403, and the processing returns to step 400 to repeat the processing.

When the affirmative judgment is made in step 401 (when the ID code of the CPU 54 is present), the CPU 54 next jumps to the specific address Pb1 in the searched block, and after this specific address. The stored program is executed (step 404).

Next, the CPU 54 transfers the contents of the retrieved block to the PROG RAM 60 (step 40
5) When the transfer is completed, the program jumps to the specific address Pb2 of the PROG RAM 60 (step 406) and PR
The execution of the program transferred to the OG RAM 60 is started. In this way, the preliminary transfer operation is completed.

Next, the CPU 54, which has started the execution of the program transferred to the PROG RAM 60, makes the WORK
It is checked whether or not the comparison table creation flag is set at a predetermined address of the RAM 59 (step 407). Here, since the flag has not been set yet, a negative judgment is made, and then the search address is set again in the head block of the ROM 62 (step 408), and the head portion of the block in which the set search address is the head address. Is checked to determine whether or not there is the ID code of the CPU 54 itself (step 409). If there is the corresponding ID code, the CPU 54 makes an affirmative decision and the WORK R
The search address set in step 408 is written in the AM 59 (step 410). In addition, WORK RAM
Reference numeral 59 corresponds to the WORK RAM 47 in the CPU board 24, the storage area is divided for each software number, and the software number and the search address are stored in association with each other.

When a negative determination is made in step 409 (when the ID code of the CPU 54 itself is not included in the block), or when the writing of the search address is completed in step 410, the next CPU
54 sets the search address to the start address of the next block (step 411). Then, the CPU 54
It is determined whether or not all blocks have been searched (step 412). If all blocks have not been searched, a negative determination is made, and the processing from step 409 onward is repeated. When the processing of step 401 has been completed for all blocks, an affirmative decision is made in step 412, and a comparison table created flag is set at a predetermined address in the WORK RAM 59 (step 413). In this way, the comparison table creating operation is completed and the next returning operation is performed.

(3b-2) Return Operation Next, the return operation will be described with reference to FIG.

First, the CPU 54 reads and inquires the software number stored in the shared RAM 50 (step 500). As described above, the shared RAM 50
The software number stored in is the software number that was executed immediately before, and by knowing this number, the recovery operation becomes possible.

Next, the CPU 54 sets the address Pb3 of the ROM 62 corresponding to the inquired software number to WOR.
Search and read K RAM 59 (step 50)
1). Then, the program jumps to the read address Pb3 (step 502) and executes the program of the corresponding software stored in the ROM 62 (the program of the software executed immediately before) (step 5).
03). As a result, the program of the corresponding software stored in the ROM 62 is transferred to the PROG RAM 60.

When the transfer of the program to the PROG RAM 60 is completed, the CPU 54 then proceeds to the PROG R
The program jumps to the specific address Pb4 of the AM 60 and starts execution of the transferred program (step 50).
5).

The PROG RAM 68 has a DSP 6
Although the operation program of 4 is transferred and stored,
In the present embodiment, the program transferred to the PROG RAM 60 includes it, and that part is stored as it is in P.
The data is transferred to the ROG RAM 68. Specifically, this is performed before step 800 described later, but since the DSP 64 operates in the same manner in any software, the same operating program for the DSP 64 is prepared in any software.
Therefore, this PROG RAM 68 is a ROM
It is also possible to store the operation program of the DSP 64 in advance.

(3c) CG RAM 86, palette RA
Data Transfer Operation to M96, Point RAM 72, Line RAM 76 When the program transfer operation by the CPU 54 is completed,
Next, data transfer to each RAM by the CPU 54 is performed.

CG RAM 86, palette RAM 9
6, when data is transferred to the point RAM 72 and the line RAM 76, the CPU 54 is the program execution unit 10 shown in FIG. 1, the shared RAM 50 is the transfer program / data identification unit 11, and the ROM 62 is the transfer source storage unit 12. CG RAM86, pallet RAM9
6, the point RAM 72 and the line RAM 76 correspond to the transfer destination storage unit 18, and the PROG RAM 60 corresponds to the transfer program storage unit 12 that stores the search program storage unit 23 and the transfer program 14.

18 to 20 are diagrams showing an operation procedure when the CPU 54 transfers data. FIG. 18 shows object-related data to be transferred (CG RAM8
6 and the data to be transferred to the palette RAM 96) and the address at which these data are stored (correspondence table creation operation 1) are shown in FIG. (Point R
20. The operation procedure (corresponding table creation operation 2) of associating the software numbers of the data transferred to the AM 72 and the line RAM 76) with the addresses at which these data are stored is shown in FIG. The operation procedure (return operation) for actually transferring the data is shown.

(3c-1) Comparison Table Creating Operation 1 First, the comparison table creating operation 1 will be described with reference to FIG.

The CPU 54 that executed the program transferred to the PROG RAM 60 again sets the search address to R
Set to the first block of OM62 (step 600),
By checking the head portion of the block in which the set search address is the head address, it is determined whether or not there is the ID code of the object data shown in FIG. 11 (d) (step 601). If there is the corresponding ID code, the CPU 54 makes an affirmative decision and the WORK R
The search address set in step 600 is written in the AM 59 (step 602).

When a negative determination is made in step 601 (when the ID code of the object data is not included in the block), or when the writing of the search address is completed in step 602, then C
The PU 54 sets the search address to the start address of the next block (step 603). And the CPU 54
Determines whether all blocks have been searched (step 604). If all blocks have not been searched, a negative determination is made, and the processing from step 601 onward is repeated. Also, step 601 for all blocks.
When the process of 1 is completed, an affirmative decision is made in step 604, and the process moves to the next comparison table creating operation 2.

(3c-2) Comparison Table Creating Operation 2 Next, the comparison table creating operation 1 will be described with reference to FIG.

First, the CPU 54 sets the search address again in the head block of the ROM 62 (step 70).
0), by checking the head portion of the block whose head address is the set search address,
It is judged whether or not there is an ID code of the polygon data shown in (c) (step 701). If there is the corresponding ID code, the CPU 54 makes an affirmative decision and the WORK
The search address set in step 700 is written in the RAM 59 (step 702).

When a negative determination is made in step 701 (when the ID code of the polygon data is not included in the block), or when the writing of the search address is completed in step 702, the CPU
54 sets the search address to the start address of the next block (step 703). Then, the CPU 54
It is determined whether or not all blocks have been searched (step 704). If all blocks have not been searched, a negative determination is made, and the processing from step 701 is repeated. When the processing of step 701 is completed for all blocks, an affirmative judgment is made in step 704, and the process returns to the next return operation.

(3c-3) Return Operation Next, the return operation will be described with reference to FIG.

First, the CPU 54 reads out and inquires the software number stored in the shared RAM 50 (step 800). As described above, the shared RAM 50
The software number stored in is the software number that was executed immediately before, and by knowing this number, various data restoration operations are possible.

Next, the CPU 54 searches the work RAM 59 for the address of the object-related data corresponding to the inquired software number and reads it (step 8).
01). Then, the object-related data included in the block specified by the read address is stored in the ROM.
62 read out from the CG RAM 86 and palette R
The data is distributed to the AM 96 and transferred (step 802). The palette RAM 96 is not directly connected to the CPU 54 via the address bus 54a and the data bus 54d, but is connected via the palette controller 94. Therefore, during data transfer, the CPU 54 writes data to the palette RAM 96 via the palette controller 94.

Next, the CPU 54 sets the address of the polygon-related data corresponding to the inquired software number to WO.
Search and read RK RAM 59 (step 80)
3). Then, the polygon-related data included in the block designated by the read address is read from the ROM 62, and the point RAM 72 and the line RAM 7 are read.
The data is divided into 6 and transferred (step 804). The point RAM 72 and the line RAM 76 are not directly connected to the CPU 54 via the address bus 54a and the data bus 54d, but are connected via the shared RAM 70 and the polygon processing circuit 74, respectively. Therefore, during data transfer, the CPU 54 writes data to the point RAM 72 and the line RAM 76 via the shared RAM 70 or the polygon processing circuit 74.

When the data transfer in step 804 is completed, the CPU 54 then sends a transfer completion signal to the shared RAM 50 (step 805, corresponding to step 307 in FIG. 15) and then starts the simulation operation.

As described above, in the simulator of this embodiment, a plurality of software programs and data are stored in the ROM 62, and the CPU board 24 stores the software programs and data to be executed at the time of startup or reset. Etc. are transferred to various boards.

(3d) Software change operation after program start of simulator When the software change instruction is issued from the I / O CPU board 38 through the communication IC 52, the CPU 40 receives the software number designated through the communication IC 52 and the I / O A reset signal is sent to the CPU 54 through the O port 44 and the process jumps to step 301. Then, as shown in the flow, the same operation as that at the time of the returning operation is performed, and the designated program is transferred to the PROG RAM 48.

In this case, the CPU 40 is provided in the program executing unit 10 shown in FIG. 1, and the I / O CPU board 38 and the communication IC 52 are provided in the transfer program / data specifying unit 11.
In addition, the ROM 62 is stored in the transfer source storage unit 12 in the PROG RA
M48 corresponds to the transfer destination storage unit 18 and the search program storage unit 23, respectively.

When the transfer operation by the CPU 40 is completed and the reset signal is released in step 306, the CPU 54 starts again from step 400 to perform the preliminary transfer operation, but the comparison table creation flag of step 407 is set. In the determination as to whether or not is set, the affirmative determination is made here because the comparison table creation flag is set in the previous process, and the process jumps to step 500 without creating the comparison table. After that, the same process as the previous process is performed as shown in the figure, and the PROG RAM 60, P
ROG RAM 68, point RAM 72, line RA
The designated program or data is transferred to the M76, the CG RAM 86, and the palette RAM 96.

In this way, it is possible to give a software change instruction from the I / O CPU board 38 at any time and replace the program and data in the transfer destination storage unit with the designated software. You will be able to play different simulation software.

As described above by taking the driving simulator as an example, since the ROM 62 stores programs and data of a plurality of software from the beginning, the software from outside the apparatus is changed every time the software to be executed is changed. No need to change clothing. Further, it is not necessary to store various kinds of software in different ROMs and replace the ROMs as needed, and the operation is not complicated. Further, as compared with a case where hardware is provided for each of a plurality of software, most of the hardware is shared and used, and there is no waste of circuits.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.

For example, in the driving simulator whose overall structure is shown in FIG. 2, a transfer program is included in the program to be transferred, and after the transfer program is transferred, the transferred program is executed and remains. However, the transfer program stored in the ROM 62 may always be used.

In the above-mentioned embodiment, the case where the program and data of the software executed immediately before is read and the simulation operation is restarted has been described as an example. However, the operation panel 11 in the I / O CPU board 38 is described.
The same can be considered when operating the ten-key pad 4 to change the software. In this case, the CPU 40
The software number input by operating the operation panel 114 is stored in the backup RAM 49, and
Program transfer is performed by executing the operation procedure shown in FIG.
Further, the CPU 54 executes the operation procedure shown in FIGS. 17 and 20 to transfer the program and data.

FIG. 2 shows a concrete example of the driving simulator.
It can also be applied to home or commercial game machines. For example, in the case of a home-use game machine, a plurality of game software programs may be stored in a ROM cassette and only the game software to be executed by the player may be transferred to the RAM of the game machine body. .

[0158]

As described above, according to the present invention, the software is executed after the data or the program corresponding to the plurality of software is transferred to the transfer destination storing means as necessary, so that the plurality of software is executed. It becomes unnecessary to operate the hardware when switching the software, and the complexity of the operation can be avoided. In addition, since a common transfer destination storage means is used when executing a plurality of software, it is possible to eliminate a redundant part of hardware and reduce circuit waste. Further, since the software is executed by using the transfer destination storing means, the circuit does not become unnecessarily complicated. Also, ROM for changing programs and data
Even if changes are made, it is convenient because they can be done collectively.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a program execution device of an embodiment to which the present invention is applied.

FIG. 2 is a diagram showing a specific configuration of the program execution device shown in FIG. 1 when the device is applied to a driving simulator.

FIG. 3 is a diagram showing a detailed configuration of a CPU board.

FIG. 4 is a diagram showing a detailed configuration of a CPU board.

FIG. 5 is a diagram showing a detailed configuration of a ROM board.

FIG. 6 is a diagram showing a specific example when a ROM is configured using a plurality of elements.

FIG. 7 is a diagram showing a detailed configuration of a DSP board.

FIG. 8 is a diagram showing a detailed configuration of a PGN board.

FIG. 9 is a diagram showing a detailed configuration of an OBJ board.

FIG. 10 is a diagram showing a detailed configuration of an I / O CPU board.

FIG. 11 is a diagram showing a storage state of a program or data stored in a ROM.

FIG. 12 is a diagram showing a specific address map when the various programs and data shown in FIG. 11 are stored in a ROM.

FIG. 13 is a diagram showing an operation procedure when a program is transferred.

FIG. 14 is a diagram showing an operation procedure when a program is transferred.

FIG. 15 is a diagram showing an operation procedure when a program is transferred.

FIG. 16 is a diagram showing an operation procedure when a program is transferred.

FIG. 17 is a diagram showing an operation procedure when a program is transferred.

FIG. 18 is a diagram showing an operation procedure when data is transferred.

FIG. 19 is a diagram showing an operation procedure when data is transferred.

FIG. 20 is a diagram showing an operation procedure when data is transferred.

FIG. 21 is a conceptual diagram when playing a plurality of types of games on a home-use game machine.

[Explanation of symbols]

 10 program execution unit 11 transfer program / data specifying unit 12 transfer source storage unit 18 transfer destination storage unit 23 search program storage unit 40, 54 CPU 46, 58, 66 BOOT ROM 48, 60, 68 PROG RAM 62 ROM 64 DSP 72 points RAM 76 Line RAM 86 CG RAM 96 Palette RAM

Claims (3)

[Claims] 1. A transfer source storage unit for storing a plurality of transferred programs or data and a transfer program for performing transfer processing, and the transferred programs or data being transferred and stored as transfer programs or data. Transfer destination storage means, and transfer program / data identification means for identifying one or more programs or data to be transferred from among the plurality of transferred programs or data stored in the transfer source storage means, Search program storage means for storing a search program for searching the storage area of the transfer source storage means for one or more programs or data to be transferred identified by the transfer program / data identification means, and the search program Execute the search program stored in the storage means Thus, the one or more programs or data to be transferred specified by the transfer program / data specifying means are searched, and the transfer program stored in the transfer source storage means is executed to search. Program executing means for transferring one or a plurality of programs or data to the transfer destination storing means, and performing a predetermined process using the transferred program or data stored in the transfer destination storing means. Characteristic program execution device. 2. The transfer program / data identification means according to claim 1, wherein one or a plurality of programs or data to be transferred are
The program execution means specifies the storage area of the transfer source storage means when executing the search program stored in the search program storage means. A program execution device, characterized in that the program or data to be transferred is searched by dividing the area into a plurality of areas and checking whether or not the predetermined identification code is included in a predetermined position of each divided area. 3. The transfer source storage unit according to claim 1, wherein the transfer source storage unit stores the transfer program in association with one or a plurality of programs specified and transferred by the transfer program / data specifying unit, The program execution means initially executes the transfer program stored in the transfer source storage means,
Transferring the transfer program together with the retrieved one or more programs, and executing the transfer program transferred to and stored in the transfer destination storing means after the transfer program is transferred. The program execution device is characterized in that the one or a plurality of retrieved programs whose transfer is not completed are transferred according to the above.