JPH073706Y2 - Demodulator - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a demodulator of a wireless device, and in particular, has an automatic frequency control (hereinafter referred to as AFC) function for stabilizing the operation against the frequency fluctuation. Regarding the demodulator.

[Prior art]

Conventionally, as this type of apparatus, there is one shown in FIG. In the figure, (1) is a high frequency amplifier for amplifying a received input signal, (2) is a local oscillator, and (3) is a high frequency amplifier (1).
, A mixer for mixing the output of the local oscillator (2) and converting it to an intermediate frequency, (4) a bandpass filter for extracting only the intermediate frequency component, (5) an intermediate frequency amplifier for amplifying the intermediate frequency component, (6) is a frequency discriminator, (7) is a DC amplifier that amplifies the output of the frequency discriminator (6), and (8) is a PL
A carrier regeneration circuit configured of an L loop for performing carrier regeneration, (9) a bit regeneration circuit for performing bit regeneration of demodulated data in the carrier regeneration process of the carrier regeneration circuit (8), and d from the carrier regeneration circuit (8) This is the demodulated data that is output.

Next, the operation will be described. The received high frequency signal is amplified by the high frequency amplifier (1), then mixed with the output of the local oscillator (2) in the mixer (3) and converted into an intermediate frequency. The signal converted to the intermediate frequency passes through the band pass filter (4), is sufficiently band-limited, and is then sufficiently amplified by the intermediate frequency amplifier (5). This amplified signal is demodulated by the frequency discriminator (6) and only the DC component is extracted. That is, in the output of the frequency discriminator (6), when the frequency of the signal converted to the intermediate frequency is higher than the specified frequency, a DC voltage appears in proportion to the difference, and when it is low, it is proportional to the difference in the same manner. A DC voltage opposite to the above appears.

Further, this DC voltage is amplified by the DC amplifier (7), and the oscillation frequency of the local oscillator (2) is controlled by this voltage. Therefore, even if the input reception frequency deviates from the regulation frequency or the oscillation frequency of the local oscillator (2) fluctuates, the signal converted into the intermediate frequency is kept at the prescribed frequency by the above operation.

On the other hand, the output of the intermediate frequency amplifier (5) is sent to the carrier wave regenerating circuit (8) and the bit regenerating circuit (9), which demodulates the data d.

[Problems to be solved by the device]

Since the conventional AFC circuit is configured as described above, in order to increase the frequency range in which data can be demodulated even when the input reception frequency of the carrier recovery circuit shifts, that is, the carrier range, It had the drawbacks of requiring an accurate frequency discriminator and complicating the local oscillator.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional ones, and by constructing an AFC circuit with digital elements and coupling the output to the carrier recovery circuit of the demodulator, the input reception frequency was shifted. In this case, or even if the oscillation frequency of the local oscillator fluctuates considerably, the signal converted to the intermediate frequency is kept at the specified frequency, and the demodulator provides a demodulator that can perform data demodulation in an optimum state. The purpose is to do.

[Means for Solving the Problems]

A mixer for mixing the received input signal and the local oscillation signal and converting it to an intermediate frequency, a band pass filter for extracting only the intermediate frequency component, an intermediate frequency amplifier for amplifying the intermediate frequency component, and an intermediate frequency amplifier connected to the intermediate frequency amplifier. A divider that divides the intermediate frequency, a clock oscillator that oscillates a reference clock, a delay circuit that is connected to the divider and delays the phase of the divider output according to the reference clock, and the divider. A phase comparator for comparing the phases of the frequency divider output and the delay circuit output, a low pass filter for filtering the phase comparator output, a carrier recovery circuit connected to the intermediate frequency amplifier, and the low pass filter. And a reference carrier wave oscillator of the carrier wave regenerating circuit controlled according to the output of the demodulator.

[Example of device]

The demodulator is for demodulating an original signal (data) that has been modulated from a modulated wave (high-frequency signal) that has been subjected to beam modulation.

In FIG. 2, the received high frequency signal is converted to an intermediate frequency and then input to the carrier wave regenerating circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block connection diagram showing a demodulator according to an embodiment of the present invention. In the figure, (1), (3)-
(5) and (9) are the same as the same reference numerals in FIG. (11) is a carrier wave regenerating circuit made of steel by a PLL loop to regenerate the carrier wave, and its details are shown in FIG.
(12) is a reference carrier oscillator (VCO) that oscillates a reference carrier for performing carrier recovery, (13) is a frequency divider that divides the output of the intermediate frequency amplifier (5), and (14) is a frequency divider ( 13)
A delay circuit that delays the output phase of (15) is a frequency divider (1
3) A phase comparator that compares the phase of the output with the output of the delay circuit (14), (16) a phase comparator (15) a low-pass filter that attenuates high frequency components in the output, and (17) a low-pass filter. A direct current amplifier (18) for amplifying the direct current component in the output of the pass filter (16) and a clock oscillator (18) for oscillating a reference clock supplied to the delay circuit (14).

In FIG. 2, (1), (3), (4),
(5), (9), (10) and (11) are components of a normal data demodulation circuit. (12), (13), (14), (1
Since 5), (16), (17), and (18) are the parts added in the present invention, this part will be described below.

The output of the amplifier (5) is an intermediate frequency component, and this frequency is fi (normal, that is, the frequency when there is no deviation).
Next, the output waveform of each block is shown.

In Fig. 3, the input frequency (amplifier output (5)) is the intermediate frequency.
When it is equal to fi, that is, the deviation of the input frequency is 0
4 shows the characteristics when the input frequency (amplifier output (5)) is lower than the intermediate frequency fi, that is, the characteristics when the deviation (shift) of the input frequency is negative. The fifth
Contrary to FIG. 4, the figure shows the characteristics when the input frequency is higher than the intermediate frequency fi. FIG. 6 is a diagram in which the characteristics shown in FIGS. 3 to 5 are rewritten as input frequency-output voltage characteristics,
It is a figure (DC amplifier (17) output) rewritten as a deviation.

That is, the bull-in range of the carrier recovery circuit is expanded by controlling (increasing or decreasing) the oscillation frequency of the reference carrier oscillator (12) according to the deviation of the input frequency.

Next, the operation will be described.

The oscillation frequency of the reference carrier oscillator (12) in Fig. 2 is 4 times the input frequency (in this case, the intermediate frequency 455KHz) = 1.82MH.
It is manufactured to be z.

The reason for quadrupling is that in-phase and 90 ° phase shift components are required in the carrier recovery circuit (11), and 4 times the frequency is used to make 90 ° phase shift components, that is, the process of dividing by 1/4. This is because a value shifted by 360 ° / 4 = 90 ° can be obtained at.

There is no deviation in the input intermediate frequency, 455 KHz (or deviation 1 KHz
If input within the range (about within), the carrier recovery circuit (11) enters a synchronized state (the reference carrier oscillator (12) follows the input intermediate frequency) and demodulates the modulated wave.

If the input intermediate frequency shifts by about 1 KHz or more, that is, the oscillation frequency of the reference carrier oscillator (12) (after 1/4 division) and 1
If a difference of about KHz or more occurs, the synchronization cannot be pulled in and the modulated wave cannot be demodulated normally.

According to the present invention, when the input intermediate frequency shifts by 1 KHz, the oscillation frequency of the reference carrier oscillator (12) is also 1 KHz after frequency division (4 KHz before frequency division).
It has a structure of automatic frequency control (AFC) that shifts.

That is, when the input intermediate frequency rises by 1 KHz (to 456 KHz), the automatic frequency control circuit operates and sets the oscillation frequency of the reference carrier wave oscillator (12) to 456 KHz × 4 and always oscillates the input intermediate frequency and the reference carrier wave oscillator (12). Control so that the frequency difference (after 1/4 frequency division) is within 1 KHz.

The same applies when the input intermediate frequency is lowered.

The intermediate frequency component of the output of the intermediate frequency amplifier (5) is the frequency divider (1
It is divided by N by 3). Next, the output of the frequency divider (13) is connected to the delay circuit (14), where a predetermined amount of delay is performed by the reference clock of the clock oscillator (18).
The output of the delay circuit (14) is phase-compared with the output of the frequency divider (13) in the phase comparator (15), and a DC voltage proportional to the phase difference between them is output to the output of the low-pass filter (16). appear.

That is, when the oscillation frequency of the reference carrier wave oscillator (VCO) (12) is equal to the reception intermediate frequency (output of the intermediate frequency amplifier (5)), the output of the low-pass filter (16) has a voltage showing a median value. When the reception intermediate frequency is higher than the oscillation frequency of the reference carrier oscillator (VCO) (12), a positive voltage (or negative voltage) that is proportional to the frequency difference appears as the median value as the reference value, and an opposite frequency difference occurs. In that case, a negative voltage (or positive voltage) appears in the same manner. Further low-pass filter (1
6) The output DC voltage is amplified by the DC amplifier (17), and this voltage is applied to the reference carrier oscillator (VCO) (12) and becomes its control voltage, which controls the oscillation frequency.

The feature of this AFC circuit is that it does not form a negative feedback loop like the conventional device, but has a feedforward type configuration. That is, in this AFC circuit, the intermediate frequency amplifier (5)
If the output frequency fluctuates, the oscillation frequency of the reference carrier oscillator (12) is controlled so as to follow the change, and as a result, demodulation is possible even if the input reception frequency or the local oscillation frequency deviates from the regular frequency. This will be possible and the carrier range of the carrier recovery circuit (11) will be expanded.

To operate as above, the reference carrier oscillator (1
It is necessary to detect the frequency difference between the oscillation frequency in 2) and the reception intermediate frequency.

The reference for detecting this frequency difference is the clock oscillator (18) in FIG. 2, which is usually composed of a crystal oscillator.

The detection accuracy is the accuracy of the oscillator times the number of delay stages in the delay circuit, and the number of delay stages is about 20 to 50.

The delay circuit (14) in FIG. 2 expands the frequency error by the number of stages described above, and enhances the sensitivity of the phase comparator (15). This delay circuit (14) can be easily constructed by a digital circuit.

Configuration of carrier wave regeneration circuit (11) and reference carrier wave oscillator (12)
The connection with is shown in FIG.

In the reference carrier oscillator (12), the input from the LOOP FIL in the carrier generation circuit (11) and the DC amplifier (17) are illustrated.
And the input from are supplied to the adder, the oscillation frequency is changed by the output of the adder, and the oscillation frequency is supplied to the carrier generation circuit (11).

The conventional system (Fig. 1) is a system that suppresses frequency fluctuations in the circuit before the intermediate frequency amplifier (5), and there is no deviation (deviation) in the frequency input to the carrier generation circuit (8) or within 1 KHz. is there.

In the present invention (Fig. 2), the output of the intermediate frequency amplifier (5), that is, the input of the carrier recovery circuit (11) has a frequency fluctuation, and even if the circuit after the carrier recovery circuit (AFC circuit) has a frequency fluctuation. This is a method that can be demodulated.

Since the conventional method (Fig. 1) is an analog circuit and requires a large-sized (difficult to miniaturize) and high-precision frequency discriminator, it is expensive, whereas the circuit of the present invention is a digital circuit and thus can be integrated into an IC. Because it is possible, it can be made smaller and at a lower price.

Normally, the bull-in range of the carrier recovery circuit is at most 1 KHz, and if the input frequency (intermediate frequency) shifts by 1 KHz or more,
Loop no longer locks (no longer pulls in). Therefore, in this embodiment, by adding the AFC as described above, the loop is locked even when the deviation is several KHz, and the data can be stably reproduced.

Since this AFC circuit was constructed using digital elements, the carrier recovery circuit and the bit recovery circuit are included.
It can be made into a chip IC, can be easily downsized, and has the effects of simplifying maintenance, improving reliability, and reducing costs.

In the above embodiment, the AF in which the output is coupled to the data demodulator is used.
Although the C circuit has been described, the present invention can be applied to an analog demodulator that demodulates a modulated signal signal component from a received signal by using a PLL circuit, and has the same effect as the above embodiment.

[Effect of device]

As described above, according to the present invention, the AFC circuit is composed of digital elements and the feed-forward type,
Since the output is connected to the carrier recovery circuit of the demodulator, the capacities of the demodulator can be expanded and the circuit can be downsized, the reliability can be improved, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a conventional demodulator, and FIG. 2 is a block diagram showing an AFC circuit according to an embodiment of the present invention. Fig. 3 shows the characteristics when the deviation (deviation) of the input frequency is 0, Fig. 4 shows the characteristics when the deviation of the input frequency is negative, and Fig. 5 shows the characteristics when the input frequency is from the intermediate frequency fi. Fig. 6 is a diagram showing the characteristics at a high time, Fig. 6 is a diagram in which the characteristics described in Figs. 3 to 5 are rewritten into the input frequency-output voltage characteristic, and Fig. 7 is the characteristic of Fig. 6 is frequency deviation-output. FIG. 8 in which voltage deviation is rewritten, and FIG. 8 are views showing the details of the carrier recovery circuit (11). (11) is a carrier recovery circuit, (12) is a reference carrier oscillator,
(13) is a frequency divider, (14) is a delay circuit, (15) is a phase comparator, and (16) is a low-pass filter. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-175346 (JP, A) JP-A-57-72441 (JP, A) JP-A-56-125144 (JP, A) JP-A-56- 2769 (JP, A) JP 55-134532 (JP, A) JP 57-135556 (JP, A)

Claims (1)

[Scope of utility model registration request] 1. A mixer that mixes a received input signal and a local oscillation signal and converts them into an intermediate frequency, a bandpass filter that extracts only an intermediate frequency component, an intermediate frequency amplifier that amplifies the intermediate frequency component, and the above intermediate A frequency divider connected to the frequency amplifier to divide the intermediate frequency, a clock oscillator oscillating a reference clock, and a delay connected to the frequency divider to delay the phase of the frequency divider output according to the reference clock. A circuit, a phase comparator for comparing the phases of the frequency divider output and the delay circuit output, a low-pass filter for filtering the phase comparator output, and a carrier recovery circuit connected to the intermediate frequency amplifier. A demodulator, comprising: a reference carrier wave oscillator of the carrier wave regenerating circuit controlled according to an output of the low pass filter.