JPH0737372Y2 - Signal synthesis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Purpose of the invention [Industrial field of application] The present invention is designed to clamp a plurality of input signals with corresponding clamp circuits and then switch corresponding switch circuits to combine them. More specifically, the present invention relates to a signal synthesizing circuit that serves as a synthetic signal, and in particular, amplifies the difference between a set of two sampling signals obtained by sampling a plurality of input signals at two different timings, and applies the amplified differences to corresponding clamp circuits. Thus, the present invention relates to a signal synthesizing circuit which suppresses the variation of the reference level of the synthesized signal due to the variation of the reference level of a plurality of input signals.

[Prior Art] Conventionally, as this kind of signal synthesizing circuit, as in the signal synthesizing circuit 10 shown in FIG. 3, a plurality of input signals (here, an odd output signal S _O and an even output signal S _{O of the} detector 20 are used. _E and) are respectively amplified by amplifier circuits 11A and 11B, and then clamped appropriately by clamp circuits 14A and 14B according to timing pulse S _C generated by timing pulse generator circuit 19A, and generated by timing pulse generator circuit 19A. It has been proposed that the combined signal S be formed by combining the two by the switch circuits 15A and 15B that alternately operate according to the timing pulses S _A and S _B having a phase difference of π.

[Problems to be Solved] However, in the conventional signal synthesizing circuit 10 , (i) a plurality of input signals (that is, the odd output signal S _O and the even output signal S _{E of the} detector 20 ) are directly amplified and then directly clamped. 14A, 14B
Since the multiple input signals (ie, the odd output signal S _O and the even output signal S _{E of the} detector 20 ) change rapidly, the multiple input signals (ie, the odd output signal S _O and the odd output signal S _O There is a drawback that the reference level of the even output signal S _E ) fluctuates and the reference level of the composite signal S also fluctuates and becomes unstable, and (ii) a plurality of input signals (that is, an odd number of detectors 20 ). Output signal S _O and even output signal
Switch circuit 15A, 15B after amplifying and clamping S _E ).
Since it was immediately synthesized via the switch circuit 15A, 15
The cycle of the timing pulses S _A and S _B for operating B must be matched with the operation cycle of the detector 20 (that is, the cycle of the odd output signal S _O and the even output signal S _E ), which simplifies the circuit configuration. In addition, (iii) the combined signal S by the switch circuits 15A and 15B is simply the buffer circuit 1
Since it was output only via 7, switch circuit 15
There is a drawback that glitches are likely to occur in the composite signal S corresponding to the switching times of A and 15B.

Therefore, in order to eliminate these drawbacks, the present invention amplifies a difference between a pair of sampling signals obtained by sampling a plurality of input signals at two different timings, and respectively clamps the corresponding clamp circuits. To suppress the fluctuation of the reference level of the combined signal due to the fluctuation of the reference level of a plurality of input signals by providing the signal combining circuit.

(2) Configuration of the Invention [Means for Solving the Problem] The means for solving the problem provided by the present invention is, “Clamping a plurality of input signals by corresponding clamp circuits and then switching the corresponding switch circuits to combine them. In the signal synthesizing circuit which becomes a synthetic signal by doing so, (a) a plurality of input signals are sampled and held at two different timings, respectively, and held as a set of two sampling signals. Sample-hold circuits (12A ₁ , 12A ₂ ; 12B ₁ , 12B ₂ ) and (b) a plurality of sample-hold circuits (12A ₁ , 12A ₂ ; 12)
B ₁ , 12B ₂ ) output terminals of each pair are connected to a non-inverting input terminal and an inverting input terminal, and the output terminals are connected to the corresponding input terminals of the clamp circuit. And a plurality of differential amplifiers (13A; 13B) for amplifying the differences between the sampling signals and applying the amplified differences to the corresponding clamp circuits.

[Operation] In the signal synthesizing circuit according to the present invention, a plurality of input signals are clamped by the corresponding clamp circuits, and then the corresponding switch circuits are switched to synthesize each other, as clearly shown in the above [Solution to Problem]. (A) a plurality of input signals are sampled and held at two different timings, respectively, and are output as a set of two sampling signals. A plurality of sample and hold circuits, (b)
The non-inverting input terminal and the inverting input terminal are connected to the output terminals of the plurality of sample-hold circuits for each group, and the output terminals are connected to the input terminals of the corresponding clamp circuits. Since a plurality of differential amplifiers are provided for amplifying the differences between the signals and then applying the amplified differences to the corresponding clamp circuits, (i) a plurality of input signals are changed at a high speed, and a reference of a composite signal is provided. Even if the level fluctuates, it has the effect of suppressing it, and (ii) has the effect of simplifying the circuit configuration by making the cycle of the timing pulse larger than the cycle of a plurality of input signals.

[Embodiment] Next, a signal synthesizing circuit according to the present invention will be specifically described with reference to the accompanying drawings. However, the embodiments described below are provided for facilitating or facilitating the understanding of the present invention, and not for limiting the present invention. In other words, each element disclosed in the embodiments described below includes all design changes and equivalent replacements within the spirit and technical scope of the present invention.

(Explanation of the attached drawings) FIG. 1 is a circuit diagram showing an embodiment of a signal synthesizing circuit according to the present invention.
The case where the odd output signal S _O and the even output signal S _E output from 20 are combined with each other to form a combined signal S is shown.

FIG. 2 is a time chart diagram for explaining the operation of the embodiment shown in FIG.

(Structure of Embodiment) First, referring to FIGS. 1 and 2, the present invention will be described.
The detailed configuration of one embodiment of the signal synthesis circuit
explain. Here, to keep the explanation concise,
Input signal is a detector20Odd output signal S output from_OAnd
And even output signal S_EWill be described only.Ten Is a signal combining circuit according to the present invention, which is a detector20
One output end (called "odd output end") Q_OThe input end is connected to
Continued and strange output signal S_OOutput processing for processing
circuit10AAnd the detector20The other output end (of "even output end")
Say) Q_EThe input terminal is connected to the even output signal S_EHandle
Output processing circuit for10BAnd odd output processing circuit10Aof
Output terminal and even output processing circuit10BConnected to the output end of
Odd output processing circuit10AAnd even output processing circuit10BProcessed by
Odd output processed signal S_O ^*And even output processed signal S_E ^*Synthesize
Signal combining circuit for outputting as a combined signal S10C
And odd output processing circuit10A, Even output processing circuit10BAnd detection
vessel20Connected to the odd output processing circuit10A, Accidental
Force processing circuit10BAnd detector20Control the operation timing of
Control circuit for10DIt has and.

The odd output processing circuit 10A has an input terminal connected to the odd output terminal Q _O of the detector 20 , and an amplification circuit 11A for amplifying the odd output signal S _O to obtain the odd output amplified signal S _O ¹ and an amplification circuit 11A. The input terminal is connected to the output terminal of the circuit 11A, and the odd output amplified signal S _O ¹ is sampled at two different timings, held for a predetermined time, and output as sampling signals S _O ¹¹ and S _O ^12. A pair of sample and hold circuits 12A ₁ ,
The non-inverting input terminal and the inverting input terminal are connected to the output terminals of 12A ₂ and the sample and hold circuits 12A ₁ and 12A ₂ , respectively, and the output signals of the sample and hold circuits 12A ₁ and 12A ₂ (that is, the sampling signal S _O ¹¹ , S _O ¹² ), the difference S _O ¹¹ −
The differential amplifier 13A for obtaining and amplifying S _O ¹² to obtain the differential amplified signal S _O ^2, and the input end of the differential amplifier 13A are connected to the output end of the differential amplifier 13A. The clamp circuit 14A for appropriately clamping the differential amplified signal S _O ² to obtain the clamp signal S _O ³ and the input end of the clamp circuit 14A are connected to the output end of the clamp circuit 14A. Signal S _O ³ ) output odd processed signal S
_{It includes} a switch circuit 15A for setting _O ^* . The switch circuit 15A may be formed by a known circuit element such as a field effect transistor.

偶出force processing circuit 10B includes an amplifier circuit 11B for the偶出force amplified signal S _E ¹ input to偶出force end Q _E is amplifies the偶出force signal S _E is connected to the detector 20, amplified The input terminal is connected to the output terminal of the circuit 11B, and the even output amplified signal S _E ¹ is sampled at two different timings, held for a predetermined time, and output as sampling signals S _E ¹¹ and S _E ^12. A pair of sample and hold circuits 12B ₁ ,
The non-inverting input terminal and the inverting input terminal are connected to the output terminals of 12B ₂ and the sample and hold circuits 12B ₁ and 12B ₂ , respectively, and the output signals of the sample and hold circuits 12B ₁ and 12B ₂ are the sampling signals S _E ¹¹ , S _E ¹² ), the difference S _E ¹¹ −
A differential amplifier 13B for obtaining and amplifying S _E ¹² to obtain a differential amplified signal S _E ² and an input end of the differential amplifier 13B are connected to an output end of the differential amplifier 13B. A clamp circuit 14B for appropriately clamping the differential amplified signal S _E ² ) to obtain a clamp signal S _E ³ and an input end connected to the output end of the clamp circuit 14B, that is, the output signal of the clamp circuit 14B (that is, It includes a switch circuit 15B for making the clamp signal S _E ³ ) an even output processed signal S _E ^* .
The switch circuit 15B may be formed by a known circuit element such as a field effect transistor.

The output combining circuit 10C has an input end connected to the output end of the switch circuit 15A included in the odd output processing circuit 10A and the output end of the switch circuit 15B included in the even output processing circuit 10B. , 15B (that is, the odd output processing circuit 10A and the even output processing circuit 10B ) hold the output signals (that is, the odd output processing signal S _O ^* and the even output processing signal S _E ^* ) for a predetermined time, and thereby switch circuits 15A and 15B. (That is, the odd output processing circuit 10A and the even output processing circuit 10B ) (that is, the odd output processing signal S _O ^* and the even output processing signal S
A hold circuit 16 for removing a glitch from the combined signal S of _E ^* ), an input terminal connected to the output terminal of the hold circuit 16, and an output terminal connected to a subsequent circuit (not shown). It includes a buffer circuit 17 for facilitating the transmission of the combined signal S to the subsequent circuit.

Control circuit 10D includes an oscillator 18 for outputting an oscillation output S _F having a predetermined frequency, the input end connected and the first output terminal to the output terminal of the oscillator 18 is a sample and hold circuit
The second output end is connected to the control ends of 12A ₁ and 12B _{1 and} the control end of the switch circuit 15A, and has a second output end.
A _2, control end of the 12B ₂ and connected to a control terminal of the switch circuit 15B and the third output terminal clamp circuit 14A, the first to third timing from the connected and the oscillation output S _F to a control terminal of 14B After creating the pulses S _A , S _B , and S _C , the first timing pulse S _{A is applied} to the control ends of the sample and hold circuits 12A ₁ and 12B _{1 and} the control end of the switch circuit 15A, and the second timing pulse S A is applied. _B is the sample and hold circuit 12A ₂ ,
Timing pulse generation circuit for giving the control end of 12B _{2 and} the control end of the switch circuit 15B and giving the third timing pulse S _C to the control ends of the clamp circuits 14A, 14B
It has 19A and.

The control circuit 10D further has an input end connected to the output end of the oscillator 18 and an output end connected to the control end Q _C of the detector 20 to generate the drive signal S _D from the oscillation output S _F. A drive circuit 19B for supplying the detector 20 is provided.

(Operation of Embodiment) Further, the operation of one embodiment of the signal synthesizing circuit according to the present invention will be described in detail with reference to FIGS. 1 and 2.

In the signal synthesizing circuit 10 according to the present invention, the timing pulse generating circuit 19A included in the control circuit 10D creates timing pulses S _A , S _B , and S _C from the oscillation output S _F of the oscillator 18 to generate an odd output processing circuit. 10A and the even output processing circuit 10B , and the oscillator in the drive circuit 19B included in the control circuit 10D.
The drive signal S _D is generated from the oscillation output S _{F of} 18 and is given to the control terminal Q _C of the detector 20 .

Detector 20 in accordance with the drive signal S _D, and outputs the odd output signal S _O and偶出force signal S _E alternately from the odd output terminal Q _O and偶出force end Q _E.

The odd output signal S _O of the detector 20 is appropriately amplified by the amplification circuit 11A included in the odd output processing circuit 10A to be an odd output amplified signal S _O ¹ . The odd output amplified signal S _O ¹ is given to the pair of sample and hold circuits 12A ₁ and 12A ₂ and two different signals are generated according to the timing pulses S _A and S _B given from the timing pulse generation circuit 19A. It is sampled at the timing and held for a predetermined time.

The outputs of the sample hold circuits 12A ₁ and 12A ₂ (that is, the sampling signals S _O ¹¹ and S _O ¹² ) are given to the non-inverting output terminal and the inverting output terminal of the differential amplifier 13A, and their difference S _O
¹¹ −S _O ¹² is appropriately amplified and output.

The output of the differential amplifier 13B (that is, the differential amplified signal S _O ² ) is
It is given to the clamp circuit 14A and is appropriately clamped according to the timing pulse S _C given from the timing pulse generation circuit 19A.

Output of clamp circuit 14A (ie clamp signal S _O ³ )
Is given to the switch circuit 15A, and is passed through when the switch circuit 15A is turned on in response to the timing pulse S _A to be an odd output processing signal S _O ^* , which is given to the output combining circuit 10C. .

On the other hand, the even output signal S _E of the detector 20 is appropriately amplified by the amplifier circuit 11B included in the even output processing circuit 10B to be an even output amplified signal S _E ¹ . Even output amplified signal S
_E ¹ is given to a pair of sample and hold circuits 12B ₁ and 12B ₂ and is sampled at two different timings in accordance with the timing pulses S _A and S _B given from the timing pulse generation circuit 19B. Holds only for hours.

The outputs of the sample hold circuits 12B ₁ and 12B ₂ (that is, the sampling signals S _E ¹¹ and S _E ¹² ) are given to the non-inverting output terminal and the inverting output terminal of the differential amplifier 13B, and the difference S _E
¹¹ −S _E ¹² is appropriately amplified and output.

The output of the differential amplifier 13B (that is, the differential amplified signal S _E ² ) is
It is given to the clamp circuit 14B, and is appropriately clamped according to the timing pulse S _C given from the timing pulse generation circuit 19B.

Output of clamp circuit 14B (ie clamp signal S _E ³ )
Is given to the switch circuit 15B and is passed through when the switch circuit 15B is turned on in response to the timing pulse S _A to be an even output processing signal S _E ^* , which is given to the output combining circuit 10C. .

In the output synthesis circuit 10C , the odd output processing signal S _O ^* given by the odd output processing circuit 10A and the even output processing signal S _E ^* given by the even output processing circuit 10B are held by the hold circuit 16 for a predetermined time. After that, it is output as a composite signal S via the buffer circuit 17. Therefore, in the combined signal S, it is possible to avoid the occurrence of glitches in the combined portion of the odd output processed signal S _O ^* and the even output processed signal S _E ^* (and thus in the portion corresponding to the switching time of the switch circuits 15A and 15B). .

(Summary of Embodiments) The signal synthesizing circuit 10 according to the present invention includes an odd output signal S _O and an even output signal S _{E of the} detector 20 , which are provided as a plurality of input signals, respectively. After being clamped by 14A, 14B, the first and second switch circuits 15A, 15B are switched and synthesized with each other to form a synthesized signal S.
(A) A first sample-hold circuit 12A ₁ for sampling and holding the odd output signal S _O at a first timing and outputting it as a first sampling signal S _O ¹¹ , and (b) an odd output signal S _O For sampling and holding at a second timing and outputting as a second sampling signal S _O ¹²
Sample hold circuit 12A ₂ and (c) the output terminals of the first and second sample hold circuits 12A ₁ and 12A ₂ are connected to the non-inverting input terminal and the inverting input terminal, respectively, and the output terminal is the first clamp circuit. A first differential amplifier 13A which is connected to the input terminal of 14A and amplifies the difference between the first and second sampling signals S _O ¹¹ and S _O ¹² and then applies the first differential amplifier 13A to the first clamp circuit 14A. , (D) a third sample hold circuit 12B ₁ for sampling and holding the even output signal S _E at the first timing and outputting it as the third sampling signal S _E ¹¹ ,
(E) a fourth sample and hold circuit 12B ₂ for sampling and holding the even output signal S _E at the second timing and outputting it as a fourth sampling signal S _E ¹² , and (f) a third sample and hold circuit 12B ₂ .
The output terminals of the fourth sample hold circuits 12B ₁ and 12B ₂ are connected to the non-inverting input terminal and the inverting input terminal, respectively, and the output terminals are connected to the input terminal of the second clamp circuit 14B. since a second differential amplifier 13B for providing a second clamp circuit 14B After amplifying the difference between the sampling signals S _E, ^11, S _E ¹² of, (i) detector 2
Even if the odd output signal S _O and the even output signal S _{E of 0} are changed at high speed and the reference level of the composite signal S is changed, it can be suppressed (that is, noise can be suppressed), and ( ii) The circuit configuration can be simplified by making the cycle of the timing pulse larger than the cycle of the odd output signal S _O and the even output signal S _E of the detector 20 .

The signal synthesizing circuit 10 according to the present invention further includes an odd output processing signal S _O ^* and an even output processing signal by connecting the output terminals of the first and second switch circuits 15A and 15B to the input terminal of the hold circuit 16. Since S _E ^* is held for a predetermined time when it is combined, it is possible to remove the glitch generated in the combined signal S corresponding to the switching time of the first and second switch circuits 15A and 15B.

(3) Effects of the Invention As is clear from the above, the signal synthesizing circuit according to the present invention clamps a plurality of input signals with the corresponding clamp circuits as described in the above [Solution to Problem]. A signal synthesizing circuit configured as a synthetic signal by switching to a corresponding switch circuit and synthesizing each other, and in particular, (a) a plurality of input signals are sampled and held at two different timings, and a set of two sampling signals is held. A set of two sample-hold circuits for outputting as signals, and (b) a non-inverting input terminal and an inverting input terminal are connected to the output terminals of the plurality of sample-hold circuits, respectively, and output terminals Are respectively connected to the input terminals of the corresponding clamp circuits, and after amplifying the difference between the sampling signals of two pairs, respectively, Since it is provided with a plurality of differential amplifiers for supplying to the corresponding clamp circuit, (i) it is suppressed even if a plurality of input signals change at high speed and the reference level of the combined signal changes. This has the effect of enabling it, and (ii) has the effect of making the cycle of the timing pulse larger than the cycle of a plurality of input signals and simplifying the circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a signal synthesizing circuit according to the present invention, FIG. 2 is a time chart diagram for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a conventional example. It is a circuit diagram for. 10 …… Signal synthesis circuit 10A …… Odd output processing circuit 11A …… Amplification circuit 12A ₁ , 12A ₂ …… Sample hold circuit 13A …… Differential amplifier 14A …… Clamp circuit 15A …… Switch circuit 10B …… Even output processing Circuit 11B …… Amplifier circuit 12B ₁ , 12B ₂ …… Sample hold circuit 13B …… Differential amplifier 14B …… Clamp circuit 15B …… Switch circuit 10C …… Output synthesis circuit 16 …… Hold circuit 17 …… Buffer circuit 10D … … Control circuit 18 …… Oscillator 19A …… Timing pulse generator 19B …… Drive circuit 20 …… Detector Q _O …… Odd output Q _E …… Even output Q _C …… Control

Claims (1)

[Scope of utility model registration request] 1. A signal synthesizing circuit, wherein a plurality of input signals are clamped by respective corresponding clamp circuits, and then corresponding switch circuits are switched to synthesize each other as a synthesized signal. A plurality of sample and hold circuits (12A ₁ , 12A ₂ ; 12B ₁ , 12B ₂ ) for sampling and holding at two different timings and outputting as a set of two sampling signals, and (b) a plurality of Sample and hold circuit (12A ₁ , 12A ₂ ; 12
B ₁ , 12B ₂ ) output terminals of each pair are connected to a non-inverting input terminal and an inverting input terminal, and the output terminals are connected to the corresponding input terminals of the clamp circuit. And a plurality of differential amplifiers (13A; 13B) for amplifying the differences between the sampling signals and then applying the amplified differences to the corresponding clamp circuits.