JPH073756B2 - Dynamic semiconductor memory device - Google Patents

Description

The present invention relates to a dynamic semiconductor memory device having a high yield.

[Prior Art] In recent years, in order to meet the demand for microelectronics in industrial and consumer equipment, VLSI (Very Large Scale Integrated Circuit), which is a larger scale LSI (Large Scale Integrated Circuit), has been developed and put to commercial use. Has been done.

In such a VLSI, it is necessary to integrate millions of devices on one silicon chip, and therefore, the minimum size is about 1
A fine processing technology of μm is used. Therefore, foreign matters having a particle size of 1 μm or less and residues of various materials for processing, which have not been a problem in the past, adversely affect the device, and the yield rate of non-defective products, that is, the yield is significantly reduced.

Therefore, in order to improve the yield, redundant circuit technology is generally adopted. This is to provide a spare (spare) word line or bit line on the same chip and replace a defective cell in the memory cell array with a spare line in word line or bit line units. is there. As a result, most of the chips that should be excluded as defective products are relieved by adopting such a redundant circuit, so that the yield can be greatly improved.

FIG. 3 is a block diagram showing a conventional 1M (mega) bit dynamic RAM (Random Access Memory) having a redundant circuit. In this figure, a portion related to the redundant circuit is omitted for simplification, but this will be described later.

Referring to FIG. 3, the dynamic RAM has a memory array 1 to 4 divided into four blocks and a word for generating a signal W _DS for driving a word line included in each memory array 1 to 4. A line drive signal generation circuit 51,
A word line boost circuit 10 for boosting the word line drive signal W _DS . The word line drive signal generation circuit 51
It is connected to receive a ▲ ▼ (row address strobe) signal through the RAS buffer 52. Each memory array 1 to 4, for example memory array 1, has a row decoder 1a.
, The sense amplifier 1b and the column decoder 1c are connected.

This dynamic RAM is accessed to the memory arrays 1 to 4 of four blocks in a 4-bit high-speed serial access mode called a nibble mode.

Next, the operation will be described.

In general, the dynamic RAM receives row and column address signals in a time division manner through terminals A0 to A9. First, the respective address signals are ▲ ▼ signal and ▲
▼ (Column address strobe) signal is input at the falling edge timing. Then, one of the four row decoders is selected by the row address signal, and the boosted word line drive signal W _DB activates the word line. On the other hand, one of the four column decoders is selected by the column address signal, and the bit line is selected. Thereby, for example, the signal stored in the memory cell is applied to the bit line during the read operation.

FIG. 4 is a circuit diagram showing an equivalent circuit of one conventional memory cell.

Referring to FIG. 4, memory cell MC includes a switching transistor Q _M connected to word line WL and bit line BL, and a capacitor C _S. A signal is stored by applying a high level (1) or low level (0) voltage to this capacitor C _S.

A certain level of voltage V _CP is applied to one electrode of the capacitor C _S.
Is given. The transistor Q _M for activating the word line WL is turned on. Thus, charge stored in the capacitor C _S is applied to the bit line BL brought to a floating state. Here, the stray capacitance C _BL of the bit line _BL
Is about 10 times as large as the capacitance of the capacitor C _S, a slight potential change of several hundred mV appears on the bit line BL.

Therefore, as shown in FIG. 3, this potential change is applied to the read / write I / O line after being amplified by the sense amplifier. Further, this signal is further amplified by the preamplifier.

Through the series of operations described above, 4-bit signals of the memory cells MC1 to MC4 designated in the memory arrays 1 to 4 are simultaneously applied to the preamplifiers 21 to 24 through the I / O lines.

In the nibble mode, the nibble decoder 58 operates as a shift register and sequentially transfers these 4-bit signals to the output buffer 57 at high speed by toggling the signal. On the other hand, in the normal mode, the nibble decoder 58 is
Acts as a decoder to decode the top row and column address signals RA9 and CA9, and addresses address signals RA9 and C
In response to A9, a 1-bit signal from the 4-bit signal is transferred to the output buffer 57.

On the other hand, in the write operation, conversely, the input data input via the input buffer 56 is written into the memory cells MC1 to MC4 via the I / O line.

Next, the word line boost circuit will be described.

Referring again to FIG. 4, when the word line WL changes to high level, the transistor Q _M turns on. If this high level is the power supply voltage level Vcc, the high level storage level is lost by the threshold voltage V _TH of the transistor Q _M.
This loss rate is usually around 20%, and malfunction does not occur immediately. However, for example, when the power supply voltage level is low, there is a problem that the loss is relatively large and the operation margin is reduced. The word line boost circuit is for solving this problem and boosts the voltage level of the word line to a value equal to or higher than the value obtained by adding the threshold voltage V _TH of the transistor Q _M to the power supply voltage level Vcc.

FIG. 5 is a circuit diagram showing an example of a conventional word line boost circuit.

Referring to FIG. 5, the word line boost circuit 10 includes an inverter 41 connected to receive the word line drive signal W _DS and a clocked inverter 42 connected to its output.
And a series connection of inverters 43 to 46 for delay connected to the output of the clocked inverter 42, and a capacitor C _B for boosting. Node N _F to which inverters 44 and 45 are connected is connected to the clock input of clocked inverter 42. The node N _B is the inverter 46
, And W _DB is the boosted word line drive signal.

FIG. 6 is a timing chart for explaining the operation of the word line boost circuit shown in FIG.

Next, the operation of the word line boost circuit 10 will be described with reference to FIGS. 5 and 6.

First, at time T ₀ , the word line drive signal W _DS changes to high level. The output signal W _DB is delayed by the inverters 41 and 42 and changes to a high level at time T ₁ . Further, the voltage level V _NF of the node N _F is delayed by the inverters 43 and 44 and changes to the high level at the time T ₂ . The clocked inverter 42 outputs the high level voltage V _NF.
Is cut off, and the output of the clocked inverter 42 (the output of the word line boost circuit 10) is brought into a floating state having the power supply voltage level Vcc.

Thereafter, the voltage level V _NB of the node N _B further changes to the high level at time T ₃ due to the delay of the inverters 45 and 46. As a result, the voltage level of the output signal W _DB is boosted to the level Vcc + Vα exceeding the power supply voltage level Vcc by the capacitive coupling of the capacitor C _B. By appropriately setting the capacitance value of the capacitor C _B , this Vα is made equal to or higher than the threshold voltage V _TH of the transistor Q _M.

In this way, the word line drive signal W _DS is boosted and the boosted word line drive signal W _DB is obtained. The high level of this signal W _DB is disconnected from the power supply and becomes a floating state. It is output from the output.

The boosted word line drive signal W _DB is applied to the memory arrays 1 to 4 via four row decoders as shown in FIG.
Are activated at the same time.

FIG. 7 is a schematic circuit diagram showing an example of a conventional row decoder. In this figure, the row decoder 1a of FIG. 3 is shown as an example.

Referring to FIG. 7, each of the row decoders 1a has 51
It includes 512 unit row decoders RD for activating one of the two rows. In this figure, the Kth unit row decoder RD is included.
_K and the K + 1th unit row decoder RD adjacent to K
_{K + 1} is shown. For example, the Kth unit row decoder
RD _K includes a NAND gate 71 connected to no row address signals RA0 to receive RA8, an inverter 72 connected to its output, the three N-channel transistors Q _AK, and Q _BK and Q _CK.

In operation, for example when it is selected the unit row decoder RD _K, to no row address signals RA0 becomes RA8 all high level, NAND gate 71 outputs a low level signal. This signal is inverted by the inverter 72 and given to the gate of the transistor Q _BK.
It is also given to the gate of _CK . As a result, the transistor Q _BK is turned on, and the boosted word line drive signal W _DB is given to the word line WL _K via the transistor Q _BK .

On the other hand, in the adjacent unit row decoder RDK _{+ 1} , the NAND gate outputs a high-level signal because it is in the non-selected state, so that the transistor QBK _{+ 1} turns off and the transistor QCK _{+ 1} turns on. As a result, the word line WL _{K + 1}
Is brought to a low level.

Next, the redundant circuit will be described.

FIG. 8 is a conceptual diagram showing a conventional memory array and a redundant circuit provided therein.

Referring to FIG. 8, a spare row decoder 1as provided in the row decoder 1a and a spare row 1s having a plurality of spare memory cells provided in the memory array 1 are provided as redundant circuits. And are provided. Generally, a spare column decoder and a spare column are further provided, but they are omitted in this figure.

When a defect is found in a certain memory cell or word line in the memory array 1 by the redundancy test, the unit row decoder for activating the word line is always made inactive, and this defective unit row decoder is The spare row decoder 1as is programmed to be selected when an address signal for selecting is selected. Generally, this program is performed by blowing the fuse element with a high voltage pulse or a laser beam. In this way, the row including the defect is replaced with the spare row 1s, and the defective product is reproduced as a good product.

[Problems to be Solved by the Invention] FIG. 9 is a circuit diagram showing a case where the row decoder shown in FIG. 7 has an abnormality.

Referring to FIG. 9, as an example of abnormality, FIG. 9 shows a case where two adjacent word lines WL _K and WL _{K + 1} are short-circuited by a foreign substance having a low anti- _RS . As a result, the boosted word line drive signal W _DB flows to the ground via the resistor R _{S along the} path indicated by the arrow. As described above, this signal W _DB is output from the word line boost circuit whose output is brought into a floating state,
The level of the signal W _DB drops, and this word line WL _K becomes defective.

However, as shown in FIG. 3, this signal W _DB is simultaneously applied to the four word lines WL via the four row decoders, so that, for example, only the word line of the memory array 1 has such a structure. Even if a defect occurs, the level of the signal W _DB drops, so that the word lines of the other memory arrays 2 to 4 are also determined to be defective. That is, they are considered defective even though the other word lines have no defects.

As a result, when each memory array 1 to 4 is provided with only one spare row decoder and one spare row, all of them are used for replacing the word line, and the memory cell is defective. When it exists, it cannot be remedied, so there is a problem that the yield is reduced. Further, even when two or more spare row decoders and spare rows are prepared, there is a problem in that they cannot be effectively used due to the apparent defects as described above.

The present invention has been made to solve the above problems, and an object thereof is to obtain a dynamic semiconductor memory device with a high yield by taking effective measures.

[Means for Solving the Problem] A dynamic semiconductor memory device according to the present invention is provided for each of a plurality of memory cell array blocks and generates a plurality of drive voltages for driving word lines of the respective memory cell array blocks. Drive voltage generation means and a plurality of memory cell array blocks, and the drive voltages from the plurality of drive voltage generation means are simultaneously applied to word lines designated by address signals of two or more corresponding memory cell array blocks. Decoder means.

[Operation] In the dynamic semiconductor memory device according to the present invention, since the plurality of drive voltage generating means are provided for each memory cell array block, it is possible to limit the location where a defect exists to each memory cell array block. As a result, it is possible to effectively take measures such as applying a redundant circuit.

[Embodiment of the Invention] FIG. 1 is a block diagram showing a 1 Mbit dynamic RAM showing an embodiment of the present invention.

Referring to FIG. 1, the difference between this dynamic RAM and the conventional one shown in FIG. 3 is that four word line boost circuits 11 to 14 are used for memory arrays 1 to 4.
It is provided for each. That is, the word line boost circuits 11 to 14 are word line drive signal generation circuits.
The word line drive signals W _DS are respectively received from 51, and boosted word line drive signals W _DB1 to W _DB4 are output and applied to each row decoder.

FIG. 2 is a circuit diagram showing an example of the four word line boost circuits used in FIG.

With reference to FIG. 2, these word line boost circuits 11 to 14 are the same as those shown in FIG. 5, and the description thereof will be omitted.

As a result, for example, even if a short circuit due to a foreign substance occurs in the word line as shown in FIG.
The level of _DB1 decreases, but other signals W _DB2 to W _DB4
Is electrically isolated, so the level does not drop.
Therefore, the word lines of the other memory arrays 2 to 4 selected at the same time are not considered to be defective, and the spare row decoders provided in these memory arrays 2 to 4 can be used for relieving defects of other memory cells or the like. The yield can be improved.

In the above embodiment, only the word line boost circuits are provided in plural and the word line drive signal generation circuits are not provided in plural. This is because when a plurality of word line drive signal generation circuits are provided, the area occupied by these circuits increases, which is not preferable.

In the above embodiment, the dynamic semiconductor memory device using the N channel type memory cell has been described.
The present invention can be applied to a dynamic semiconductor memory device using a channel memory cell. In that case, a circuit for boosting to a potential lower than the ground potential may be provided as the word line boost circuit.

[Effects of the Invention] As described above, according to the present invention, since a plurality of drive voltage generating means for driving the word lines provided for each of the plurality of memory cell array blocks are included, the location where the defect exists is stored in the memory. This can be known for each cell array block, and a dynamic semiconductor memory device with a high yield can be obtained by effectively taking measures such as applying a redundant circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a 1 Mbit dynamic RAM showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of four word line boost circuits used in the dynamic RAM shown in FIG. FIG. 3 is a block diagram showing a conventional 1 Mbit dynamic RAM. FIG. 4 is a circuit diagram showing an equivalent circuit of a conventional memory cell. FIG. 5 is a circuit diagram showing an example of a conventional word line boost circuit. FIG. 6 is a timing chart for explaining the operation of the word line boost circuit shown in FIG. FIG. 7 is a schematic circuit diagram showing an example of a conventional row decoder. FIG. 8 is a conceptual diagram showing a conventional memory array and a redundant circuit provided therein. FIG. 9 is a circuit diagram showing a case where the row decoder shown in FIG. 7 has an abnormality. In the figure, 1 to 4 are memory arrays, 1a is a row decoder, 1b is a sense amplifier, 1c is a column decoder, 1as is a spare row decoder, 1s is a spare row, 10 to 14 are word line boost circuits, and 51 is a word line drive. It is a signal generation circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A dynamic semiconductor memory device comprising a plurality of memory cell array blocks each including a plurality of memory cells connected to a plurality of word lines, wherein the dynamic semiconductor memory device externally controls a state of the memory device. State input means for receiving a state control signal; address input means for receiving an address signal for externally addressing the memory device; and a plurality of memory cell array blocks provided for each of the memory cell array blocks.
A plurality of drive voltage generating means for respectively generating a drive voltage for driving a word line of the memory cell array block in response to a state signal from the state input means and an address signal from the address input means; Connected to each of the plurality of memory cell array blocks and to each of the plurality of drive voltage generation means, and decodes an address signal from the address input means to output two or more of each of the plurality of memory cell array blocks. A plurality of decoder means for simultaneously applying a drive voltage from each of the plurality of corresponding drive voltage generating means to a word line designated by decoding; addressing of the memory device is performed by the drive voltage generating means. Apply voltage to the word line specified by the decoding. Made by, a dynamic semiconductor memory device.