JPH0738013A - Composite base member and power semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a mount base and a power semiconductor device, which can form a semiconductor device having a small inductance and a complicated circuit configuration with relatively simple and few wiring. A first electric insulating plate (1) having a thin metal member fixed to one surface, a first electrode pad (2) fixed to the other surface of the first electric insulating plate, and a first electrode. A second electric insulating plate 6 fixed to the first electrode pad 2 and arranged on the first electric insulating plate 1 so as to sandwich the pad 2, and a second electric insulating plate 6 fixed to the second electric insulating plate 6. An electrode pad (3), the first electrode pad (2) has a conductive terminal extending from a part thereof, and the second electrically insulating plate (6) has an opening exposing at least a part of the first electrode pad (2). A power semiconductor device having a semiconductor element 5 fixed to a mount base and a first electrode pad 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite base member formed by fixing electrode pads to an electric insulating plate such as a ceramic substrate, or a power semiconductor device having a semiconductor element fixed to the composite base member. Especially high power MOSFET
The present invention relates to a power semiconductor device suitable for such a high-speed switching semiconductor module.

[0002]

2. Description of the Related Art As a power semiconductor device in which a semiconductor element is brazed to an electrode pad made of a metal plate fixed on an electric insulating plate by various methods, there is disclosed in Japanese Patent Laid-Open No. 60-103649.
JP-A-61-140158, JP-A-62-140158
-209834, or Japanese Patent Laid-Open No. 4-287952
Some of them are disclosed in Japanese publications.

With respect to the structures disclosed in these documents, an example of a field effect transistor (hereinafter referred to as FET) will be described with reference to FIG. A drain electrode pad, which is the first electrode pad 2, and a second electrode pad 3 are formed on one main surface 1A of the electric insulating plate 1 fixed to a heat dissipation plate (not shown) made of a relatively thick metal plate. An electrode pad for a source and an electrode pad for a gate which is the third electrode pad 4 are fixed. The FET chip which is the semiconductor element 5 has a drain electrode (not shown) on its lower surface and a plurality of small source electrodes 5A and gate electrodes 5B on its upper surface. The drain electrode is soldered to the drain electrode pad 2 The source small electrode 5A and the gate electrode 5B are connected to the source electrode pad 3 and the gate electrode pad 4, respectively, by bonding wires (not shown). And first, second,
Each of the third electrode pads 2, 3 and 4 has an L-shaped first conductive terminal 2A, a second conductive terminal 3A, and a third conductive terminal 4
A is soldered. 3A ′ is another conductive terminal soldered to the source electrode pad 3. In addition,
Although not shown, the plurality of small source electrodes 5A are connected to a single source electrode pad 3 by each bonding wire.
The gate electrode 5B is also connected to the third electrode pad 4 by a bonding wire.

[0004]

However, not only the power semiconductor device having this structure but also the conventional composite base member is provided with the first electrode pad 2 on one main surface 1A of the electric insulating plate 1. A certain drain electrode pad, a source electrode pad that is the second electrode pad 3, and a third electrode pad 4
Since all of the gate electrode pads are fixed in a plane, and their size cannot be reduced more than necessary,
Since the inductance of the semiconductor device cannot be reduced sufficiently, there is a difficulty in operating at high frequencies. In addition, the positioning of the semiconductor element 5 on the drain electrode pad 2 must be performed by using a positioning tool, and the first, second, and third electrode pads 2, 3 and 4 can be mounted on the third electrode pad 2, 3, 4, respectively. Since the step of soldering the conductive terminals 2A, 3A, 3A ', 4A is required, there is a problem that it is difficult to manufacture. In addition, when incorporating a plurality of semiconductor elements and other electronic component elements, there are drawbacks in that the bonding wires must intersect and become longer.

The present invention solves the conventional problems described above, and has a small inductance, is easy to manufacture with a relatively simple wiring structure, and a composite that enables such a power semiconductor device. It is intended to provide a base member.

[0006]

In order to solve the above-mentioned problems, the present invention provides a first electric insulating plate having a thin metal plate adhered to one surface and the other of the first electric insulating plate. A first electrode pad fixed to the surface of the first electrode, and the first electrode pad disposed on the first electrical insulating plate so as to sandwich the first electrode pad.
A second electric insulating plate fixed to the electrode pad of the
A second electrode pad fixed to the electrical insulating plate of
The first electrode pad has a conductive terminal of the same body extending from a part thereof, and the second electrically insulating plate has a composite base member having an opening exposing the first electrode pad, or the composite base member. The present invention provides a power semiconductor device used.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.
First, referring to FIG. 1 and FIG. 2, an embodiment of the present invention will be described. The first electrical insulating plate 1 is a copper plate having a good thermal conductivity through a metal plate 1'having a thin metallized back surface in a usual manner. A first electrode pad 2 made of a thin copper plate or the like on the pre-metallized surface of the first electrically insulating plate 1 Is fixed with brazing material. From the first electrode pad 2, the first electrode pad 2 is punched in the metal plate punching process.
The conductive terminal 2A formed at the same time extends and the conductive terminal 2A
Has a round hole 2a for mounting.

Next, the second electrically insulating plate 6 having the opening 6A, which is also a feature of the present invention, is fixed onto the first electrode pad 2. The second electric insulating plate 6 is also like a ceramic substrate whose front and back surfaces are metallized in advance, and is fixed with a brazing material as described above. Although the opening 6A will be described later, if the size of the semiconductor element 5 is larger than that of the semiconductor element 5 and the size of the opening 6A is slightly larger than that of the semiconductor element 5, the opening 6A is positioned for positioning the semiconductor element 5. Can be done. Here, the first electrode pad 2 is the second electrical insulating plate 6
Has a larger surface than the opening 6A, and the first electrode pad 2 is exposed over the entire surface of the opening 6A.

The second electrode pad 3 has a U-shaped portion, and the U-shaped portion is arranged along the semiconductor element 5. The second electrode pad 3 has conductive terminals 3A and 3A ', and the third electrode pad 4 has conductive terminals 4A. The electrode pads 3 and 4 are fixed to the second electric insulating plate 6 with a brazing material or the like. The conductive terminal 3A 'and the conductive terminal 4A are
Since the control signal power is supplied during this time, in order to minimize the inductance by making the control signal path as short as possible,
Placed close to each other. Here, for convenience of explanation, the respective members are sequentially brazed, but in the actual manufacturing process, the respective members, or a part of them, are sequentially stacked through the brazing material, and heated in a state in which a pressing force is applied. It is rational to make the composite base member 7 on which the semiconductor element 5 is mounted by performing the processing.

Thereafter, the semiconductor element 5 is put in the opening 6A of the second electric insulating plate 6 and the first main current electrode (not shown) provided on the back surface of the semiconductor element 5 is attached to the first electrode pad. Braze to 2. A second main current electrode 5A is provided on the upper surface of the semiconductor element 5, and the second main current electrode 5A is composed of a plurality of small electrodes arranged in two rows substantially parallel to the upper surface of the semiconductor element 5. The small electrodes are connected to the U-shaped portion of the second electrode pad 3 by bonding wires 8A and 8B having the same length. The control electrode 5B formed on the upper surface of the semiconductor element 5 is connected to the third electrode pad 4 by the bonding wire 8C. After that, the semiconductor element 5 is subjected to the usual insulation treatment, and if necessary, the conductive terminals 2A, 3A, 3A ', 4A are bent at a substantially right angle.

In this embodiment, the first electrode pad 2 and the second electrode pad 3 face each other with the second electric insulating plate 6 sandwiched therebetween, so that the first electrode pad 2 and the second electrode pad 3 are opposed to each other. The inductance of the main current path including 3 becomes small.

Also, by making the size of the opening 6A of the second electric insulating plate 6 slightly larger than that of the semiconductor element 5, the positioning of the semiconductor element 5 at the opening 6A can be made quite accurate.

Furthermore, since the plurality of small electrodes of the semiconductor element 5 are connected to the U-shaped portion of the second electrode pad 3 by the bonding wires 8A and 8B having the same length, the inductance can be further reduced, which is favorable. A high frequency operation can be performed.

Furthermore, the control signal is applied between the control signal conductive terminal 4A and the conductive terminal 3A 'through which the main current does not flow, and the inductance of the control signal current path is reduced. ， This enables even better high frequency operation. In addition, 2a, 3a, 3
a ', 4a are corresponding conductive terminals 2A, 3A, 3A', 4
It is a round hole for attachment provided in each A.

Next, another embodiment will be described with reference to FIG. The same symbols as those shown in FIGS. 1 and 2 indicate corresponding members. In this embodiment, a first electrode pad 2 having a conductive terminal 2A and a third electrode pad 4 having a conductive terminal 4A are arranged on a first electrically insulating plate 1.
It is fixed. A second electric insulating plate 6 having an opening 6A and an opening 6B smaller than the opening 6A is arranged and fixed thereon. In this state, a part of the first electrode pad 2 is exposed from the opening 6A, and a part of the third electrode pad 4 is exposed from the small opening 6B. The semiconductor element 5 is fixed to the exposed first electrode pad 2, and the resistance chip 9 is fixed to the exposed third electrode pad 4.

Next, a second electrode pad 3 having a window having a size exposing the semiconductor element 5 and the resistance chip 9 is fixed on the second electric insulating plate 6, and the second electrode pad 3 is fixed.
Has conductive terminals 3A and 3A 'on opposite sides. Each second main current electrode 5A of the semiconductor element 5 is connected to the adjacent second electrode pad 3 by the respective bonding wires 8A and 8B. The control electrode 5B of the semiconductor element 5 is connected to the resistance chip 9 by the bonding wire 8C.
Therefore, the control electrode 5B is connected to the third electrode via the resistor chip 9.
Will be connected to the electrode pad 4 of. In order to balance the inductance with respect to the current flowing here, the conductive terminal 2A extends from approximately the center of one side of the first electrode pad 2, and the conductive terminals 3A and 3A 'extend from approximately the center of each opposite side of the second electrode pad 3. It is extended. Similarly, the conductive terminal 4A extends from substantially the center of the third electrode pad 4.

What is important here is that the first electrode pad 2
Of the second electrode pad 3 and the conductive terminal 3A of the second electrode pad 3 face each other with a space therebetween.
Conductive terminal 3A 'and conductive terminal 4A of the third electrode pad 4
And are facing each other across a space. This reduces the inductance of the conductive terminals 2A and 3A through which the main current flows, so that the high frequency response of this semiconductor device can be further improved, and the resistance chip 9 can be easily positioned and mechanically protected.

Next, another embodiment of the present invention will be described with reference to FIG. The same symbols as those shown in FIGS. 1 to 3 indicate corresponding members. This semiconductor device is
As shown in FIG. 4 (A), a resistor R is connected to the gate of the MOS field effect transistor T, and a Schottky barrier diode S is connected in series with its drain.
In addition, it is an embodiment in which a high-speed diode D is connected in anti-parallel across them.

As shown in FIG. 2D, the first electrode pad 2, the third electrode pad 4, and the fourth electrode pad 10 are fixed to the upper surface of the first electric insulating plate 1 by a brazing material. ing. Conductive terminals 4A and 10A extend from the electrode pad 4 and the electrode pad 10, respectively. A frame surrounded by a chain line in each electrode pad indicates a portion where a semiconductor chip of a MOS field effect transistor or the like will be mounted later.

The second electrically insulating plate 6 has an opening 6A for receiving the semiconductor chip 5 of the MOS field effect transistor T and a resistor chip 9 of a resistor R, as shown in FIG.
6B for receiving the semiconductor chip 11 of the Schottky barrier diode S.
The semiconductor chip 12 including the diode C and the diode D is provided with an opening 6D. The opening 6D also has a space 6d for bonding, which will be described later. Such a second electric insulating plate 6 is arranged on the assembly as shown in FIG. 3D, and each electrode pad 2, 4, is made of a brazing material or the like.
10 and the conductive terminals 4A and 10A are partially fixed.

Next, as shown in FIG. 3B, the second electrode pad 3 similar to that of the embodiment of FIG. 3 is fixed on the second electric insulating plate 6, and the second electric insulating plate 6 is attached. Each opening 6A to 6D
An electronic component chip is mounted and fixed on each electrode pad exposed at. That is, the drain electrode of the semiconductor chip 5 of the MOS field effect transistor T is fixed to the first electrode pad 2 through the opening 6A, and the resistance chip 9 of the resistor R is fixed to the third electrode pad 4 through the opening 6B. , And the cathode electrode of the semiconductor chip 11 of the Schottky barrier diode S is fixed to the first electrode pad 2 through the opening 6C, and the cathode electrode of the semiconductor chip 12 of the diode D is fixed to the fourth electrode pad 10 through the opening 6D. To be done.

Next, a bonding wire is used for connection, but the semiconductor chip 5 and the resistance chip 9 are the same as those in FIG. The anode electrode (not shown) of the semiconductor chip 11 of the Schottky barrier diode S is connected to the fourth electrode by a plurality of short bonding wires 8D.
Is connected to the electrode pad 10. The anode electrode (not shown) of the semiconductor chip 12 of the diode D is connected to the second electrode pad 3 by a plurality of short bonding wires 8E.
Connected to. In this embodiment as well, the effects described above can be obtained, and the semiconductor chips 11 and 12 can be easily positioned.

Next, another embodiment in which semiconductor elements are arranged in parallel will be described with reference to FIG. The same symbols as those shown in FIGS. 1 to 4 indicate corresponding members.
This embodiment is basically the same as that of FIG.
The electrode pad 2 of each of the openings 6 of the second electrical insulating plate 6
Two semiconductor elements 5 and 5 ′ are mounted through A and 6A ′, and two resistance chips 9 and 9 ′ are mounted through the openings 6B and 6B ′. The second electrode pad 3 is provided with the semiconductor element 5 and the resistance chip 9, and two windows corresponding to the semiconductor element 5'and the resistance chip 9 '. Each of the plurality of second main current electrodes 5A 'of the semiconductor element 5'is also connected to the corresponding second electrode pad 3 by the corresponding bonding wire 8A', 8B ', and the control electrode 5B' is also connected by the bonding wire 8C '. It is connected to the resistance chip 9 '. Also in this embodiment, the same effect as that of the semiconductor device of FIG. 3 can be obtained.

Next, the embodiment shown in FIG. 6 is a semiconductor module in which the embodiments of FIGS. 4 and 5 are combined, and the circuit shown in FIG. 6A is made into a single semiconductor device. . The same symbols as those shown in FIGS. 1 to 5 indicate corresponding members.

FIG. 6D shows a third electrode having a first electrode pad 2 and a conductive terminal 4A fixed to a single first electrical insulating plate (not shown) as in the above embodiment. The 4th electrode pad 10 provided with the pad 4 and the conductive terminal 10A is shown. On the first electrode pad 2, semiconductor chips 5, 5'of MOS field effect transistors T1, T2, and semiconductor chips 11, Schottky barrier diodes S1, S2,
11 'is mounted, and the resistor R1,
The resistance chips 9, 9'of R2 are fixed. Then, the diode chips 12, 12 ′ of the diodes D 1, D 2 are mounted and fixed on the fourth electrode pad 10. The second electrode pad 3 has two windows similarly to that shown in FIG. 4, and the second electric insulating plate 6 has a structure in which two sheets shown in FIG. 4 are juxtaposed. In this embodiment, the same effect as the above embodiment can be obtained.

Next, the embodiment shown in FIG. 7 is an embodiment in which MOS field effect transistors T1 and T2 are connected in series to form a half bridge structure as shown in FIG. Symbols that are the same as those shown in () indicate corresponding members.

FIG. 3D shows an electrode pad 2 having a conductive terminal 2A, an electrode pad 2'having a conductive terminal 2'A, an electrode pad 4 having a conductive terminal 4A and an electrode pad 4 having a conductive terminal 4'A. ', And is fixed to a single first electrical insulating plate (not shown) as in the previous embodiment. The semiconductor chip 5 of the MOS field effect transistor T1 is mounted on the electrode pad 2, the semiconductor chip 5'of the MOS field effect transistor T2 is mounted on the electrode pad 2 ', and the resistor chip 9 of the resistor R1 is mounted on the electrode pad 4. , R2 resistor chips 9'are fixed to the electrode pads 4 '.

FIG. 3C shows the source electrode pad 3 of the semiconductor chip 5 of the MOS field effect transistor T1 and the semiconductor chip 5'of the MOS field effect transistor T2.
The electrode pad 3'for a source is shown. The electrode pad 3 has conductive terminals 3A ', and the electrode pad 3'has conductive terminals 3'A and 3'A'. The second electric insulating plate 6 has an opening 6A.
And 6B, 6A 'and 6B', and an opening 6E for bonding is provided in the center thereof. The opening 6
A part of the electrode pad 2'is exposed through E, and the bonding wire 8B extends from the source electrode of the semiconductor chip 5 of the MOS field effect transistor T1 to the electrode pad 3 '.
After being bonded to the electrode pad 2 ', a part of the electrode pad 2'is exposed through the opening 6E.

Therefore, according to this structure, the MOS field effect transistors T1 and T2 are connected by the bonding wire 8
B is connected in series through the electrode pad 2'and the conductive terminal 2
A and 3'A serve as a pair of main current terminals, and conductive terminals 2 '
A serves as an AC output terminal. In addition, the conductive terminals 3A 'and 4
A, first and second gate signals are applied between the conductive terminals 3'A 'and 4'A. Also in this embodiment, since the semiconductor module alone constitutes the half bridge and the current path and the gate signal path are made as short as possible, the inductance can be minimized, and therefore the power MO can be operated at a high frequency.
An S-type field effect transistor can be obtained.

Next, the embodiment shown in FIG. 8 is an embodiment in which two circuits shown in FIG. 4A are connected in series to form a half-bridge structure, and the same symbols as those shown in FIGS. Indicates a corresponding member.

FIG. 3D shows electrode pads 2 and 2 ', electrode pad 4 having conductive terminals 4A and electrode pad 4'having conductive terminals 4'A, and electrode pad 10 having conductive terminals 10A and conductive terminals. Electrode pad 10 'provided with 10'A
And is fixed to a single first electrical insulating plate (not shown) as in the previous embodiment. The semiconductor chip 5 of the MOS field effect transistor T1 and the semiconductor chip 11 of the Schottky barrier diode S1 are provided on the electrode pad 2, and the semiconductor chip 5'of the MOS field effect transistor T2 and the Schottky barrier diode S2 are provided on the electrode pad 2 '. A semiconductor chip 11 'is mounted. Electrode pad 4, 4 '
To the electrode pads 10 and 10 ', and the diode chips 12 and 12' of the diodes D1 and D2 are fixed to the electrode pads 10 and 10 ', respectively.

The plurality of bonding wires 8D connect the anode electrode of the semiconductor chip 11 of the Schottky barrier diode S1 to the electrode pad 10 exposed from the bonding space 6d of the opening 6D of the second electric insulating plate 6. The plurality of bonding wires 8E are diodes D
After connecting the anode electrode of the first diode chip 12 to the electrode pad 3, it is subsequently connected to the electrode pad 10 through the opening 6E at the center of the second electric insulating plate 6. The semiconductor chip 11 'and the diode chip 12' are connected by bonding wires 8D'8E 'in the same manner as in FIG. In this embodiment, the same effect as the above-mentioned embodiment can be obtained.

Although the MOS type field effect transistor has been described as the semiconductor element in the above embodiments, a power semiconductor device having a relatively high frequency response such as an electrostatic induction type semiconductor device and an IGBT (insulated gate type bipolar transistor). The same effect as described above can be obtained even when applied to.
Further, in the embodiment of FIGS. 5 to 8, the second electric insulating plate 6 may be composed of the same number of electric insulating plates as the semiconductor elements for standardization. In this case, the opening 6E can be used in place by providing an appropriate gap between the electric insulating plates. Further, if the positioning of each electronic component element is not so required, the second opening may have a considerably larger area than the electronic component element it receives, or it may have any shape for receiving a plurality of electronic component elements. .

[0034]

As described above, according to the present invention, since the inductance of the main current path and the control current path can be reduced, a power semiconductor device having a good high frequency response can be obtained. In addition, a semiconductor device having a complicated circuit configuration can be configured relatively easily with a small amount of wiring, and at the same time,
Since each electronic component element can be positioned by the second electric insulating plate, the manufacturing becomes easy.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram for explaining another embodiment of the present invention.

FIG. 3 is a diagram for explaining another embodiment of the present invention.

FIG. 4 is a diagram for explaining another embodiment of the present invention.

FIG. 5 is a diagram for explaining another embodiment of the present invention.

FIG. 6 is a diagram for explaining another embodiment of the present invention.

FIG. 7 is a diagram for explaining another embodiment of the present invention.

FIG. 8 is a diagram for explaining another embodiment of the present invention.

FIG. 9 is a diagram for explaining an example of a conventional semiconductor device.

[Explanation of symbols]

 1 ... 1st electric insulation board 2 ... 1st electrode pad 2A ... conductive terminal 3 ... 2nd electrode pad 3A ... conductive terminal 4 ... 3rd Electrode pad 4A ... Conductive terminal 5 ... Semiconductor element 6 ... Second electrical insulating plate 6A to 6E ... Opening of second electrical insulating plate 7 ... Composite base member 8A 8E ... Bonding wire 9 ... Resistor chip 10 ... 4th electrode pad 10A ... Conductive terminal 11 ... Semiconductor chip 12 ... Diode chip

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 25/18

Claims (10)

[Claims] 1. A first electric insulating plate having a thin metal member fixed to one surface thereof, a first electrode pad fixed to the other surface of the first electric insulating plate, and the first electric insulating plate. A second electric insulating plate which is arranged on the first electric insulating plate so as to sandwich the electrode pad and is fixed to the first electrode pad, and a second electrode which is fixed to the second electric insulating plate. A pad, the first electrode pad has a conductive terminal extending from a portion thereof, and the second electrically insulating plate has an opening exposing at least a portion of the first electrode pad. Composite base member to be. 2. A conductive terminal extending from one or more of the first and second electrode pads is provided.
The composite base member according to 1. 3. The composite base member according to claim 1, wherein a conductive terminal extending from the first electrode pad and a conductive terminal extending from the second electrode pad face each other. 4. The composite base member according to claim 1, wherein a conductive terminal extending from the second electrode pad and a conductive terminal extending from the third electrode pad face each other. 5. The first conductive terminal and the second conductive terminal, wherein the second electrode pad has a window portion larger than the first opening portion of the second electric insulating plate, and extends from a substantially central portion thereof. The composite base member according to claim 1, further comprising: 6. The composite base member according to claim 1, wherein the second electrically insulating plate has a plurality of openings for receiving the electronic component elements. 7. A semiconductor device in which a first main current electrode, a second main current electrode, and a control signal electrode of a semiconductor element are electrically connected to corresponding first, second, and third electrode pads, respectively. In the above, the first electrode pad is fixed to the first electric insulating plate, and the second electric insulating plate having an opening larger than the semiconductor element area sandwiches the first electrode pad. Is disposed on the first electric insulating plate, the semiconductor element is fixed to the first electrode pad in the opening of the second electric insulating plate, and the second electrode is attached to the second electric insulating plate. A power semiconductor device having a fixed pad. 8. A semiconductor device in which a first main current electrode, a second main current electrode, and a control signal electrode of a semiconductor element are electrically connected to corresponding first, second, and third electrode pads, respectively. In the above, the first electrode pad and the third electrode pad are fixed to the first electrical insulating plate, and the first opening having a size larger than the semiconductor element area and the second opening having a size smaller than the area are formed. A second electric insulating plate having the second electric insulating plate is disposed on the first electric insulating plate with the first electrode pad and the third electrode pad interposed therebetween, and the semiconductor element has the second electric insulating plate of the second electric insulating plate. The second electronic component is fixed to the first electrode pad in the first opening, and the other electronic component element is fixed to the first electrode pad in the second opening.
The semiconductor device for electric power, wherein the second electrode pad is fixed to the electric insulating plate. 9. The second electrode pad has first and second conductive terminals, and is controlled between a conductive terminal extending from the third electrode pad and a second conductive terminal of the second electrode pad. 9. The power semiconductor device according to claim 7, wherein a signal is applied. 10. One or more electronic component elements other than the one or more semiconductor elements are fixed to the first electrode pad, and the electronic component element is connected to the fourth electrode pad by a conductive member. Claim 7 or claim 8 characterized in that
The power semiconductor device according to item 1.