JPH0738169B2 - Memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel write / serial read type memory device.

2. Description of the Related Art Conventionally, a serial data communication device, which has been widely used in one-chip microprocessors, is composed of a shift register, a shift counter, and a buffer register, a typical example of which is JP-B-60-58482.
It is shown in the publication. According to this, in order to transmit serial data, one frame of data (often 4 bits or 8 bits becomes one frame) is transferred from the data bus to the buffer register, and then serial data is transferred from the shift register. Is sent out.

However, in the above configuration, in order to transmit a data group of several frames at a time, it is necessary to prepare a plurality of buffer registers, which increases the wiring in the parallel data input / output section. Had the problem.

In view of the above problems, the present invention realizes a buffer register group in which the wiring of the data input / output unit does not increase even when serial data for several frames is continuously transmitted, and more specifically, the number of wirings is reduced. An object of the present invention is to provide a memory device which can store a small amount of data for a plurality of frames and can also retrieve serial data.

Means for Solving the Problems In order to solve the above-mentioned problems, in a memory device of the present invention, a decoder for selecting a bit position of a frame configured by arranging a plurality of data storage bits and a data storage bit are respectively connected. A plurality of bit selection lines are provided and line switching means for supplying parallel data to the bit selection lines when writing data and connecting a decoder to the bit selection lines when outputting data.

Operation In the present invention, with the above-described configuration, writing of parallel data and selection of bit positions at the time of data output are performed through a common line, and the number of wires for performing these operations is greatly reduced. .

EXAMPLES Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a memory device according to an embodiment of the present invention. A first frame 100 is composed of data storage bits 110, 120, 130, 140, 150, 160, 170, 180. The data storage bit 110 is a unit memory cell formed by the inverter 111 and the 3-state inverter 112, a 3-state inverter 113 for sending the output of the unit memory cell to the SX terminal, a 3-state buffer 114 for transmitting write data to the inverter 111, 3-state buffer 1
3-state inverter 11 when 14 is active
Inverter 1 that puts the output of 2 in the high impedance state
15 and an AND gate 116 that activates the 3-state inverter 113 when the 8th bit of the first area is selected by the data supplied to the X0 terminal, X1 terminal, X2 terminal, Y0 terminal, and Y1 terminal Data storage bit 12
0 to 180 have the same configuration. Also, the first frame
Similar to 100, a second frame 200 and a third frame 300 are configured.

On the other hand, the first frame 100, the second frame 200, the third frame
The output side of the line selection switch group 500 is connected to the bit selection line group 400 that is connected to each data storage bit that forms the line selection switch group 500.
Input terminals of the state buffers 501 to 508 are respectively connected to terminals D0 to D7, and input terminals of the three state buffers 511 to 518 are supplied with outputs of the decoder 600.

In FIG. 1, when writing data, parallel data for writing in the first frame 100 to the third frame 300 is supplied to the D0 terminal to the D7 terminal, and the first frame 100 to the third frame are supplied to the P0 terminal and the P1 terminal. 2-bit data for selecting one of the frames 300 is supplied and the level of the LOAD terminal is temporarily shifted to "1". Also, when outputting serial data from the SX terminal, 2-bit data for selecting one of the first frame 100 to the third frame 300 is supplied to the Y0 and Y1 terminals, and the X0, X1 and X2 terminals are supplied. Is supplied with 3-bit data that specifies the bit position of the selected frame.

The operation of the memory device configured as described above will be described based on the timing charts of the main parts shown in the configuration diagram of FIG. 1 and FIG.

First, FIG. 2A shows a clock signal waveform for transmitting serial data, and FIGS. 2B, C and D show X0 terminal, X1 terminal and X2, respectively.
The signal waveforms supplied to the terminals, Fig. 2E and F are the signal waveforms supplied to the Y0 and Y1 terminals, respectively, and Fig. 2G is the change in the output data from the SX terminal. is there.

Now, in order to write parallel data to the first frame 100, set the levels of the P0 and P1 pins to "1" and "0", respectively, supply the transmit data to the D0 to D7 pins, and then , LOAD pin level is temporarily changed to "1". By the operation of these series of operations, the output level of the AND gate 1 shifts to "1", the 3-state buffer 508 transmitting the level of the D7 terminal also becomes active, and conversely, the AND gate 608 of the decoder 600 constituting the decoder 600 is activated. The output of the 3-state buffer 518 transmitting the output level is in a high impedance state. As a result, the data storage bit 110
In particular, the output of the 3-state inverter 112 is in a high impedance state, and on the contrary, the 3-state buffer 114 is in an active state, the level of the D7 terminal is transmitted to the inverter 111, and the writing of data is completed.

Similarly, in order to write parallel data to the second frame 200, set the levels of the P0 terminal and the P1 terminal to “0”,
Set it to "1", supply the transmission data to the D0 to D7 pins, and then temporarily shift the level of the LOAD pin to "1". In order to write parallel data to the third frame 300, Sets the levels of the P0 and P1 pins to “1” and “1” respectively, supplies the transmit data to the D0 to D7 pins, and then loads
It is sufficient to temporarily shift the pin level to "1".

When transmitting data, fix the level of the LOAD pin to "0" and set the levels to be supplied to the X0 pin to X2 pin, Y0 pin, and Y1 pin as shown in Fig. 2B to D, E, and F, respectively. If changed, the data sent to the SX terminal changes as shown in FIG. 2G. That is, since the levels of the X0 terminal to the X2 terminal, the Y0 terminal, and the Y1 terminal are all “1” before the time t _{1 in} FIG. 2, the output levels of the AND gate 608 and the AND gate 2 are both “1”. 1 ", the data storage bit 180 of the first frame 100
Also, the output level of the AND gate 186 that configures is also "1". Therefore, at this time, the data held in the data storage bit 180 is sent to the SX terminal via the 3-state inverter 183. When the leading edge of the clock signal arrives at time t ₁ , the level of the X0 terminal shifts from “1” to “0” (FIG. 2B), whereby the AND gate 607 which constitutes the decoder 600. The output level of is shifted to "1", and the data held in the data storage bit 170 is sent to the SX terminal this time. Thereafter, similarly, until the time t ₂ , the output of each data storage bit of the first frame 100 is successively output by SX.
It is sent to the terminal.

When the leading edge of the clock signal arrives at time t _2, the the level of X0 terminal -X2 terminal transitions to "1" respectively, the level of this time Y0 pin goes to "0" (second
As a result, the output level of the AND gate 3 is "1".
The second frame 20 from this point until time t ₃
The output of each data storage bit of 0 is sent to the SX pin one after another.

Further, from the time t ₃ to the time t _4, the third frame 300
The output of each data storage bit of is sent to the SX pin one after another.

In this way, the memory device shown in FIG. 1 can store data for a plurality of frames to be transmitted at one time, and can also store data to be applied to the X0 to X2, Y0 and Y1 terminals. If changed, serial data can be sequentially fetched from the SX terminal. That is, the memory device shown in FIG. 1 has the functions of the conventional buffer register and shift register, and the bit selection line group 400 is used not only for selecting each data storage bit but also for parallel data. Since it is also used as a transfer path, the number of internal wirings is reduced.

Next, FIG. 3 is a circuit configuration diagram showing another embodiment of the present invention, in which the storage portion of the transmission data is the first frame 100 and the second frame.
Consists of a frame 200, with the first data storage bit configuration
Different from the device shown. That is, data storage bit 11
0'is composed of inverters 111, 115, 3-state inverters 112, 3-state buffers 114, 117. Compared with the device of FIG. 1, the AND gate 116 is eliminated and the 3-state inverter 117 is replaced by the 3-state buffer 117. Has been. The serial data from the first frame 100 'is supplied to the SX terminal via the 3-state inverter 4, and the serial data from the second frame 200' is supplied to the SX terminal via the 3-state inverter 5. Therefore, in the apparatus of FIG. 2, the serial data from the first frame 100 is supplied to the SX terminal when the level of the P1 terminal is "1", and the serial data from the second frame 200 'is supplied to the SX terminal when the level is "0". Is supplied to. Since the other operations are the same as those of the apparatus shown in FIG. 1, description thereof will be omitted.

As is apparent from the above description, the memory device of the present invention has a plurality of data storage bits each including a unit memory cell and output switch means for transmitting the output of the unit memory cell to a common output terminal. A frame configured by arranging, a decoder that selects the bit position of the frame, a plurality of bit selection lines that are connected to the data storage bits, respectively, and parallel data is supplied to the bit selection line when writing data Since the line switching means that connects the decoder to the butt selection line is provided at the time of output, even when serial data for several frames is continuously transmitted, the wiring of the data input / output unit does not increase and the serial data It is possible to realize a memory device that can also take out the memory device, which has a great effect.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a memory device in one embodiment of the present invention, FIG. 2 is a timing chart of the main part of FIG. 1,
FIG. 3 is a circuit configuration diagram of a memory device according to another embodiment of the present invention. 100 ... 1st frame, 180 ... Data storage bit, 183
... 3-state inverter, 183,200 ... 2nd frame, 300 ... 3rd frame, 400 ... bit selection line group,
500 …… Line changeover switch group, 600 …… Decoder.

Claims (1)

[Claims] 1. A frame formed by arranging a plurality of data storage bits, each unit memory cell and output switch means for transmitting an output of the unit memory cell to a common output terminal, and a bit of the frame. A decoder for selecting a position, a plurality of bit selection lines respectively connected to the data storage bits, parallel data is supplied to the bit selection lines when writing data, and the decoder is provided to the bit selection lines when outputting data. And a line switching means for connecting the memory device.