JPH073867B2 - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- JPH073867B2 JPH073867B2 JP60271859A JP27185985A JPH073867B2 JP H073867 B2 JPH073867 B2 JP H073867B2 JP 60271859 A JP60271859 A JP 60271859A JP 27185985 A JP27185985 A JP 27185985A JP H073867 B2 JPH073867 B2 JP H073867B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- substrate
- layer
- imaging device
- state imaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/15—Charge-coupled device [CCD] image sensors
- H10F39/158—Charge-coupled device [CCD] image sensors having arrangements for blooming suppression
Landscapes
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、固体撮像装置に関するものである。TECHNICAL FIELD The present invention relates to a solid-state imaging device.
従来の技術 従来、Ｐウェル型固体撮像装置は、第２図に示す構造で
あった。第２図ｂは、受光部を模式的に示したものであ
り、第２図ａは、第２図ｂのＢ−Ｂ′方向の不純物濃度
分布を示したものである。第２図ｂにおいて、５はＮ型
シリコン基板で、23はＰ型層、24はＮ型領域である。実
効的な受光領域は、Ｐ型層23とＮ型領域24で形成され
る。実動作として、Ｐ型層23は0Vに接地され、Ｎ型シリ
コン基板５とＮ型領域24は、Ｐ型層23に対して逆バイア
スされている。2. Description of the Related Art Conventionally, a P-well type solid-state imaging device has a structure shown in FIG. FIG. 2b schematically shows the light receiving portion, and FIG. 2a shows the impurity concentration distribution in the BB ′ direction of FIG. 2b. In FIG. 2b, 5 is an N-type silicon substrate, 23 is a P-type layer, and 24 is an N-type region. The effective light receiving region is formed by the P-type layer 23 and the N-type region 24. In actual operation, the P-type layer 23 is grounded to 0V, and the N-type silicon substrate 5 and the N-type region 24 are reverse biased with respect to the P-type layer 23.
そして、第２図の従来の固体撮像装置の構成で必要なブ
ルーミング抑制を行なうためには、Ｐ型層23を完全に空
乏化しなければならない。そのためには、特にＮ型シリ
コン基板５に加える電圧（以下、基板電圧と呼ぶ）は重
要である。少なくとも基板電圧は、通常の駆動電圧（20
V以下）にする必要がある。The P-type layer 23 must be completely depleted in order to suppress the blooming required in the configuration of the conventional solid-state imaging device shown in FIG. For that purpose, the voltage applied to the N-type silicon substrate 5 (hereinafter referred to as the substrate voltage) is particularly important. At least the substrate voltage is the normal drive voltage (20
V or less).
前記、基板電圧を決める要因は、Ｐ型層23の不純物分布
（濃度，深さ）およびＮ型シリコン基板５の濃度であ
る。そして、それらの関係は、プロセスの安定性から、
Ｎ型シリコン基板５は低濃度のものが用いられ、撮像装
置の分光特性の要求から、Ｐ型層23は、拡散長は深く、
低濃度のものが必要であった。The factors that determine the substrate voltage are the impurity distribution (concentration, depth) of the P-type layer 23 and the concentration of the N-type silicon substrate 5. And the relationship between them is
A low concentration N-type silicon substrate 5 is used, and the P-type layer 23 has a deep diffusion length because of the requirement of the spectral characteristics of the image pickup device.
Low concentrations were needed.
発明が解決しようとする問題点 このような従来の構造では、撮像装置の光学的特性とプ
ロセス安定性を同時に満たそうとすると基板電圧は必然
的に高くなる。基板電圧を低くするには、基板の不純物
濃度を上げるかあるいはＰ型層の不純物濃度を下げるか
拡散長を短くする必要がある。しかし、前者は、プロセ
ス変動に敏感になり、後者は、光学的特性が劣化すると
いう問題があった。Problems to be Solved by the Invention In such a conventional structure, the substrate voltage inevitably increases when it is attempted to simultaneously satisfy the optical characteristics and process stability of the image pickup device. To reduce the substrate voltage, it is necessary to increase the impurity concentration of the substrate, reduce the impurity concentration of the P-type layer, or shorten the diffusion length. However, the former has a problem that it becomes sensitive to process variations, and the latter has a problem that optical characteristics are deteriorated.
本発明はこのような問題点を解決するもので、光学的特
性を劣化させることなく、基板電圧の低電圧化が図れし
かもプロセス安定性をも同時に実現することを目的とす
るものである。The present invention solves such a problem, and an object of the present invention is to reduce the substrate voltage and achieve process stability without deteriorating the optical characteristics.
問題点を解決するための手段 この問題点を解決するために本発明は、一導電型を有す
る高不純物濃度の半導体基板の表面に、前記半導体基板
と同一導電型を有するとともに前記半導体基板よりも低
不純物濃度のエピタキシャル層と、前記半導体基板と反
対導電型の第１の半導体層が順次形成され、前記反対導
電型の半導体層の表面に前記半導体基板と同一導電型の
第２の半導体層が形成され、前記半導体基板と前記エピ
タキシャル層とで基板部が形成され、前記第１の半導体
層と前記第２の半導体層とで受光部が形成されているも
のである。Means for Solving the Problems In order to solve this problem, the present invention provides a semiconductor substrate of one conductivity type having a high impurity concentration, which has the same conductivity type as that of the semiconductor substrate and is more preferable than the semiconductor substrate. An epitaxial layer having a low impurity concentration and a first semiconductor layer having an opposite conductivity type to the semiconductor substrate are sequentially formed, and a second semiconductor layer having the same conductivity type as the semiconductor substrate is formed on the surface of the semiconductor layer having an opposite conductivity type. A substrate portion is formed by the semiconductor substrate and the epitaxial layer, and a light receiving portion is formed by the first semiconductor layer and the second semiconductor layer.
作用 この構造により、半導体基板と反対導電型のＰ型層を完
全に空乏化するに必要な基板側の空乏層幅の広がりを高
濃度不純物基板によって制限することにより、空乏化に
必要な基板印加電圧の低電圧化を図ることとなる。Action With this structure, the width of the depletion layer on the substrate side necessary for completely depleting the P-type layer of the opposite conductivity type to the semiconductor substrate is limited by the high-concentration impurity substrate, so that the substrate applied for depletion is applied. The voltage will be lowered.
実施例 第１図a,bはそれぞれ本発明の一実施例によるＰウェル
型固体撮像装置受光部の深さ方向不純物濃度分布と模式
的断面図ｂである。Embodiments FIGS. 1A and 1B are a schematic sectional view b and an impurity concentration distribution in the depth direction of a light receiving portion of a P-well type solid-state imaging device according to an embodiment of the present invention.
第１図ｂにおいて、１は高濃度Ｎ型シリコン基板、２は
低濃度Ｎ型エピタキシヤル層、３は低濃度Ｐ型層、４は
Ｎ型領域である。第１図ａは、第１図ｂのＡ−Ａ′の断
面における深さ方向の不純物濃度分布を示したものであ
る。表面側から、N/P/N-/N+構造となっている。ブルー
ミング抑制の基本動作は、従来型と同一で、低濃度Ｐ型
層３を0Vに接地し、高濃度Ｎ型シリコン基板１に正電圧
を印加して、低濃度Ｐ型層３を完全空乏化することによ
り行なわれる。ブルーミング抑制時には、Ｐ型層３を完
全空乏化するに必要なＮ型基板の不純物量が満足される
までＮ型基板側の空乏層は広がる。本発明によるN/P/N-
/N+構造によれば、Ｎ型基板側の空乏層幅は、Ｎ+基板で
制限され、第１図ａに示すＸAまでとなる。一方、従来
型（N/P/N-構造）では、第１図ａに参考のため示したＸ
Bまで広がる。その結果、基板電圧は、従来型に比べ低
電圧にすることができる。In FIG. 1b, 1 is a high-concentration N-type silicon substrate, 2 is a low-concentration N-type epitaxial layer, 3 is a low-concentration P-type layer, and 4 is an N-type region. FIG. 1A shows the impurity concentration distribution in the depth direction in the cross section AA ′ of FIG. 1B. From the surface side, N / P / N - has a / N + structure. The basic operation for suppressing blooming is the same as the conventional type, in which the low-concentration P-type layer 3 is grounded to 0 V and a positive voltage is applied to the high-concentration N-type silicon substrate 1 to completely deplete the low-concentration P-type layer 3. It is done by doing. When suppressing blooming, the depletion layer on the N-type substrate side expands until the amount of impurities in the N-type substrate required to completely deplete the P-type layer 3 is satisfied. According to the invention N / P / N -
According to the / N + structure, the width of the depletion layer on the N-type substrate side is limited by the N + substrate and is up to X A shown in FIG. 1A. On the other hand, in the conventional type (N / P / N - structure), X shown for reference in FIG.
Spread to B. As a result, the substrate voltage can be made lower than that of the conventional type.
また、本発明の第１図ａにおいて、Ｐ型層やＮ-エピタ
キシヤル層の不純物分布が変動しても、Ｎ型基板側の空
乏層端ＸAの変動は、従来型のＸBに比べて小さいため、
プロセス変動に対しても強い構造となっている。Further, in FIG. 1a of the present invention, even if the impurity distribution of the P-type layer or the N − epitaxial layer changes, the change of the depletion layer edge X A on the N-type substrate side is different from that of the conventional X B. Because it is small
It has a strong structure against process fluctuations.
なお、実施例では、Ｐウェル型固体撮像装置について述
べたが、Ｐ型基板を用いたＮウェル型固体撮像装置にお
いても同様な効果が得られることは明白である。In addition, although the P-well type solid-state imaging device has been described in the embodiment, it is obvious that the same effect can be obtained also in the N-well type solid-state imaging device using the P-type substrate.
発明の効果 以上のように本発明によれば、固体撮像装置の光学特性
の劣化およびプロセスの安定化を損うことなく、基板電
圧の低電圧化が図れ、かつ、プロセス変動に対しても強
いなどきわめて有効な効果が得られる。EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to lower the substrate voltage without deteriorating the optical characteristics of the solid-state imaging device and stabilizing the process, and it is also resistant to process fluctuations. Very effective effect can be obtained.
第１図a,bは、本発明の一実施例によるＰウェル型固体
撮像装置受光部の不純物分布図および断面模式図、第２
図a,bは従来のＰウェル型固体撮像装置受光部の不純物
分布図および断面模式図である。 １……高濃度Ｎ型シリコン基板、２……低濃度Ｎ型エピ
タキシヤル層、3,23……低濃度Ｐ型層、4,24……Ｎ型領
域、５……低濃度Ｎ型シリコン基板。1A and 1B are an impurity distribution diagram and a schematic sectional view of a light receiving portion of a P-well type solid-state imaging device according to an embodiment of the present invention, and FIG.
1A and 1B are an impurity distribution diagram and a cross-sectional schematic diagram of a conventional P-well type solid-state imaging device light receiving portion. 1 ... High-concentration N-type silicon substrate, 2 ... Low-concentration N-type epitaxial layer, 3,23 ... Low-concentration P-type layer, 4,24 ... N-type region, 5 ... Low-concentration N-type silicon substrate .
Claims (1)
板の表面に、前記半導体基板と同一導電型を有するとと
もに前記半導体基板よりも低不純物濃度のエピタキシャ
ル層と、前記半導体基板と反対導電型の第１の半導体層
が順次形成され、前記反対導電型の半導体層の表面に前
記半導体基板と同一導電型の第２の半導体層が形成さ
れ、前記半導体基板と前記エピタキシャル層とで基板部
が形成され、前記第１の半導体層と前記第２の半導体層
とで受光部が形成されていることを特徴とする固体撮像
装置。1. An epitaxial layer having the same conductivity type as the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, and a conductivity type opposite to the semiconductor substrate, on a surface of a semiconductor substrate having one conductivity type and a high impurity concentration. First semiconductor layer is sequentially formed, a second semiconductor layer of the same conductivity type as the semiconductor substrate is formed on the surface of the semiconductor layer of the opposite conductivity type, and the semiconductor substrate and the epitaxial layer form a substrate portion. A solid-state imaging device, wherein a light receiving portion is formed by the first semiconductor layer and the second semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60271859A JPH073867B2 (en) | 1985-12-03 | 1985-12-03 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60271859A JPH073867B2 (en) | 1985-12-03 | 1985-12-03 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62131567A JPS62131567A (en) | 1987-06-13 |
| JPH073867B2 true JPH073867B2 (en) | 1995-01-18 |
Family
ID=17505880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60271859A Expired - Lifetime JPH073867B2 (en) | 1985-12-03 | 1985-12-03 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073867B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58193B2 (en) * | 1978-08-08 | 1983-01-05 | 日本電信電話株式会社 | Semiconductor optical detection device |
| JPS58125976A (en) * | 1982-01-22 | 1983-07-27 | Nec Corp | solid-state image sensor |
-
1985
- 1985-12-03 JP JP60271859A patent/JPH073867B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62131567A (en) | 1987-06-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6429039B2 (en) | Semiconductor device and method of manufacturing the same | |
| US4667392A (en) | Solid-state image sensor manufacturing process | |
| JPS61133659A (en) | Forming method for semiconductor element isolating region | |
| JPH0240956A (en) | Solid-state image sensing device | |
| JPH0715981B2 (en) | Solid-state imaging device | |
| US4697329A (en) | Method of manufacturing an antiblooming image sensor device | |
| JP3100663B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6286756A (en) | Optoelectric transducer | |
| JPS6123669B2 (en) | ||
| JP3048011B2 (en) | Charge-coupled device | |
| JPS62131567A (en) | solid-state imaging device | |
| JPS59161082A (en) | Semiconductor light-receptor | |
| KR930000905B1 (en) | Integrated device having surface epitaxial layer of highly doped impurity | |
| JPS6327865B2 (en) | ||
| JPS63142858A (en) | Solid-state image sensing device | |
| JPS6224665A (en) | Solid-state image pickup device | |
| JP2701180B2 (en) | Photodiode | |
| JP2936826B2 (en) | Solid-state imaging device | |
| JP2643431B2 (en) | Manufacturing method of high breakdown voltage semiconductor device | |
| JP2003174188A (en) | Optical semiconductor device and method of manufacturing the same | |
| JPH0428144B2 (en) | ||
| JPH02246230A (en) | Charge transfer device | |
| JPS63124567A (en) | Semiconductor device | |
| JPH0558256B2 (en) | ||
| JPH0555494A (en) | High-voltage mos ic |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |