JPH073868B2 - Light-receiving diode array - Google Patents
Light-receiving diode arrayInfo
- Publication number
- JPH073868B2 JPH073868B2 JP61010271A JP1027186A JPH073868B2 JP H073868 B2 JPH073868 B2 JP H073868B2 JP 61010271 A JP61010271 A JP 61010271A JP 1027186 A JP1027186 A JP 1027186A JP H073868 B2 JPH073868 B2 JP H073868B2
- Authority
- JP
- Japan
- Prior art keywords
- light
- light receiving
- semiconductor substrate
- receiving portion
- drain region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
Landscapes
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、受光ダイオードアレーに係り、特に、ホトダ
イオードアレーの受光部と受光部以外の領域との信号比
（以下、S/N比という）の改善に関するものである。The present invention relates to a photodiode array, and more particularly to a signal ratio (hereinafter referred to as S / N ratio) between a light receiving portion of a photodiode array and a region other than the light receiving portion. It is about the improvement of.
（従来の技術） 従来、１チップ中に受光部を複数個形成するホトダイオ
ードアレーの場合、S/N比を良くするために、受光部以
外をアルミニウムなどで形成した遮光膜で被覆し、受光
部以外の領域では光を感じさせないようにしていた。な
お、この種の先行技術としては、例えば、特公昭53−29
589号があげられる。(Prior Art) Conventionally, in the case of a photodiode array in which a plurality of light receiving portions are formed in one chip, in order to improve the S / N ratio, the light receiving portion other than the light receiving portion is covered with a light shielding film formed of aluminum or the like. I tried not to feel the light in other areas. Note that, as this type of prior art, for example, Japanese Patent Publication No. 53-29
No. 589 is given.
第４図は係る従来のホトダイオードアレーの平面図、第
５図は第４図のＶ−Ｖ線断面図である。FIG. 4 is a plan view of such a conventional photodiode array, and FIG. 5 is a sectional view taken along line VV of FIG.
このホトダイオードアレーでは受光部が３個の場合を示
している。図において、１は半導体基板、２は受光部で
ある半導体基板と反対導電型の不純物導入領域、３はア
ルミニウムなどにより形成された外部取り出しリードボ
ンディングパッド、４はアルミニウムなどにより形成さ
れた遮光膜、５は絶縁膜、６は受光部２と外部取り出し
リードボンディングパッド３をオーミック接触させるた
めのコンタクト穴である。This photodiode array shows the case where there are three light receiving portions. In the figure, 1 is a semiconductor substrate, 2 is an impurity introduction region of a conductivity type opposite to that of the semiconductor substrate which is a light receiving part, 3 is an external lead bonding pad formed of aluminum or the like, 4 is a light shielding film formed of aluminum or the like, Reference numeral 5 is an insulating film, and 6 is a contact hole for making ohmic contact between the light receiving portion 2 and the external lead lead bonding pad 3.
このホトダイオードアレーを動作させるには、半導体基
板１と外部取り出しリードボンディングパッド３の間に
PN接合の逆方向に電圧を印加して、通常のホトダイオー
ドとして動作させる。In order to operate this photodiode array, between the semiconductor substrate 1 and the external lead lead bonding pad 3.
A voltage is applied in the opposite direction of the PN junction to operate as a normal photodiode.
（発明が解決しようとする問題点） しかしながら、上記構成の装置では、半導体基板と各受
光部との間に電圧を順次印加していき、その時の各受光
部の出力電圧を順次検出する方法をとった場合は、出力
電圧を測定している受光部に光が照射されていなくて
も、他の受光部に光が照射されていると、それらの受光
部で発生した光励起キャリアが出力を測定している受光
部に流れ込み、S/N比が悪くなる（第６図参照）という
問題があった。なお、この点については、本発明との対
比において後述する。(Problems to be Solved by the Invention) However, in the device having the above-described configuration, a method of sequentially applying a voltage between the semiconductor substrate and each light receiving unit and sequentially detecting the output voltage of each light receiving unit at that time is provided. In this case, even if the light receiving unit that is measuring the output voltage is not illuminated, if other light receiving units are illuminated, the photoexcited carriers generated in those light receiving units measure the output. However, there is a problem that the S / N ratio deteriorates (see FIG. 6) when it flows into the light receiving part. Note that this point will be described later in comparison with the present invention.
本発明は、上記の問題点を除去し、S/N比及び応答特性
を向上し得る受光ダイオードアレーを提供することを目
的とする。It is an object of the present invention to eliminate the above-mentioned problems and provide a photodiode array that can improve the S / N ratio and response characteristics.
（問題点を解決するための手段） 本発明は、上記問題点を解決するために、１チップ上に
複数個受光部を形成するホトダイオードアレーにおい
て、半導体基板（１）上に長方形状に複数個形成され
る、半導体基板（１）と反対導電型の不純物導入領域か
らなる受光部（２）と、この受光部（２）の両側に長方
形状に複数個形成される、前記受光部（２）と同導電型
の不純物を導入してなるドレイン領域（７）と、前記受
光部（２）の長尺方向の一端部から導出され、前記半導
体基板（１）の一端部に形成される受光部外部取出しリ
ードボンディングパッド（３）と、前記複数個のドレイ
ン領域（７）の全てに電気的に接続され、かつ、前記ド
レイン領域（７）上及びその周辺を覆うとともに、前記
複数個の受光部（２）の外周を個別に微小絶縁距離を有
して包囲する遮光膜（９）と、この遮光膜（９）の一端
部から導出され、前記半導体基板（１）の一端部に形成
される単一のドレイン領域外部取り出しリードボンディ
ングパッド（８）とを設け、前記半導体基板（１）に所
定電位（＋5V）を付与し、前記受光部（２）に負荷（R
L）を接続し、前記ドレイン領域（７）をグランドに接
続するようにしたものである。(Means for Solving the Problems) In order to solve the above problems, the present invention provides a photodiode array in which a plurality of light receiving portions are formed on one chip, and a plurality of rectangular arrays are formed on a semiconductor substrate (1). A light-receiving portion (2) formed of an impurity introduction region having a conductivity type opposite to that of the semiconductor substrate (1), and a plurality of light-receiving portions (2) formed on both sides of the light-receiving portion (2) in a rectangular shape. A drain region (7) formed by introducing an impurity of the same conductivity type as that of the light receiving part, and a light receiving part formed at one end part of the semiconductor substrate (1), which is led out from one end part in the longitudinal direction of the light receiving part (2). The plurality of light receiving parts are electrically connected to the external extraction lead bonding pad (3) and all of the plurality of drain regions (7) and cover the drain region (7) and its periphery. Separate the outer circumference of (2) individually A light-shielding film (9) surrounding with an edge distance, and a single drain region external lead-out lead-out that is led out from one end of this light-shielding film (9) and is formed at one end of the semiconductor substrate (1). A pad (8) is provided, a predetermined potential (+ 5V) is applied to the semiconductor substrate (1), and a load (R) is applied to the light receiving unit (2).
L) and the drain region (7) is connected to the ground.
（作用） 本発明によれば、１チップ上に複数個受光部を形成する
ホトダイオードアレーにおいて、各受光部（２）間にド
レイン領域（７）となる受光部（２）と同導電型の不純
物導入領域を受光部（２）と接続しないように形成し、
かつドレイン領域（７）に独自に電圧が印加されるよう
にする。つまり、このホトダイオードアレーでは、ドレ
イン領域（７）が各受光部（２）間に形成されており、
そのドレイン領域（７）はグランドに接続されているた
め、ある受光部（２）以外の各受光部（２）で発生した
光励起キャリアはそのドレイン領域（７）に吸収するこ
とができる。このため、他の受光部で発生した光励起キ
ャリアの影響がなくなり、S/N比が改善される。また、
有効拡散長内の走行時間の大きいキャリアをドレイン領
域（７）が吸収するため、応答性が高まる。(Operation) According to the present invention, in a photodiode array in which a plurality of light receiving portions are formed on one chip, an impurity of the same conductivity type as the light receiving portion (2) which becomes the drain region (7) between each light receiving portion (2). The introduction region is formed so as not to be connected to the light receiving part (2),
In addition, the voltage is independently applied to the drain region (7). That is, in this photodiode array, the drain region (7) is formed between the light receiving portions (2),
Since the drain region (7) is connected to the ground, photoexcited carriers generated in each light receiving unit (2) other than a certain light receiving unit (2) can be absorbed in the drain region (7). Therefore, the influence of photoexcited carriers generated in other light receiving sections is eliminated, and the S / N ratio is improved. Also,
Since the drain region (7) absorbs carriers having a long transit time within the effective diffusion length, responsiveness is enhanced.
更に、遮光膜（９）によって受光部（２）を除いた領域
は、略遮光膜（９）によって覆い、しかも、この遮光膜
（９）の一端部から導出され、前記半導体基板（１）の
一端部に形成される単一のドレイン領域外部取り出しリ
ードボンディングパッド（８）とを設け、前記半導体基
板（１）に所定電位（＋5V）を付与し、前記受光部
（２）に負荷（RL）を接続し、前記ドレイン領域（７）
をグランドに接続するようにしたので、１チップ上の一
端部にリードボンディングパッドが形成され、そのリー
ドボンディングパッド数も少なくて済むので、ボンディ
ングパッドへのボンディングも容易である。Further, the region except the light receiving portion (2) by the light shielding film (9) is substantially covered with the light shielding film (9) and is led out from one end of the light shielding film (9) to be the semiconductor substrate (1). A single drain region external lead lead bonding pad (8) formed at one end is provided, a predetermined potential (+ 5V) is applied to the semiconductor substrate (1), and a load (RL) is applied to the light receiving unit (2). And the drain region (7)
Is connected to the ground, a lead bonding pad is formed at one end on one chip, and the number of the lead bonding pad is small, so that the bonding to the bonding pad is easy.
（実施例） 以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, the Example of this invention is described in detail, referring drawings.
第１図は本発明に係るホトダイオードアレーの一実施例
を示す平面図、第２図は第１図におけるII−II′線断面
図である。なお、第４図及び第５図に関して説明した部
分と同じ部分は同番号で示されている。FIG. 1 is a plan view showing an embodiment of a photodiode array according to the present invention, and FIG. 2 is a sectional view taken along the line II-II 'in FIG. The same parts as those described with reference to FIGS. 4 and 5 are designated by the same reference numerals.
図において、２は半導体基板１上に長方形状に複数個形
成される、半導体基板１と反対導電型の不純物導入領域
からなる受光部、７は長方形状に複数個形成される、受
光部２と同導電型の不純物導入領域からなるドレイン領
域、８は受光部２の長尺方向の一端部から導出され、半
導体基板１の一端部に形成される単一のドレイン領域外
部取り出しリードボンディングパッド、９は複数個のド
レイン領域７の全てに電気的に接続され、かつ、前記ド
レイン領域７上及びその周辺を覆うとともに、前記受光
部２の外周を個別に微小絶縁距離を有して包囲する、ド
レイン領域外部取り出しリードボンディングパッドに接
続するようにアルミニウムなどで形成した遮光膜、10は
ドレイン領域７と遮光膜９をオーミック接触させるコン
タクト穴である。これは、通常プレーナー拡散技術によ
り形成する。受光部２とドレイン領域７は同導電型であ
るため、同時に形成してもかまわない。In the figure, reference numeral 2 denotes a light receiving portion formed on the semiconductor substrate 1 in a rectangular shape, the light receiving portion including an impurity introduction region having a conductivity type opposite to that of the semiconductor substrate 1, and 7 a plurality of light receiving portions 2 formed in a rectangular shape. A drain region 8 formed of an impurity introduction region of the same conductivity type, a single drain region lead-out lead bonding pad 8 formed at one end of the semiconductor substrate 1 which is led out from one end of the light receiving portion 2 in the longitudinal direction. Is electrically connected to all of the plurality of drain regions 7, covers the drain region 7 and its periphery, and individually surrounds the outer periphery of the light receiving portion 2 with a minute insulating distance. A light-shielding film formed of aluminum or the like so as to be connected to the lead-out pad for taking out the region outside, and 10 is a contact hole for making ohmic contact between the drain region 7 and the light-shielding film 9. This is usually formed by the planar diffusion technique. Since the light receiving portion 2 and the drain region 7 have the same conductivity type, they may be formed at the same time.
このように、１チップ上に複数個受光部を形成するホト
ダイオードアレーにおいて、半導体基板１上に長方形状
に複数個形成される、半導体基板１と反対導電型の不純
物導入領域からなる受光部２と、この受光部２の両側に
長方形状に複数個形成される、前記受光部２と同導電型
の不純物を導入してなるドレイン領域７と、前記受光部
２の長尺方向の一端部から導出され、前記半導体基板１
の一端部に形成される受光部外部取出しリードボンディ
ングパッド３と、前記複数個のドレイン領域７の全てに
電気的に接続され、かつ、前記ドレイン領域７上及びそ
の周辺を覆うとともに、前記受光部２の外周を個別に微
小絶縁距離を有して包囲する遮光膜９と、この遮光膜９
の一端部から導出され、前記半導体基板１の一端部に形
成される単一のドレイン領域外部取り出しリードボンデ
ィングパッド８とを設け、図３に示すように、前記半導
体基板１に所定電位（＋5V）を付与し、前記受光部２に
負荷（RL）を接続し、前記ドレイン領域７をグランドに
接続するようにしている。なお、５は絶縁膜、６はコン
タクト穴である。As described above, in the photodiode array in which a plurality of light receiving portions are formed on one chip, a plurality of light receiving portions 2 formed in the rectangular shape on the semiconductor substrate 1 and including the impurity introduction regions of the opposite conductivity type to the semiconductor substrate 1. A plurality of rectangular-shaped drain regions 7 are formed on both sides of the light-receiving part 2 and are formed by introducing impurities of the same conductivity type as the light-receiving part 2 and one end of the light-receiving part 2 in the longitudinal direction. The semiconductor substrate 1
The lead-out pad 3 for taking out the light-receiving part formed at one end of the light-receiving part and all of the plurality of drain regions 7 are electrically connected, and cover the drain region 7 and its periphery, and the light-receiving part. A light-shielding film 9 which individually surrounds the outer periphery of 2 with a minute insulation distance, and this light-shielding film 9
And a single drain region external lead-out lead bonding pad 8 which is derived from one end of the semiconductor substrate 1 and is formed at one end of the semiconductor substrate 1, and the semiconductor substrate 1 is provided with a predetermined potential (+ 5V) as shown in FIG. Is applied, a load (RL) is connected to the light receiving portion 2, and the drain region 7 is connected to the ground. In addition, 5 is an insulating film and 6 is a contact hole.
上記のホトダイオードアレーの動作について、第３図を
用いて従来のホトダイオードアレーと対比しながら説明
する。ここでは、半導体基板１をｎ型、受光部２及びド
レイン領域７をｐ型として説明する。The operation of the above photodiode array will be described with reference to FIG. 3 in comparison with the conventional photodiode array. Here, the semiconductor substrate 1 will be described as n-type, and the light receiving portion 2 and the drain region 7 will be described as p-type.
第３図は本発明により得られたホトダイオードアレーの
特性測定説明図であり、第３図（ａ）はその測定特性
図、第３図（ｂ）はその測定回路図、第６図は従来のホ
トダイオードアレーの特性測定説明図であり、第６図
（ａ）はその測定特性図、第６図（ｂ）はその測定回路
図である。FIG. 3 is a diagram for explaining the characteristic measurement of the photodiode array obtained according to the present invention. FIG. 3 (a) is its characteristic measurement diagram, FIG. 3 (b) is its measuring circuit diagram, and FIG. 6A and 6B are explanatory views of characteristics measurement of a photodiode array, FIG. 6A is a measurement characteristic diagram thereof, and FIG. 6B is a measurement circuit diagram thereof.
ここで、ホトダイオードアレーの測定方法は、光源の光
を受光部内に十分おさまるようにしぼり込み、ホトダイ
オードアレー上を走査させる。つまり、例えば、第３図
（ｂ）及び第６図（ｂ）に示される受光部へのバイア
スを順次受光部そして受光部へとスキャンする。こ
の時、ホトダイオードアレーには、ｎ型半導体基板側に
＋5V、受光部にのみ負荷抵抗RLを介して接地する。更
に、本発明のホトダイオードアレーにおいてはドレイン
領域７を接地する。出力信号の取り出しは受光部に接
地した負荷抵抗RLの両端で検出する。Here, in the method of measuring the photodiode array, the light from the light source is sufficiently narrowed down within the light receiving portion, and the photodiode array is scanned. That is, for example, the bias to the light receiving portion shown in FIG. 3 (b) and FIG. 6 (b) is sequentially scanned to the light receiving portion and the light receiving portion. At this time, the photodiode array is grounded at + 5V on the n-type semiconductor substrate side and only the light receiving portion is grounded via the load resistor RL. Further, in the photodiode array of the present invention, the drain region 7 is grounded. The extraction of the output signal is detected by both ends of the load resistor RL grounded to the light receiving part.
従来のホトダイオードアレーでは受光部に光が照射さ
れなくても、他の受光部に光が照射されると、第６図
（ａ）に示される様に、受光部下及び受光部下で発
生した、この場合ホールが受光部に少数キャリアの拡
散により流れ込み、受光部で出力電圧が検出される。
なお、第３図（ａ）及び第６図（ａ）において、横軸は
距離ｌ、縦軸Ｖは受光部のトータル電圧を示している。In the conventional photodiode array, even if the light receiving portion is not irradiated with light, when the other light receiving portion is irradiated with light, as shown in FIG. 6A, the light is generated under the light receiving portion and under the light receiving portion. In this case, holes flow into the light receiving section due to the diffusion of minority carriers, and the output voltage is detected at the light receiving section.
In FIGS. 3 (a) and 6 (a), the horizontal axis represents the distance 1 and the vertical axis V represents the total voltage of the light receiving portion.
本発明により得られたホトダイオードアレーでは、ドレ
イン領域が各受光部間に形成されており、かつ、グラン
ドに接続されているため、受光部及び受光部で発生
した光励起キャリアはドレイン領域に吸収することがで
きる。In the photodiode array obtained by the present invention, since the drain region is formed between the light receiving portions and is connected to the ground, the photoexcited carriers generated in the light receiving portion and the light receiving portion should be absorbed in the drain region. You can
このため、第３図（ａ）に示されるように、受光部で
検出される出力信号は、他の受光部及びで発生した
光励起キャリアの影響がなくなり、受光部で発生する
光励起キャリアによるものだけとなり、S/N比が改善さ
れる。Therefore, as shown in FIG. 3 (a), the output signal detected by the light receiving section is not affected by the photoexcited carriers generated in the other light receiving sections and only by the photoexcited carriers generated in the light receiving section. And the S / N ratio is improved.
前記実施例においては、PN構造のホトダイオードアレー
を用いて説明したが、PIN構造のホトダイオードアレー
であっても良いことは言うまでもなく、また、半導体の
導電型についても指定して説明したが、これは全て逆導
電型としても良いことは言うまでもない。In the above-mentioned embodiment, the photodiode array of the PN structure is used for explanation, but it goes without saying that the photodiode array of the PIN structure may also be used, and the conductivity type of the semiconductor is also specified and explained. It goes without saying that all may be of opposite conductivity type.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。The present invention is not limited to the above embodiment,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果） 以上、詳細に説明したように、本発明によれば、１チッ
プ上に複数個出力を形成するホトダイオードアレーにお
いて、半導体基板上に長方形状に複数個形成される、半
導体基板と反対導電型の不純物導入領域からなる受光部
と、該受光部の両側に長方形状に複数個形成される、前
記受光部と同導電型の不純物を導入してなるドレイン領
域と、前記受光部の長尺方向の一端部から導出され、前
記半導体基板の一端部に形成される受光部外部取出しリ
ードボンディングパッドと、前記複数個のドレイン領域
の全てに電気的に接続され、かつ、前記ドレイン領域上
及びその周辺を覆うとともに、前記複数個の受光部の外
周を個別に微小絶縁距離を有して包囲する遮光膜と、該
遮光膜の一端部から導出され、前記半導体基板の一端部
に形成される単一のドレイン領域外部取り出しリードボ
ンディングパッドとを設け、前記半導体基板に所定電位
を付与し、前記受光部に負荷を接続し、前記ドレイン領
域をグランドに接続するようにしたので、 出力信号検出を行っている受光部においては、その受光
部以外の受光部に入射する光により発生した光励起キャ
リアの影響はなくなり、S/N比を大幅に改善することが
できる。(Effects of the Invention) As described in detail above, according to the present invention, in a photodiode array in which a plurality of outputs are formed on one chip, a plurality of rectangular semiconductor substrates are formed on a semiconductor substrate. A light receiving portion formed of an impurity introduction region of an opposite conductivity type, a plurality of rectangular regions formed on both sides of the light receiving portion, the drain region being formed by introducing impurities of the same conductivity type as the light receiving portion, and the light receiving portion of the light receiving portion. A light receiving portion external lead-out lead bonding pad that is led out from one end portion in the longitudinal direction and is formed at one end portion of the semiconductor substrate, and is electrically connected to all of the plurality of drain regions, and on the drain region. And a light-shielding film that covers the periphery of the light-receiving portion and individually surrounds the outer periphery of the plurality of light-receiving portions with a minute insulating distance, and is guided from one end portion of the light-shielding film to one end portion of the semiconductor substrate. A single drain region to be formed is connected to the outside to form a lead bonding pad, a predetermined potential is applied to the semiconductor substrate, a load is connected to the light receiving portion, and the drain region is connected to the ground. In the light receiving section that is performing signal detection, the influence of the photoexcited carriers generated by the light incident on the light receiving sections other than the light receiving section is eliminated, and the S / N ratio can be significantly improved.
同時に有効拡散長内の走行時間の大きいキャリアをドレ
イン領域が吸収するため、応答特性の向上を図ることが
できる。At the same time, the drain region absorbs carriers having a long transit time within the effective diffusion length, so that the response characteristics can be improved.
更に、１チップ上の一端部にリードボンディングパッド
が形成され、そのリードボンディングパッド数も少なく
て済むとともに、ボンディングパッドへのボンディング
も容易である。Further, a lead bonding pad is formed at one end on one chip, the number of lead bonding pads is small, and bonding to the bonding pad is easy.
第１図は本発明に係るホトダイオードアレーの平面図、
第２図は第１図におけるII−II′線断面図、第３図は本
発明のホトダイオードアレーの特性測定説明図、第４図
は従来のホトダイオードアレーの平面図、第５図は第４
図におけるＶ−Ｖ′線断面図、第６図は従来のホトダイ
オードアレーの特性測定説明図である。 １…半導体基板、２…受光部、３…受光部外部取り出し
リードボンディングパッド（受光部用）、５…絶縁膜、
6,10…コンタクト穴、７…ドレイン領域、８…ドレイン
領域外部取り出しリードボンディングパッド、９…遮光
膜。FIG. 1 is a plan view of a photodiode array according to the present invention,
2 is a sectional view taken along the line II-II 'in FIG. 1, FIG. 3 is an explanatory view of characteristics measurement of the photodiode array of the present invention, FIG. 4 is a plan view of a conventional photodiode array, and FIG.
FIG. 6 is a sectional view taken along the line VV 'in FIG. 6, and FIG. 6 is an explanatory view of characteristics measurement of a conventional photodiode array. 1 ... Semiconductor substrate, 2 ... Light receiving part, 3 ... Light receiving part external extraction lead bonding pad (for light receiving part), 5 ... Insulating film,
6, 10 ... Contact hole, 7 ... Drain region, 8 ... Drain region external extraction lead bonding pad, 9 ... Light-shielding film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉村 久乗 東京都武蔵野市吉祥寺南町１丁目27番１号 吉祥寺パインクレストビル エヌ・テ イ・テイ技術移転株式会社内 (56)参考文献 特開 昭48−81494（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kumura Yoshimura 1-27-1, Kichijoji Minamimachi, Musashino City, Tokyo Kichijoji Pine Crest Building NTTay Technology Transfer Co., Ltd. (56) References 48-81494 (JP, A)
Claims (1)
ダイオードアレーにおいて、 （ａ）半導体基板上に長方形状に複数個形成される、半
導体基板と反対導電型の不純物導入領域からなる受光部
と、 （ｂ）該受光部の両側に長方形状に複数個形成される、
前記受光部と同導電型の不純物を導入してなるドレイン
領域と、 （ｃ）前記受光部の長尺方向の一端部から導出され、前
記半導体基板の一端部に形成される受光部外部取出しリ
ードボンディングパッドと、 （ｂ）前記複数個のドレイン領域の全てに電気的に接続
され、かつ、前記ドレイン領域上及びその周辺を覆うと
ともに、前記複数個の受光部の外周を個別に微小絶縁距
離を有して包囲する遮光膜と、 （ｅ）該遮光膜の一端部から導出され、前記半導体基板
の一端部に形成される単一のドレイン領域外部取り出し
リードボンディングパッドとを設け、 （ｆ）前記半導体基板に所定電位を付与し、前記受光部
に負荷を接続し、前記ドレイン領域をグランドに接続す
ることを特徴とする受光ダイオードアレー。1. A photodiode array having a plurality of light receiving portions formed on one chip, comprising: (a) a plurality of light receiving portions formed in a rectangular shape on a semiconductor substrate, the light receiving portion having an impurity introduction region of a conductivity type opposite to that of the semiconductor substrate. And (b) a plurality of rectangular shapes are formed on both sides of the light receiving portion.
A drain region formed by introducing an impurity having the same conductivity type as that of the light-receiving portion, and (c) a light-receiving-portion lead-out lead which is derived from one end portion of the light-receiving portion in the longitudinal direction and is formed at one end portion of the semiconductor substrate. A bonding pad, and (b) is electrically connected to all of the plurality of drain regions, covers the drain region and the periphery thereof, and individually provides a minute insulating distance to the outer periphery of the plurality of light receiving portions. A light-shielding film having and surrounding the light-shielding film; and (e) a single drain region external lead-out lead bonding pad that is derived from one end of the light-shielding film and is formed at one end of the semiconductor substrate. A light-receiving diode array, characterized in that a predetermined potential is applied to a semiconductor substrate, a load is connected to the light-receiving portion, and the drain region is connected to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010271A JPH073868B2 (en) | 1986-01-22 | 1986-01-22 | Light-receiving diode array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010271A JPH073868B2 (en) | 1986-01-22 | 1986-01-22 | Light-receiving diode array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62169476A JPS62169476A (en) | 1987-07-25 |
| JPH073868B2 true JPH073868B2 (en) | 1995-01-18 |
Family
ID=11745650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61010271A Expired - Fee Related JPH073868B2 (en) | 1986-01-22 | 1986-01-22 | Light-receiving diode array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073868B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2676814B2 (en) * | 1988-09-07 | 1997-11-17 | 株式会社ニコン | Multi-type light receiving element |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5213918B2 (en) * | 1972-02-02 | 1977-04-18 |
-
1986
- 1986-01-22 JP JP61010271A patent/JPH073868B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62169476A (en) | 1987-07-25 |
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