JPH0744417B2 - Noise cancellation circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a noise canceling circuit of a magnetic recording / reproducing apparatus, for example.

[Technical background of the invention]

Generally, in a magnetic recording / reproducing device (hereinafter referred to as a VTR), when recording a video signal on a magnetic tape and reproducing it, the S / N ratio of the reproduced signal (modulation noise, sliding noise, reproduction amplification noise, etc.) Signal-to-noise ratio) deteriorates. Therefore, the S / N of the reproduced signal is passed through the noise cancel circuit.
We are trying to improve the ratio. This noise cancel circuit is shown in FIG. The operation of this circuit will be described below with reference to FIG. 2 which shows operation waveforms at various points in the circuit of FIG.

The reproduced video signal input from the terminal (1) is shown in Fig. 2 (A).
It is supposed to contain noise as shown in. This signal is input to the delay device (2) and the high pass filter (HPF) (3). The output of the HPF (3) is as shown in FIG. 2 (B), where the noise component of the signal is extracted. However, the high frequency component SH of the signal is also extracted at the same time. The amplifier (4) and the limiter (5) extract only the noise component from the noise component and the high frequency component of the signal. Here, if the input conversion limiter level at the input end of the amplifier (4) is V _L , However, V _L ′ is the input conversion limiter level of the limiter (5), and G _A is the gain of the amplifier (4).

Becomes This input conversion limiter level V _L is shown in FIG. 2 (B).
As shown in FIG. 7, if the noise level pp (peak to peak) value is selected to be slightly larger than the noise level, a noise component and a slight signal high frequency component are obtained at the output of the limiter (5).
By subtracting the output of the limiter (5) from the reproduced video signal that has passed through the delay device (2) by the subtractor (6),
A reproduced video signal output from which noise has been removed is obtained from the terminal (7) (see FIG. 2 (C)). The delay device (2) is here used to time the two inputs to the subtractor (6). That is, τ _DL = τ _HPF + τ _A , where τ _DL , τ _HPF , τ _A , and τ _L are signal delay times in the delay device (2), HPF (3), amplifier (4), and limiter (5), respectively. The delay time of the delay device (2) is determined so that + τ _L (2) holds.

By the way, in the noise cancel circuit of FIG. 1, the following conditions may be satisfied in order to most effectively remove the noise and minimize the distortion of the reproduced video signal. That is, assuming that the input ratio to the subtractor (6) is 1: 1, the equation (2) and V _L = Np−p (3) G _HPF・ G _A・ G _L (= G) = G _DL (4 ) It is necessary to satisfy the above expressions (3) and (4). Here, Np-p is the p-p value of noise in the reproduced video signal, and G _HPF , G _L , and G _DL are the gain in the pass band of HPF (3), the gain of the limiter (5), and It is the transmission gain of the delay device (2). If the above conditions are not met, for example
When V _L > Np-p, the noise is completely removed, but the amount of high-frequency components of the signal removed is large, and the reproduced waveform is rounded. Further, when V _L <Np-p, noise is not completely removed. Similarly, when G ≠ G _DL , the noise is not completely removed.

As described above, in order to effectively operate the noise cancel circuit, it is necessary to satisfy both expressions (3) and (4).

[Problems of background technology]

By the way, when the above-described noise-cancell circuit is to be integrated into a semiconductor integrated circuit, the above gains G _A and G _L vary due to variations in the elements in the integrated circuit. Therefore, it is extremely difficult to exactly satisfy the expressions (3) and (4). Therefore, it is necessary to compensate for this variation. Since the limiter operation is usually performed by the differential amplifier in the integrated circuit, the input conversion limiter level V _L ′ of the limiter (5) in the equation (1) becomes a constant value, and the equations (3) and (4) are satisfied. Has gain G _A , G _L
Both need to be controlled. (Equations (3) and (4) are related by equation (1), and V _L and G cannot be changed independently.) However, in this case, 2
Requires two terminals.

On the other hand, it is also considered that one of the gains G _{A and} G _L is externally controlled by using one terminal so that the noise cancellation effect is not perfect but the following is achieved. There are drawbacks. That is, when the noise level becomes smaller due to improvement of the tape or video head, etc., or combination with other S / N improvement devices, the amplifier (4)
It is possible to further improve the image quality by reducing the input conversion limiter level V _L at the input end of. However,
Only V _{L in} equation (3) cannot be changed independently.
That is, one control terminal cannot satisfy the expressions (3) and (4) at the same time, and eventually two control pins are required to cope with the above system change.

[Object of the Invention]

The present invention has been made in view of the above points, and provides a noise cancel circuit using a limiter circuit that can arbitrarily set only an input-converted limiter level without changing a gain by a control input from one terminal. To aim.

[Outline of Invention]

In a noise canceling circuit according to the present invention, a limiter circuit in the circuit is provided with a gain control amplifier whose gain decreases (or increases) with an increase (or decrease) of a control voltage (or current), and the control voltage (or current). The gain is increased (or decreased) with an increase (or a decrease) and the input-referred limiter level is constant, and the gain control limiter is connected to the input-referred limiter level (that is, the above-mentioned Only the input conversion limiter level at the input end of the amplifier) can be arbitrarily set.

Example of Invention

 An embodiment of the present invention will be described below with reference to FIG.

FIG. 3 is a block diagram showing an embodiment of the limiter circuit according to the present invention, and (10) is a limiter input terminal.
(11) is a gain control amplifier, and (12) is a gain control limiter connected to this amplifier. Both are controlled by the control voltage source (13). (14) is a control pin,
(15) is an output terminal.

The gain control amplifier (11) has a characteristic that the gain decreases (or increases) as the control voltage (V _C ) increases (or decreases), and the gain control limiter (12) increases (or decreases) the control voltage (V _C ). Gain increases (or decreases) with decreasing,
Moreover, it has a characteristic that the input conversion limiter level is constant. The gain of the gain control amplifier (11) is G _A (V _C ), the gain of the gain control limiter (12) is G _L (V _C ), the input conversion limiter level is V _L ′, the total gain is G _T , the amplifier Set the input conversion limiter level at the input end of (11) to V _L
Then, G _T = G _A (V _C ) · G _L (V _C ) (5) V _L = V _L ′ / G _A (V _C ) (6) Here, if G _{T in the} equation (5) is always constant with respect to the value of V _C within a certain range, the limiter circuit of FIG.
The input conversion limiter level V _L can be arbitrarily set depending on the value of V _C. Further, the gain is constant at the value of V _{C in} the above range. An example of this characteristic is shown in FIG. Here, as the gain-gain control amplifier, an example using a gain control amplifier having a characteristic that the gain increases as the control voltage increases and a gain control limiter having a characteristic that the gain decreases as the control voltage increases is shown. In FIG. 4, the horizontal axis is the control voltage V _C , and the vertical axes are G _T and G _A , G _L , V _L , V
Indicates the value of _L '. Further, a is a graph of GT in the expression (5), and b and c are graphs of G _A and G _{L in} the same expression (5). Further, d is a graph of V _{L in} the equation (6), and e is a graph of V _L ′ in the equation (6). The control voltage source (13) in FIG. 3 may be replaced with a control current source.

According to the configuration of FIG. 3 above, one terminal (in this case,
With the control input (V _C ) from the control pin (14), only the input conversion limiter level (V _L ) can be arbitrarily set without changing the gain (G _T ) of this circuit. Therefore, it is suitable for use in a noise cancel circuit.

FIG. 5 is a circuit diagram showing an embodiment in which the limiter circuit according to the present invention is applied to a noise cancel cell circuit.

First, the configuration of this circuit will be described. (20) is an integrated circuit, and (21) to (25) are pins of this integrated circuit (20). (26) is an input signal source, (27) is a delay device connected to it, and (28) is also an HPF connected to the signal source (26) via pin (25). Further, (29) is an output terminal of the noise-cancell circuit. Furthermore (3
0), (31), and (32) are current sources, and their current values are I ₁ , I ₂ , and I ₃ , respectively. In this circuit, the transistors Q ₁ through Q _5, resistors R ₁ to R ₅ and the external resistor R _C constitute a current mirror circuit by connexion current value to the value of the resistor R _C is determined, the transistor Q _6, Q _7, resistors R ₈ constitutes a Atsuteneta the Yotsute gain is determined on the current value of the current mirror circuit. Also transistors
Q ₉ , Q ₁₀ , resistors R ₁₀ , R ₁₁ and the current source (30) form a differential amplifier, and the transistors Q ₁₁ , Q ₁₂ , current sources (31), (32) form an emitter follower circuit. Further, the transistors Q ₁₃ , Q ₁₄ , the resistors R ₁₂ , R ₁₃ and the transistor Q ₁₅ constitute a limiter whose gain is determined by the current value of the current mirror circuit. The resistors R ₁₂ , R ₁₃ and the transistor Q ₁₅ also function as a subtractor.

Next, the operation of this circuit as a noise cancel circuit will be described. The signal V _I (playback luminance signal) from the input signal source (26) passes through the delay device (27), the transistor Q ₁₅ , and the resistor R.
It is output to the output terminal (29) through the line ₁₃ . On the other hand, the signal V _I of the input signal source (26) also passes through the pin (25), HPF (28), pin (24), and limiter circuit and is output to the output terminal (29) in reverse phase. At this time, the signal on the delay device (27) side and the HPF (2
The signal on the 8) side is added by the resistor R ₁₃ . That is, the output V ₀ to the terminal (29) is V ₀ = {| G _DL | Lθ _DL ＋ | G _HPF ｜ ・ G _T | L (θ _HPF + θ _T )}
V _I (7) where | G _DL |, G _HPF |, G _T | are delay units (27) and HP, respectively.
F (28) is the absolute value of the transmission gain of the limiter circuit, and θ _DL , θ _HPF and θ _T are the delay device (27) and HPF (2
8), the phase shift amount of the limiter circuit. Therefore, if the condition of | G _DL | = | G _HPF | ・ | G _T | (8) θ _DL =-(θ _HPF + θ _T (9) is satisfied, the output V to the output terminal (29) is _The noise component (HPF (28) from the signal V _I of the input signal source (26) is set to _0.
A signal having a frequency that passes through and a component whose level is lower than the input conversion limiter level V _L of the pin (24) can be taken out.

Therefore, here, the gain from the pin (24) to the output terminal (29) is divided into the gain G _A before the limiter input of the transistors Q ₁₃ and Q ₁₄ and the gain G _L after the limiter input, and is calculated. However, in the following calculation, the emitter ground current amplification factor β of the transistor is calculated as infinity. G _A and G _L are calculated as follows. That is, for G _A , an attenuator composed of the internal emitter resistance of the transistor Q ₆ , the series resistance of the resistor R ₈ , and the internal emitter resistance of the transistor Q ₇ ,
And transistors Q ₉ and Q ₁₀ and their load resistances R ₁₀ and R
Considering the differential amplifier composed of ₁₁ , it is found as in equation (10), and for G _L , the transistors Q ₁₃ and Q ₁₄
Considering a differential amplifier composed of the load resistances R ₁₂ and R ₁₃ , and the load resistances R ₁₂ and R ₁₃ , it is obtained as shown in equation (11).

However, here and in the future, re _n (n = 1,2, ...) Indicates the emitter internal resistance of the transistor Q _n , and 2 is multiplied by the equation (10) is the output of the transistors Q ₉ and Q ₁₀ . Is transmitted as a differential signal to the inputs of the transistors Q ₁₃ and Q ₁₄ .

Here, if R ₁ = R ₂ = R ₃ = R ₄ = 2R ₅ (12), However, I _Cn (n = 1, ..., 5) becomes the collector current of the transistor Q _n . Therefore, re ₆ = re ₇ = re ₈ = re ₁₃ = re ₁₄ (= re) (14), and all of them are set as re. Since re ₉ = re ₁₀ , re ₉ + re ₁₀ = 2re ′ (15). Substituting equations (14) and (15) into equations (10) and (11), However, re = V _T / I _C , I _C = I _C1 = I _C2 = I _C3 = I _C4 = re ′ ＝ 2V _T / I ₁ V _T = k _T / q (k: Boltzmann constant, T: absolute temperature, q: electron charge). Note that R ₈ >> 2re in equation (16). In an actual circuit, it is easy to set R ₈ >> 2re within a certain I _C range. Here, when the input conversion limiter level V _L at pin (24) and the gain G _T from pin (24) to the output terminal (29) are obtained from equations (16) and (17), However, V _L ′ is 8 V _T which is the pp value of the input conversion limiter level at the base input terminals of the transistors Q ₁₃ and Q ₁₄ , and V _BEI is the base-emitter voltage drop of the transistor Q ₁ .

Becomes That is, as can be seen from equation (18), the pin (2
The input conversion limiter level V _L in 4) can be set arbitrarily by changing the value of the external resistance R _C , and at that time (19)
As can be seen from the equation, the gain G _T from the pin (24) to the output terminal (29) is constant regardless of the value of the resistor R _C.

As described above, the noise cancel circuit shown in FIG. 5 changes the value of the resistance R _C attached to the single pin (22), thereby making the relationship between the equations (8) and (9) The input conversion limiter level V _L at pin (24) can be changed without any change. Therefore, by selecting the value of the resistor R _C according to the noise level included in the input signal V _I , a good noise canceling effect can be obtained even in a system having different noise levels.

〔The invention's effect〕

As described above, according to the present invention, a gain control amplifier whose gain decreases (or increases) with an increase (or decrease) of a control voltage (or current) and an increase (or decrease) of a control voltage (or current) as well. By connecting the gain control limiter whose gain increases (or decreases) and the input conversion limiter level is constant at this time, the overall gain is fixed by changing the control voltage (or current). It is possible to provide a noise canceling circuit using a limiter circuit that can freely set only the input-converted limiter level maintained at.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional noise-cancell circuit, FIG. 2 is a diagram showing waveforms at various parts of the circuit of FIG. 1, and FIG. 3 is a block diagram showing one embodiment of a limiter circuit according to the present invention. The figure is a diagram showing a characteristic example of the circuit of FIG.
FIG. 5 is a circuit diagram showing an embodiment of the noise cancel circuit of the present invention. 11 ... Gain control amplifier, 12 ... Gain control limiter, 13 ...
... control voltage source.

Claims (1)

[Claims] 1. A delay circuit which receives a video signal and delays the same, a band limiting filter which also receives the video signal, a limiter circuit connected to the latter stage of the band limiting filter, and an output of the delay circuit. And a subtractor for subtracting the output of the limiter circuit from the limiter circuit, the limiter circuit is controlled by a control voltage (or current).
Gain control amplifier whose gain decreases (or increases) with increase (or decrease), and which is cascaded to this gain control amplifier and whose gain increases (or decreases) with increase (or decrease) of the control voltage (or current). And a gain control limiter having a constant input conversion limiter level, and the input conversion limiter level at the input end of the gain control amplifier is set substantially according to the noise level included in the input video signal. A noise canceling circuit characterized in that