JPH0748198B2 - Multiprocessor system - Google Patents

Description

The present invention relates to a master-slave multiprocessor system including a master processor and a plurality of slave processors, and when an abnormality occurs on the slave processor, the slave processor itself. Relates to a multiprocessor system for performing abnormal processing.

Recently, computer systems are required to have higher speed. Therefore, multiprocessor systems that can execute each processing in a decentralized manner have been widely used. In such a multiprocessor system, it is necessary to reduce the processing and guarantee the operation of the system when an abnormality occurs.

[Conventional technology]

As one of the multiprocessor systems, there is a master-slave type multiprocessor system in which one master processor and a plurality of slave processors are connected by a common bus. In this type of system, the master processor issues instructions to each slave processor, and each slave processor implements distributed processing.

Conventionally, in a master-slave type multiprocessor system, when an error occurs on the slave processor,
The control as shown in FIG. 6 was performed.

In the example shown in FIG. 6A, when an abnormality occurs in the slave processor 11, an abnormality notification interrupt is issued to the master processor 10, and the master processor 10 resets the slave processor 11 in response to the abnormality notification.

In the example shown in FIG. 6B, when the master processor 10 accesses the slave processor 11 and the slave processor 11 does not respond, the master processor 10 recognizes that an abnormality has occurred in the slave processor 11, Reset the slave processor 11.

FIG. 7 shows an example of abnormality processing for the example shown in FIG.

In the slave processor 11, if an error occurs during software execution, an error notification interrupt is issued to the master processor 10. In response to this interrupt, the master processor 10 interrupts the processing by the software currently being executed and sends a system reset signal to the slave processor 11. After that, execution of the interrupted software is resumed.

In the slave processor 11, the firmware starts to operate by resetting and reset processing is performed. In this process, each part such as an input / output port is initialized, and after the initialization is completed, a process request instruction from the master processor 10 is waited for.

The same applies to the abnormality processing for the example shown in FIG.

[Problems to be Solved by the Invention]

According to the above-described conventional method, when the slave processor 11 has an abnormality, the master processor 10 must be interposed, which increases the processing load of the master processor 10. Also, when trying to recover the slave processor 11, the master processor 10 sends a system reset.
There is a problem that the operation of the slave processor 11 after restoration cannot be guaranteed because the cause of the abnormality is cleared and remains. In the case of an abnormality that cannot be cleared by system reset, the abnormality processing between the master processor 10 and the slave processor 11 is repeated many times.

An object of the present invention is to solve the above problems, to reduce the processing load on the master processor when a slave processor error occurs, and to guarantee the operation of the slave processor after recovery.

[Means for Solving the Problems]

 FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, 10 is a master processor, 11-1 to 11
-N is a slave processor, 12 is an automatic reset generation circuit,
13 is an abnormality factor storage circuit, 14 is a microprocessor (MP
U), 15 is firmware consisting of fixed instructions, 1
Reference numeral 6 represents an automatic recovery control unit, 17 represents a common bus, and 18 represents a common memory which can be commonly accessed by the master processor 10 and the slave processors 11-1 to 11-n.

This system includes a master processor 10, a plurality of slave processors 11-1 to 11-n, and a common memory on a common bus 17.
18 slaves are connected to each slave processor 11-1 to 11-n
Are processed according to an instruction from the master processor 10.

Each of the slave processors 11-1 to 11-n has a microprocessor 14 that fetches and executes an instruction, an automatic reset generation circuit 12, and an abnormality factor storage circuit 13. It also has an automatic recovery control unit 16 configured by the firmware 15.

The automatic reset generation circuit 12 is a circuit that monitors the occurrence of an error in its own processor and automatically resets the own processor when an error occurs.

The abnormality factor storage circuit 13 is a circuit that logs status information when an abnormality occurs.

The automatic restoration control unit 16 is configured by the firmware 15 which starts its operation by resetting, and the abnormality factor saving circuit 13
Based on the status information logged by, the cause of abnormality is determined, restart is performed if recovery is possible, and control is performed to stop processing by the microprocessor 14 if recovery is not possible.

[Action]

When an abnormality such as a hangup occurs, each of the slave processors 11-1 to 11-n resets itself except for the abnormality cause storage circuit 13 by the automatic reset generation circuit 12, and then the automatic restoration control unit 16 by the firmware 15 According to the above, the cause of the abnormality is determined, and if the recovery is possible, the recovery process is performed by itself without the intervention of the master processor 10. If it is not possible, notify the master processor 10,
Stop.

As a result, the processing load on the master processor 10 is eliminated from the occurrence of an abnormality in the slave processors 11-1 to 11-n to the restoration, and the operation after restoration can be guaranteed by determining the cause of the abnormality.

〔Example〕

2 is a block diagram of an embodiment of the present invention, FIG. 3 is a configuration example of an automatic reset generation circuit according to an embodiment of the present invention, and FIG.
FIG. 5 is a time chart of the automatic reset generation circuit shown in FIG. 3, and FIG. 5 is a process explanatory diagram of one embodiment of the present invention.

In FIG. 2, the same reference numerals as those in FIG. 1 correspond to those shown in FIG. 1, 20 is an abnormality occurrence monitoring circuit for monitoring abnormality occurrence in the slave processor, and 21 is an automatic reset signal upon abnormality detection. Automatic reset creation circuit, 2
2 is an automatic reset flag that stores the fact that an automatic reset has been performed in its own processor, 23 is a read-only memory (ROM), 24 is an abnormality occurrence notification terminal that notifies the abnormality of the microprocessor 14 to the outside, 25 Is a reset terminal, 26 is an external circuit including various circuits such as a common bus interface that configures the slave processor 11, 27 is a logging flag that enables logging in the error factor saving circuit 13, 28 is a logging flag 27 that includes an error factor A logging register 29 for storing hardware information represents an internal bus.

The abnormality occurrence monitoring circuit 20 monitors the abnormality occurrence notification terminal 24 for notifying a hang-up of the microprocessor 14 or the like, and when detecting an abnormality, outputs an abnormality detection signal to the automatic reset creation circuit 21. The automatic reset generation circuit 21 outputs an automatic reset signal and sets the automatic reset flag 22 according to the abnormality detection signal.

The automatic reset signal is input to the reset terminal 25 of the microprocessor 14 and the external circuit 26, and resets the microprocessor 14 and various circuits of the external circuit 26 except the abnormality factor storage circuit 13.

The error factor saving circuit 13 always collects the hardware information of the internal bus 29 and the like in the logging register 28, and when the logging flag 27 is set due to the occurrence of an error, the contents of the logging register 28 at that time are saved. Logging is enabled.

The microprocessor 14 normally executes a software program stored in a local memory (not shown) or the like. When a reset signal is input to the reset terminal 25, the execution control is transferred to the firmware 15 stored at a predetermined address of the ROM 23, and the automatic recovery control unit 16 including a fixed instruction group starts the reset process. At this time, the automatic reset flag 22 is determined to determine whether to perform the conventional reset processing by the system reset from the master processor 10 or the automatic reset processing according to the present invention.

In the case of automatic reset processing, the logging information in the logging register 28 is saved in the common memory 18. After that, referring to the logging information in the common memory 18, determine the cause of the error,
If restarting is possible, the microprocessor 14 and the external circuit 26 are set according to the logging information, and software processing is restarted. If it cannot be restarted, the slave processor 11 is stopped and the slave processor 11 is logically separated from the master processor 10.

FIG. 3 shows a detailed circuit configuration example of the automatic reset generation circuit 12 shown in FIG. FIG. 4 is a time chart for explaining the operation. Signals shown in FIG.
Correspond to the signals 1 to 3 shown in FIG.

When the abnormality detection signal is validated by the abnormality occurrence monitoring circuit 20, the D flip-flop 30 and the AND circuit 31 output a signal indicating its rise, and the JK flip-flop 32 and the JK flip-flop 33 are set. The JK flip-flop 33 corresponds to the automatic reset flag 22.

The output signal set by the JK flip-flop 32 is an automatic reset signal and is input to the timer 34 and the OR circuit 35. The output of the OR circuit 35 resets the microprocessor 14 shown in FIG. 2 and the external circuit 26 excluding the abnormality factor storage circuit 13. The logging flag 27 is also set by the output signal of the JK flip-flop 32 or the like.

Further, when the JK flip-flop 32 is set, the timer 34 composed of a counter is started, and a time-out signal is output after a lapse of a predetermined time. As a result, the JK flip-flop 32 is reset and the automatic reset ends.

When the automatic reset operation is completed, the microprocessor 14 shown in FIG. 2 starts the operation of the firmware 15,
ON / O of automatic reset flag 22 (JK flip-flop 33)
Depending on FF, automatic reset processing or conventional reset processing is performed. In the automatic reset process, the automatic reset flag 22 is turned off by the signal.

Since the abnormality occurrence monitoring circuit 20, the abnormality factor storage circuit 13 and the like shown in FIG. 2 can be realized by known techniques,
Detailed description of the internal configuration is omitted.

The flow of processing according to the embodiment of the present invention is as shown in FIG. The process shown in FIG. 5 will be described below.

The master processor 10 does not directly participate in the abnormality processing performed by the slave processor 11 by detecting it by itself.
Continue execution of software processing.

When the slave processor 11 detects an abnormality, it uses hardware such as the automatic reset generation circuit 12 shown in FIG.
Turn on logging flag 27. As a result, logging in the abnormality factor storage circuit 13 becomes effective. Further, the automatic reset flag 22 is set and the automatic reset is performed.

When the firmware 15 is activated by reset,
Judges ON / OFF of the automatic reset flag 22. If it is OFF, the reset is performed by the master processor 10, so the same reset processing as the conventional one is performed.

If the automatic reset flag 22 is ON, the error cause saving circuit
The logging information held by 13 is saved in the common memory 18. Then, the logging flag 27 and the automatic reset flag 22 are cleared (reset). Next, the cause of the abnormality is determined based on the logging information saved in the common memory 18, and whether restarting is possible or not is determined. When restarting is possible, each part is reset according to the logging information and software processing is restarted. When the restart is not possible, the master processor 10 is notified and the processing is stopped so as not to affect other slave processors and the like.

〔The invention's effect〕

As described above, according to the present invention, when an abnormality occurs in the slave processor, the master processor does not need to be aware of the abnormality of the slave processor from the abnormality occurrence to the recovery, and the processing load is reduced. In addition, since the status information including the cause of abnormality is not lost due to the automatic reset inside the slave processor, it is possible to guarantee the operation after the restoration.

[Brief description of drawings]

1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a configuration example of an automatic reset generation circuit according to an embodiment of the present invention, and FIG. FIG. 5 is a time chart of the automatic reset generation circuit shown in FIG. 5, FIG. 5 is an explanatory view of processing of one embodiment of the present invention, FIG. 6 is an example of a conventional method, and FIG. In the figure, 10 is a master processor, 11-1 to 11-n are slave processors, 12 is an automatic reset generation circuit, 13 is an error factor storage circuit, 14 is a microprocessor, 15 is a firmware, 16 is an automatic restoration control unit, Reference numeral 17 represents a common bus, and 18 represents a common memory.

Claims (1)

[Claims] 1. A master-slave type multi-processor in which one master processor (10) and a plurality of slave processors (11-1, ...) Are connected on a common bus (17) and the master processor controls the slave processors. In the processor system, each of the above slave processors monitors the occurrence of an error in its own processor and automatically resets itself when an error occurs (12) and an error factor that logs status information when the error occurs. A storage circuit (13) and a firmware that starts operation upon reset, and a processing means for determining whether or not the reset is due to the automatic reset generation circuit, and if not automatic reset, the reset by the master processor. It is a processing means that recognizes and performs predetermined reset processing, automatic reset In this case, processing means for determining an abnormality factor based on the logged status information, processing means for restarting processing if restart is possible based on the determination of the abnormality factor, and the master processor if restart is not possible A multiprocessor system comprising: an automatic recovery control section (16) having a processing means for notifying an abnormal occurrence to the processor and stopping its own processor.