JPH0749685A - Automatic playing device - Google Patents

Abstract

PURPOSE:To play a music with a colorful quality of tone with a small amount of storage capacity in an automatic playing device. CONSTITUTION:In a rhythm pattern memory, a musical instrument group number IGN and a series of event data EVT which follow prescribed rhythm patterns are stored for every rhythm kind. The IGN represents one group among 8 musical groups. Each musical instrument group includes 8 musical instrument tone colors that are to be used to play one or plural kinds of rhythms and these musical instrument tone colors respectively correspond to 8 sound generating channels of a rhythm sound source section. The EVT includes a channel number CHN and sound generation timing data in a first byte and pitch and volume control data in a second byte. The CHN represents one of the 8 sound generation channels. During a performance, a musical instrument color tone such as cymbals is determined by the IGN and the CHN for every sound generating channel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic performance device suitable for use in automatic rhythm performance, and more particularly to setting tone colors of a plurality of tone generation channels for each tone color group and setting the tone color of each tone color group in performance pattern data. By storing channel designation data as tone color data, it is possible to automatically play various tone colors with a small storage capacity.

[0002]

2. Description of the Related Art Conventionally, as a technique for controlling the tone color of an automatic performance tone, there has been known one in which tone color data is stored in combination with timing data indicating the timing of tone generation (for example, Japanese Patent Laid-Open No. 55-55). (See Japanese Patent No. 135899).

[0003]

According to the above-mentioned prior art, the total number of tone colors that can be set as tone color data (for example, 1
Because I tried to memorize the code that identifies 0),
There has been a problem that the storage capacity for playing patterns increases.

An object of the present invention is to provide a novel automatic performance device capable of performing automatic performance with various tone colors with a small storage capacity.

[0005]

SUMMARY OF THE INVENTION An automatic musical instrument according to the present invention comprises a musical tone generating means having a plurality of musical tone generating channels each of which can set a tone color, and a plurality of the tone color groups among the plurality of tone color groups. First storage means for storing a plurality of tone color designation data for designating the tone colors of the tone generation channels, and a plurality of performance pattern data respectively corresponding to the plurality of tone color groups and corresponding to each performance pattern data. A second storage means for storing tone color group designation data for designating a tone color group, wherein each performance pattern data is a channel for designating a desired one of the plurality of tone generation channels for a plurality of tone to be generated. Designated data and timing data indicating the generation timing for each of the plurality of musical tones Of the performance pattern data, pattern selection means for selecting any of the plurality of performance pattern data, performance pattern data selected by the pattern selection means, and tone color group designation data corresponding to the performance pattern data. First read means for reading from the second storage means and a plurality of tone color designation data corresponding to the tone color group designated by the tone color group designation data read from the second storage means from the first storage means. Second read means for reading, and tone patterns of the plurality of tone generation channels are set in accordance with a plurality of tone color designation data read from the first storage means, and performance patterns read from the second storage means. The tone generation channel designated by the channel designation data in the performance pattern data according to the timing data in the data. In which a control means for instructing a tone signal generator in.

[0006]

According to the structure of the present invention, when the desired performance pattern data is selected, the performance pattern data relating to the selection and the tone color group designation data corresponding thereto are read from the second storage means. Then, a plurality of tone color designation data corresponding to the tone color group designated by the read tone color group designation data is read from the first storage means, and the tone colors of the plurality of tone generation channels are set in accordance with these tone color designation data. .

The musical tone generating means generates a musical tone signal by controlling one or a plurality of musical tone generating channels according to the read performance pattern data. That is, a tone signal is generated by instructing the tone signal generation in the tone generation channel designated by the channel designation data in the performance pattern data according to the timing data in the performance pattern data.

If the number of tone generation channels is M and the number of tone color groups is N, M × N tone colors can be set. Even if the number of timbres that can be set in this way increases,
As the tone color data in the performance pattern data, not the multi-bit data for identifying the M × N tone colors but the small bit channel designation data for identifying the M channels is stored. It can be used in a small amount, and the storage capacity can be reduced.

[0009]

FIG. 1 shows an electronic musical instrument provided with an automatic rhythm playing device according to an embodiment of the present invention. This electronic musical instrument generates a manual playing sound signal and an automatic rhythm sound signal with the help of a microcomputer. Are controlled.

The keyboard 10 includes a large number of keys and a large number of key switches interlocking with the respective keys, and each key switch is scanned through a key switch (KSW) interface 12. The key depression data obtained by the key scanning is supplied to the key tone sound interface 16 via the bus 14.

The panel 18 is provided with a large number of musical tone selecting operators 18A and a large number of rhythm operating elements 18B. The rhythm operating element 18B is selected from a large number of rhythms as shown in FIG. A group of rhythm selection switches 20 for selecting a specific rhythm, a rhythm start / stop switch 22, and a balance adjusting volume 2 for noise (cymbal) rhythm sounds and drum rhythm sounds.
4 and the volume 26 for adjusting the total volume of the rhythm sound
And a rhythm tempo adjusting volume 28. The operators 18A and 18B are scanned via the panel interface 30, and musical tone selection operation data among the operation data obtained by this scanning is supplied to the key musical tone interface 16 via the bus 14.

The key tone interface 16 converts the key depression data and tone selection operation data into a serial signal and supplies the serial signal to the keyboard tone forming circuit 32. The keyboard sound forming circuit 32 responds to the serial signal from the interface 16 by time-division-multiplexed digital tone signal (manual performance tone signal) K.
Form TS and convert serial (S) / parallel (P)
It is supplied to the distribution circuit 34. The S / P conversion / distribution circuit 34 converts the digital musical tone signal KTS into a parallel signal and supplies it to the digital (D) / analog (A) conversion circuit 36. Then, the analog tone signal from the D / A conversion circuit 36 is supplied to the central speaker 40C via the output amplifier 38 and converted into sound.

The central processing unit (CPU) 42 has a RAM (random access memory) in a working area 44,
A program memory 46 including a ROM (Read Only Memory) is used to control the tone signal generation as described above and the rhythm tone signal generation as described below. General-purpose A, X, Y registers, etc. Is included.

Regarding the rhythm sound signal generating operation, the working area 44 is provided with a large number of storage areas as shown in Table 1 below.

[0015]

[Table 1] Rhythm operation data obtained by scanning the rhythm operator 18B is transferred from the panel interface 30 to the bus 14
And is stored in the working area 44 via the. That is, the operation data of the rhythm selection switch 20 is stored in the register RHYPTN as rhythm designation data, and the noise / drum system balance adjusting volume 24 is set.
Operation data is divided into noise system volume data and drum system volume data, and is divided into registers RHCLEV and R
The operation data of the total volume adjusting volume 26 is stored in the register TOTLEV as the total volume data, and the operation data of the rhythm tempo adjusting volume 28 is stored in the register TEMPO as the rhythm tempo data.

Rhythm pattern memory 48 including a ROM
Shows the rhythm pattern data stored in the format shown in FIG. 3 for various rhythms shown in FIG. In each rhythm pattern data, a 1-byte musical instrument group number data is initially arranged corresponding to the head address, and the lower 3 bits thereof indicate any musical instrument group number IGN of 0 to 7 according to the rhythm classification of FIG. It has become. Then, between the instrument group number data and the first beat end data BE, some event data EVT relating to the rhythm sound to be sounded in the first beat is arranged in the sounding timing order.

Each event data EVT consists of 2-byte data, the most significant bit of the first byte is not used, and the lower 3 bits are any one of channel numbers CHN 0 to 7 as shown in FIG. The lower 4 bits indicate any one of the intra-beat timings TMG of 0 to 11. Here, the channel numbers CHN of 0 to 7 correspond to rhythm musical instruments represented by symbols such as "TCY" and "HH" for each musical instrument group, that is, for each rhythm type as shown in FIG. The correspondence with each rhythm musical instrument is shown in Table 2 below.

[0018]

[Table 2] In the second byte of each event data EVT, the upper 4 bits are the pitch PIT, and the lower 1 bit is the sustain short (S) / long (L) in the amplitude envelope.
, The lower 3 bits indicate the volume level LEV. Here, the pitch PIT specifies, for example, whether the tom tones are treble or bass,
It is for specifying whether the conga is a high tone, a low tone or a crash tone. Also, the volume level L
EV is for designating the strength of each sound in the range from pianissimo to fortissimo.

Therefore, each event data EVT includes information on which rhythm instrument is to be sounded at which beat timing, what pitch, what envelope shape, and at what volume. Will be there.

The beat end data BE consists of 1-byte data, the upper 4 bits are not used, and the remaining 4 bits are “1101”. For convenience, this content is expressed as “OD” in hexadecimal notation. .

The second beat event data EVT is sequentially arranged after the first beat end data BE, and the second beat end data BE is then arranged, and so on. And beat end data B
E is placed. And the last event data EVT
Is followed by return data RTN. Return data RTN consists of 1-byte data, and its upper 4
Bits are not used, and the remaining 4 bits are “1111”, and this content is expressed as “OF” in hexadecimal notation for convenience.

The pattern head address memory 50, which is a ROM, stores head address data for each rhythm of the rhythm pattern memory 48.
The stored contents are read by using the rhythm designation data from the register RHYPTN in 4 as an address signal.

The logarithmic (LOG) volume table 52 includes a first ROM for logarithmically converting the total volume data from the register TOTLEV, a drum volume data from the register RHDLEV, and a noise volume data from the register RHCLEV. Second for logarithmic conversion
It has a ROM.

The rhythm interface 54 repeatedly generates tempo pulses at a cycle corresponding to the set tempo and sends out each tempo pulse as an interrupt command signal INT, and if there is event data to be sounded at a specific timing, The serial data OPC as shown in 4 is sequentially supplied to the rhythm sound generating circuit 56 for eight musical instruments. In the serial data OPC of FIG. 4, CLR (first bit) is a clear signal, NKON is a sounding command signal, and LEV.
(3 bits) indicates a volume level designation signal, S / L indicates a sustain short / long designation signal, and PIT (4 bits) indicates a pitch designation signal. The rhythm interface 54 has a register TEMP when the rhythm tempo is designated.
Since the rhythm tempo data is supplied from O, the rhythm tempo is determined based on this rhythm tempo data.

The panel data interface 58 is shown in FIG.
Volume control signal LV and rhythm control signal PA as shown in FIG.
N is supplied to the rhythm sound generating circuit 56. The volume control signal LV is an 8-bit signal NLEV for designating the volume level of a noise rhythm instrument and an 8-bit signal DLE for designating the volume level of a drum rhythm instrument.
V and V are arranged in series, and the value of the noise system volume level designating signal NLEV is represented by log (T × B _N ) and the value of the drum system volume level designating signal DLEV is represented by log (T × B _D ), respectively. Here, T represents the total volume level of the volume 26, and B _N and B _D represent the noise volume level and the drum volume level of the volume 24, respectively. Therefore, the noise volume level designating signal NLEV is obtained by adding the total volume data from the first ROM of the logarithmic volume table 52 and the noise volume data from the second ROM of the table 52, and the drum volume level designating signal DLEV is obtained by adding the total volume data from the first ROM of the logarithmic volume table 52 and the drum volume data from the second ROM of the table 52.

As shown in FIG. 4, the rhythm control signal PAN is composed of 8-bit musical instrument group number data read from the rhythm pattern memory 48 and includes a 3-bit musical instrument group number signal IGN. This signal IGN is data (musical instrument name data, noise system / drum system designation data, and center speaker / left speaker designation data) corresponding to the rhythm type in the rhythm sound generation circuit 56.
Read out.

The rhythm sound generating circuit 56 performs time-divisional generation of digital rhythm sound waveform data and a sound volume control operation based on the serial data OPC, the sound volume control signal LV and the rhythm control signal PAN, and the sound volume is controlled. Waveform data is designated by either the center speaker 40C or the left speaker 40L, and then P /
S converted. For each musical instrument group, whether each rhythm musical instrument sound is to be produced by the speaker is shown in FIG. 2 “C” or “L”.
The predetermined contents are stored in advance in the ROM in the rhythm sound generation circuit 56. In FIG. 2, “C” and “L” indicate that the central speaker and the left speaker should produce sound.

As a result, the rhythm sound generating circuit 56 outputs the time-division multiplexed serial digital rhythm sound signal R.
The TS is transmitted and supplied to the S / P conversion / distribution circuit 34. The S / P conversion / distribution circuit 34 S / P-converts the rhythm sound signal RTS and distributes it to any of the D / A conversion circuits 36 or 60 corresponding to the above-described speaker designation processing. Therefore, the analog rhythm sound signal from the D / A conversion circuit 36 passes through the output amplifier 38 and the central speaker 40C.
To the D / A conversion circuit 60 while being acoustically converted.
The analog rhythm sound signal from is supplied to the left speaker 40L via the output amplifier 62 and is acoustically converted.

Next, the operation of the electronic musical instrument will be described in more detail with reference to FIG.

First, when the power switch is turned on, an initial clear signal for initialization is generated, and each register is cleared in response to this.

Next, scanning of the keyboard 10 and the panel operators 18A and 18B is started, and key information and operation information are detected. Then, the presence or absence of an event (yes Y or no N) is determined, and if there is no event (if N), the scanning is repeated.

If one of the rhythm selection switches 20 is pressed to select a specific rhythm, the rhythm designating data designating the selected rhythm is stored in the register RHYPTN of the working area 44. Further, since an event related to rhythm selection is detected, it means that there is an event (Y), and the rhythm set subroutine is executed. This rhythm set subroutine performs processing such as setting the start address of the rhythm pattern memory 48 according to the selected rhythm type, and will be described later with reference to FIG.

Next, a noise system /
When the drum system balance adjusting volume 24 and the total volume adjusting volume 26 are set at appropriate positions, noise system volume data is stored in the register RHCLEV, drum system volume data is stored in the register RHDLEV, and total volume data is stored in the register TOTLEV. . Each volume data stored in this case indicates any value from 0 to 15 according to the operation amount of the corresponding volume. Further, since the event related to the rhythm volume setting is detected, the event occurs (Y), and as described above, the processing for generating the volume control signal LV using the registers RHCLEV, RHDLEV and TOTLEV and the logarithmic volume table 52 is performed. Done.

Next, when the rhythm tempo adjusting volume 28 is set at an appropriate position for setting the rhythm tempo, the rhythm tempo data corresponding to the set value is stored in the register TEMP.
Stored in O. Further, since an event related to the rhythm tempo setting is detected, the event is present (Y), and the rhythm tempo data of the register TEMPO is output to the rhythm interface 54. That is, in the rhythm interface 54 of FIG. 7, the decoder 72 that decodes the signal from the address bus 70 has the timing signal R.
When HYDEC1 is generated, this signal is supplied as the load signal L to the tempo register 74, so the register 7
4, rhythm tempo data of data bits 0 to 5 (6 bits) is loaded from the data bus 76. Register 7
The rhythm tempo data from 4 is converted into preset data PSD for the counter 80 by the tempo ROM 78.

Next, when the rhythm start / stop switch 22 is set to the start position, an event related to the rhythm start is detected, the event is present (Y), and the rhythm run flag is set. That is, "80" in hexadecimal notation ("10000000" in binary notation) is set in the register RHYRUN. Then, the rhythm interface of FIG. 7 performs a rhythm tempo synchronization operation. More specifically, "01" is loaded in hexadecimal notation into the function register 82 in response to the timing signal RHYDEC4 from the decoder 72, and in response thereto, the register 82 generates a start signal STRT and then automatically clears. To be done. Start signal ST
Since RT resets the frequency division counter 86 via the OR gate 84, the counter 86 starts counting the clock signal φ from the clock source 88 which receives the synchronization signal SYN after reset. Counter 86 generates a carry-out signal CO ₁ reaches a certain value by counting the clock signal phi, the signal CO ₁ is to reset the counter 86 via the OR gate 84. Therefore, the carry-out signal CO ₁ is repeatedly sent from the counter 86 at a constant cycle and is supplied to the counter 80 as the counted input CK.

The counter 80 is loaded with preset data PSD in response to the start signal STRT from the OR gate 90, and divides the carry-out signal CO ₁ of the counter 86 at a frequency division ratio according to the preset data PSD. The carry-out signal CO ₂ from the counter 80 is supplied to the counter 80 via the OR gate 90 and the load signal LD.
The counter 80
Each time the carry-out signal CO ₂ is generated, the preset data PSD is preset, and the counter 80 repeatedly outputs the carry-out signal CO ₂ at a cycle corresponding to the set tempo.

The OR gate 90 first starts the start signal ST.
After the interrupt command signal INT is generated in response to RT, the interrupt command signal INT is generated each time the carry-out signal CO ₂ is generated.
Is to occur. The interrupt command signal INT is generated 12 times within one beat corresponding to the intra-beat timings 0 to 11, and each time the interrupt command signal INT is generated, a rhythm sound as shown in FIG. 6 is generated. A subroutine for generation is executed as an interrupt process. Therefore, it is possible to generate the rhythm sound according to the set tempo immediately after the frequency division counter 86 is reset by the start signal STRT. The timing at which the rhythm sound is generated from the 12 interrupt timings within one beat differs depending on the rhythm type, and is specifically determined according to the rhythm pattern data read from the rhythm pattern memory 48.

After the rhythm sound is generated as described above, the keyboard performance can be started in synchronization with the automatic rhythm sound. Usually, prior to the keyboard performance, a musical tone selection operation including a tone color setting and a volume setting is performed by the musical tone selection operator 18A before the rhythm starts. Such a musical tone selection operation is detected by the panel scanning each time, and an event occurs (Y). Therefore, the musical tone selection operation data is processed, and the processed data is supplied to the key musical tone interface 16. When the keyboard performance is started, an event occurs (Y) every time the key is pressed. Therefore, the key depression data is processed, and the processed key depression data is supplied to the interface 16. Therefore, the manual performance sound signal KTS is formed as described above, and the manual performance sound is produced from the speaker 40C.

During the performance of the keyboard, the processing after the scanning of the keyboard / panel of FIG. 5 is carried out every time there is an event, but every time the interrupt command signal INT is generated (1
It is interrupted for interrupt processing (12 times within a beat) and restarted each time the interrupt processing is completed.

When the rhythm start / stop switch 22 is set to the stop position during the performance of the keyboard or after the completion of the performance of the keyboard, an event related to the rhythm stop is detected. For this reason, there is an event (Y), and rhythm stop processing such as buffer clearing is performed. That is,
In FIG. 7, the function register 82 displays "0" in hexadecimal notation according to the timing signal RHYDEC4.
4 "is loaded, and in response, the register 82 generates the buffer clear signal BUFCL. This signal BUFC
L is a shift register (S / R) via an OR gate 92
94. The shift register 94 has 8 stages /
It is a 1-bit signal and is timed by a channel timing signal ChT from a channel frequency dividing circuit 100 which divides the clock signal φ in accordance with the synchronizing signal SYN. The buffer clear signal BUFCL sets the contents of the shift register 94 to "1" for all eight channels (eight musical instruments), and then the register 82 is automatically cleared.

Next, the register 82 is loaded with "20" in hexadecimal notation according to the timing signal RHYDEC4, and in response thereto the register 82 generates the data transfer command signal TRAN. This signal TRAN is supplied to the P / S conversion circuit 102. Therefore, the P / S conversion circuit 102 causes the clear signal CLR from the shift register 94,
A tone generation command signal NKON from the shift register 98 and a signal from a shift register 118, which will be described later, are loaded for each one channel according to the channel timing signal ChT, sent out according to the clock signal φ, and repeated eight times. Thus, the signals for all eight channels are sequentially transmitted as serial data OPC. In this case, since the clear signal CLR is "1" for all channels, as a result, the generation of the rhythm sound is stopped as described later. The register 82 is automatically cleared after sending the data OPC by the signal TRAN.

Further, the shift registers 94 and 98 are connected to the AND gate 126 via the inverters 122 and 124.
And 128, the data transfer command signal TRAN supplies all eight channels to "0".

After that, initialization is performed by clearing the rhythm-related registers.

Next, the rhythm set subroutine will be described with reference to FIG.

First, a rhythm run is determined from the contents of the rhythm run flag RHYRUN. If the flag RHYRUN is 0, it is not a rhythm run (during rhythm playing), and if it is not 0, it is a rhythm run. Before the rhythm starts, since it is not a rhythm run (it is N), it proceeds to the processing of the progressive beat number set. The number of progressive beats is 0 to 2 if it is 3 beats,
If it is four beats, it is any of 0 to 3. The number of beats 0, 1, 2 in the case of 3 beats is the timing within a bar (counter TIMI
NG count value) 0-11, 12-23, 24-3
It corresponds to 5 respectively, and the number of beats in the case of 4 beats is 0,
1, 2, and 3 are 0 to 11 and 12 to 2 of the timing within the bar.
3, 24 to 35, 36 to 47, respectively.
Before the rhythm starts, the number of beats is 0 in any case, and 0 is written in the register HKPE.

Next, it is judged again whether or not the rhythm run. Since the rhythm run is not performed before the rhythm start, the process moves to the process of setting the head address for the rhythm pattern memory 48.
In this process, the content of the pattern head address memory 50 is read out based on the rhythm designating data from the register RHYPTN and set in the head address memory RHYROM. The memory 50 corresponds to the specific rhythm designated by the rhythm designating data. The head address data is read and written in the memory RHYROM.

Next, rhythm pattern data reading and address pointer setting processing are performed based on the head address data from the memory RHYROM. That is, in this process, the rhythm pattern data corresponding to a specific rhythm is read from the rhythm pattern memory 48,
According to the contents of the register HKPE and the counter TIMING, the channel timing data (first byte of event data) to be read first at the time of the next interrupt processing is searched, and the address of the channel timing data is the address pointer. Set to RHPNT. Before the rhythm starts, the contents of the register HKPE and the counter TIMING are both 0, so 1 is written in the address pointer RHPNT to indicate the address next to the start address.

Next, the musical instrument group number data corresponding to the specific rhythm read from the rhythm pattern memory 48 is sent to the panel data interface 58, and in response thereto, the interface 58 sends a rhythm control signal as shown in FIG. 4PAN. It is supplied to the rhythm sound generation circuit 56.

Thereafter, it is determined whether or not the specific rhythm indicated by the rhythm designating data has three beats, and if it has three beats, the maximum timing value 35 is set in the register TMPMAX,
Register TMPM if not 3 beats (4 beats)
The maximum timing value 47 is set in AX.

The above is the flow of the rhythm set processing before the rhythm starts, but the flow of the rhythm set processing when the rhythm is changed after the rhythm starts is as follows. In this case, since the rhythm has started, it is determined to be a rhythm run (Y), and the pattern change flag PCHNGF is set. That is, the flag P
In CHNGF, "01" is written in hexadecimal notation, which makes it possible to stop the generation of the previous rhythm sound at the next interrupt timing.

Next, the process goes to the process of setting the number of beats, and the register HKPE stores the number of beats when the rhythm is changed, for example, 2
(Corresponding to the third beat) is written. At this time, the contents of the intra-bar timing counter TIMING are stored in the register HKPE.
If the content of 2 is 2, it is a value from 24 to 35,
For example, 29.

After that, it is determined again whether or not the rhythm run is performed, and since it is the rhythm run, the process proceeds to the beat end / return flag RHHEND clear processing. This process is flag R
0 is written in HHEND, and the address pointer RHPNT is newly set after that, which is necessary for advancing an interrupt process described later.

Next, the processing of the head address set for the rhythm pattern memory 48 is performed. In this case, since the register RHYPTN contains the rhythm designating data corresponding to the newly selected rhythm, the leading address data corresponding to the newly selected rhythm is read from the pattern leading address memory 50, and the leading address is read. Written to memory RHYROM.

Next, the rhythm pattern data corresponding to the newly selected rhythm is sequentially read from the rhythm pattern memory 48 based on the head address data from the memory RHYROM, and the address pointer setting process is performed. In this processing, if the content of the register HKPE is 0 (if it is the first beat), the data of the counter TIMING is directly compared with the intra-beat timing data TMG.
If the content of the register HKPE is 1 or more (after the second beat), the rhythm pattern data is sequentially read and the beat change flag R is read.
Every time DISPF becomes "1" (each time the beat ends), 12 is subtracted from the data of the counter TIMING and compared with the intra-beat timing data TMG. Then, in this comparison, the address of the channel timing data when the two coincide with each other is set in the address pointer RHPNT.

For example, as described above, the register HKPE
2 and the counter TIMING contains 29, the beat change flag RDISPF becomes "1" at the end of the first beat and the end of the second beat, respectively.
The timing values 29 to 12 are subtracted twice. And
The value 5 obtained as a result is compared with the value of the in-beat timing data TMG of the third beat, and a match is obtained when the channel timing data of the timing value 5 of the third beat is read. Therefore, the address when such a match is obtained is set in the address pointer RHPNT, and at the next interrupt timing, the rhythm pattern data corresponding to the newly selected rhythm is read from the timing value 5 of the third beat. Will be started.

After the address pointer set as described above, the process of transmitting the instrument group number data regarding the newly selected rhythm, determining whether the time signature is three or four, and the maximum timing set are performed before the rhythm start described above. It is performed in the same manner as the case.

Next, the subroutine of the interrupt processing will be described with reference to FIG.

When the interrupt command signal INT is generated, the contents of each register are transferred to the memory and saved. And
In the same manner as described above, it is determined from the contents of the rhythm run flag RHYRUN that the rhythm run. After the rhythm start / stop switch 22 is set to the start position, the content of the flag RHYRUN is not 0, so it is determined to be rhythm run (Y).

Next, the pattern change flag PCHNG
It is determined from the contents of F whether the rhythm has been changed. Flag PCHN
If GF is 0, the rhythm is not changed, and if GF is not 0, the rhythm is changed. Normally, the rhythm is not changed immediately after the start of the rhythm, and in this case, the process proceeds to the rhythm pattern processing subroutine of FIG.

In FIG. 10, first of all, it is judged from the contents of the beat end / return flag RHHEND whether it is a beat end. Immediately after the rhythm starts, there is no beat end (flag RH
HEND is not 1), so address pointer RHPN
Move the contents of T to the Y register. Then, using the value obtained by adding the start address memory RHYROM and the Y register as an address, the first event data EVT corresponding to the selected rhythm, the data of the first byte, that is, the channel number CHN and the in-beat timing TMG -Read the timing data from the rhythm pattern memory 48 and store it in the A register.

Next, after transferring the channel timing data of the A register to the X register, the lower 4-bit in-beat timing data TMG is extracted from the channel timing data of the X register and placed in the A register. That is, in this state, the A register contains the in-beat timing data TMG, and the X register contains the channel number data CHN and the in-beat timing data TMG.

Next, the in-beat timing data TMG and the in-beat timing counter TMPCN which are the contents of the A register
It is determined by comparing the contents of T with the contents of T. At this time, if no timing coincidence is obtained, this means that there is no event data to be sounded at the first in-beat timing (count value of the counter TMPCNT is 0). In this case, the value of the in-beat timing data TMG in the A register is "O" in hexadecimal.
D ”or more, that is, the end / return of the beat is determined. Since it is not the beat end / return now, the contents of the Y register are transferred to the address pointer RHPNT and the rhythm pattern processing is ended.

Next, the process for outputting the data transfer instruction in FIG. 9 is started. This processing is performed in the same manner as described above regarding the rhythm stop, and the P / S conversion circuit 102 of FIG. 7 sequentially outputs serial data OPC of all bits "0" for eight musical instruments. Therefore, in this case, no musical instrument sound is generated for the selected rhythm.

After that, after the counter TMPCNT is incremented by 1 count, it is judged whether the count value of the counter TMPCNT exceeds 11, that is, whether the beat is over. Since it is not over beat now, the timing counter T in the bar
After incrementing IMIN by one count, the previously saved register contents are restored. This completes the first interrupt process and returns to the normal process such as the keyboard / panel scanning shown in FIG.

The second and subsequent interrupt processes are also performed in the same manner as above unless timing agreement is obtained.

By the way, the first in-beat timing data T
Assuming that MG indicates the timing value 5, the timing coincidence is obtained by the processing of FIG. 10 during the sixth interrupt processing. In this case, 1 is added to the contents of the Y register and the read address is advanced by 1. Then, using the head address memory RHYROM and the Y register, the data of the second byte from the first event data EVT, that is, the pitch sustain level data is read from the rhythm pattern memory 48 and written in the A register.

Next, a data output process is performed. That is, of the pitch sustain level data of the A register, the level data LEV is sent to the data bus 76 of FIG. 7 as a 3-bit signal of data bits 0 to 2, and the sustain short / long data S / L is the data bit. 3 is sent to the data bus 76 as a 1-bit signal, and the pitch data PIT is sent to the data bus 76 as a 4-bit signal of data bits 4 to 7. The 8-bit pitch sustain level data in total is loaded into the data register 104 according to the timing signal RHYDEC2.

Further, the channel number data CHN of the X register is sent to the data bus 76 as a 3-bit signal of data bits 4 to 6 and the timing signal RHYDE.
It is loaded into the channel register 106 according to C3. At this time, the timing signal RHYDEC3 is R-S.
Since the flip-flop 108 is set, the output Q of the flip-flop 108 is "1" and the AND gate 1
10 becomes conductive. The comparison circuit 112 is a channel counter 11 that counts the channel timing signal ChT.
The count output of 4 and the channel number data CHN from the channel register 106 are compared, and if they match each other, a coincidence signal EQ = "1" is generated. This coincidence signal E
Q is a flip-flop 10 via an AND gate 110.
8 is reset, and is supplied from the AND gate 110 to the selector 116 as the selection signal SB for selecting the input B. Therefore, the pitch sustain level data from the data register 104 is supplied to and stored in the 8-stage / 8-bit shift register 118 via the selector 116.

The coincidence signal EQ from the AND gate 110 is also supplied to the 8-stage / 1-bit shift register 98 via the OR gate 96 and is stored therein.
The signal “0” is supplied to the shift register 94 via the inverter 120 and the AND gate 126 and stored therein. The shift registers 94, 98 and 118 operate in synchronization with each other according to the channel timing signal ChT, and the data regarding a specific rhythm instrument (for example, a hi-hat cymbal) stored in each corresponding stage corresponds to the channel timing signal ChT. It is stored cyclically. Signals CLR and NKON stored in this case
Are "0" and "1", respectively.

After the data output processing as described above, the read address is incremented by adding 1 to the contents of the Y register. Then, by using the head address memory RHYROM and the Y register, the second event data EVT (channel timing data) is recorded in the rhythm pattern memory 4
It is read from 8 and written to the A register.

Then, as described above, the contents of the A register are transferred to the X register, and then the intra-beat timing data T
Extract MG and place in A register. Then, by comparing the contents of the A register and the contents of the counter TMPCNT in the same manner as described above, it is determined whether the timings match.
If the timings match, the pitch / sustain / level data is read as in the previous time, and the same operation is repeated thereafter. As a result, in-beat timing "5"
Data about all musical instruments to be pronounced in (maximum eight musical instruments) are shift registers 94, 98 and 118 in FIG.
Will be stored in. In the shift registers 94, 98 and 118, the stage corresponding to the musical instrument that does not produce sound is all "0" bits.

After all the event data of the in-beat timing 5 is read out, the timing data TMG indicating an in-beat timing value larger than 5 is read out and written in the A register. Move on to end / return determination. Since it is not beat end / return now, the contents of the Y register are changed to the address pointer R
Move to HPNT and finish rhythm pattern processing. At this time, the address of the timing data TMG previously written in the A register is written in the address pointer RHPNT, and the next event data reading is started from this address.

Next, the processing shifts to the output of the data transfer instruction of FIG. 9, and shift registers 94 and 9 of FIG.
The contents of 8 and 118 are P / S conversion circuit 102 for each musical instrument.
The serial data OPC is sequentially transmitted from the conversion circuit 102 for each musical instrument for eight musical instruments. Based on the data in which the tone generation command signal NKON is "1", the corresponding rhythm sound is output. Is played. During the operation of sending the serial data OPC, the transfer command signal TRAN = “1” is set to the inverters 122 and 12 respectively.
Since the AND gates 126 and 128 are controlled to be non-conducting via the switch 4, the shift registers 94 and 98 are cleared to "0". Further, since the output signal “1” of the inverter 120 is supplied to the selector 116 as the signal SA for selecting the input A, the data of the shift register 118 is cyclically stored via the selector 116.

Thereafter, in FIG. 9, the counters TMPCNT and TIMING are set to 1 in the same manner as described above.
After incrementing the count, restore the contents of each register to 6
Finish the second interrupt process.

At the first beat, if the interrupt processing with or without the above-described sounding is repeated several times, the lower 4 bits of the first beat end data BE are written in the A register. Therefore, the determination result of beat end / return in FIG. 10 is affirmative (Y), and determination of return is performed. Since it is not a return now, the process goes to the beat end / return flag RHHEND set, and the flag R
HHEND contains the contents of the A register (beat end data BE
Lower 4 bits of) are written. Then, the contents of the Y register are changed. In this case, since it is the beat end, the content of the Y register is changed to the address of the data next to the first beat end data BE (first channel timing data of the second beat).

After this, the contents of the Y register are moved to the address pointer RHPNT, and the rhythm pattern processing ends.

Next, the processing after the output of the data transfer command in FIG. 9 is started, and a rhythm sound is produced in the same manner as described above.
This time the interrupt processing is over.

In the next interrupt processing, since the beat end / return flag RHHEND is set to the beat end as described above, the determination result of the beat end in FIG. 10 becomes affirmative (Y), and the result in FIG. The routine ends immediately. Then, the processing after the output of the data transfer command in FIG. 9 is performed, but since the signal NKON is "0", no rhythm sound is generated.

When the interrupt processing in which the rhythm sound is not generated is repeated several times, the count value of the counter TMPCNT becomes 12. Then, the determination result as to whether the beat is over in FIG. 9 is affirmative (Y), and the intra-bar timing counter TIMING is advanced by 1 count to become the count value 12.

Next, it is judged whether the measure is over. However, since it is not over the measure now, the beat end / return flag RH is set.
Move on to HEND reset processing. That is, the flag RH
0 is written in HEND. And the counter TMP
After resetting CNT, the contents of each register are restored and the final interrupt processing of the first beat is completed.

In the first interrupt processing of the second beat, the flag RHHEND has been reset first, so the result of determination as to whether the end of the beat is negative (N) in FIG. 10, and the address pointer RHPNT is stored in the Y register. From, the address of the next data of the first beat end data BE is set. Therefore, the event data reading is started from the first channel timing data of the second beat.

After the first interrupt processing of the second beat is completed, the interrupt processing with or without sounding is repeated until the final beat of the format of FIG. 3 in the same manner as described above. Then, when the interrupt process is repeated several times at the final beat, the lower 4 bits of the return data RTN are written in the A register. Therefore, the determination result of beat end / return in FIG. 10 is affirmative (Y), and determination of return is made. Since it is a return now, the Y register is reset. That is, "00" is written in hexadecimal notation in the Y register.

Next, beat end / return flag RHHE
ND set processing is performed, and A is set in the flag RHHEND.
The register contents (lower 4 bits of return data RTN) are written. Then, the contents of the Y register are changed. In this case, since it is a return, the contents of the Y register are changed to the address next to the start address (corresponding to the first channel timing data).

After that, the contents of the Y register are transferred to the address pointer RHPNT, and the rhythm pattern processing ends.

Next, the process after the output of the data transfer command in FIG. 9 is performed, and a rhythm sound is produced in the same manner as described above.
This time the interrupt processing is over.

In the next interrupt processing, since the beat end / return flag RHHEND is set to return as described above, the determination result of the beat end in FIG. 10 becomes affirmative (Y), and the routine in FIG. Is the end. Then, the processing after the output of the data transfer command in FIG. 9 is performed, but no rhythm sound is generated.

When the interrupt process in which the rhythm sound is not generated is repeated several times, the count value of the counter TIMING becomes 36 when the time is 3 beats and 48 when the time is 4 beats. Then, in FIG. 9, it is determined whether the bar is over.
This judgment compares the contents of the counter TIMING and the contents of the maximum timing register TMPMAX to check whether the former value exceeds the latter value, and it is judged now (Y).

Next, beat end / return flag RHHE
ND is reset. And the counter TIMING
And TMPCNT are reset and then the contents of each register are restored to complete the final interrupt processing of the final beat.

After that, since the address next to the start address is set in the address pointer RHPNT,
The same interrupt processing as described above is repeated from the first beat of the format of FIG. 3, and the rhythm sound is repeatedly produced according to the stored rhythm pattern.

The above is the rhythm sound generation operation immediately after the rhythm start / stop switch 22 is set to the start position. The operation when the rhythm is changed after the rhythm start is as follows. That is, in this case, since the pattern change flag PCHNGF is set in the processing of FIG. 8 as described above,
The result of the determination as to whether the rhythm is changed is affirmative (Y), and the process proceeds to the buffer clearing process. This processing is performed in the same manner as in the case of the rhythm stop described above, and the shift register 94 of FIG. 7 becomes "1" for all eight channels.

Next, the pattern change flag PCHNG
After resetting F, the process moves to the rhythm pattern processing of FIG. The rhythm pattern processing in this case is executed for the newly selected rhythm. That is, as described above with reference to FIG. 8, since the read start address of the rhythm pattern data corresponding to the newly selected rhythm is set in the address pointer RHPNT in relation to the progress state of the previous rhythm, the rhythm is changed. The first channel timing data is read from the address indicated by the address pointer RHPNT. After that, the processes of FIGS. 10 and 9 are performed in the same manner as described above, and the rhythm sound is produced in accordance with the newly selected rhythm pattern. In this case, the rhythm sound of the channel whose CLR remains "1" in the previous buffer clear processing is forcibly attenuated.

Next, the detailed operation of the rhythm sound generating circuit 56 will be described with reference to FIG.

When the rhythm set processing is performed as described above, the rhythm control signal PAN is supplied from the panel data interface 58 (FIG. 1). This signal PAN
Is S / P converted by the S / P conversion / latch circuit 130 and temporarily stored. Then, the S / P conversion / latch circuit 130
The 3-bit instrument group number signal IGN from is RO
It is supplied to M132.

The ROM 132 stores musical instrument name data corresponding to eight musical instruments for each musical instrument group, and stores noise system / drum system designation data and central speaker / left speaker designation data for each musical instrument of each musical instrument group. These data are stored, and these data are musical instrument group number signals IGN.
And a 3-bit count output of the channel counter 134 that counts the timing signal φ _AB as an address signal.
It is designed to be read from the OM132.

For example, when the value of the musical instrument group number signal IGN is 1 and the rhythm types of the waltz and ballad shown in FIG. 2 are designated, when the count value (channel number CHN) of the counter 134 is 0, the instrument name top cymbal is read from the ROM 132. 5-bit data indicating TCY, and 1-bit data indicating that this musical instrument TCY is a noise system,
Parallel 7-bit data, which is a combination with 1-bit data indicating that the musical instrument TCY should be sounded from the left speaker, is read out. In such data reading, the count value of the counter 134 is 1, 2, 3, ... As the names change, the same is done for the other seven instrument names. Then, as the counter 134 repeats the counting operation for 8 channels (8 musical instruments), the data reading from the ROM 132 is also repeated.

From the rhythm interface 54 (FIG. 7), serial data O for the first eight musical instruments including pronunciation commands is generated.
When PC is supplied, this data OPC is S / P converted in the S / P conversion circuit 136.

Here, for the sake of simplicity, assuming that the serial data OPC for the first eight musical instruments includes the tone generation command only for the top cymbal TCY (channel number 0) of the musical instrument group number 1 in FIG. From the P conversion / latch circuit 136, at the timing of the channel number 0, the clear signal CLR = "0" and the tone generation command signal NKON =
"1" is sent out, and at the timing of the channel numbers 1 to 7, both of the signals CLR and NKON are "0".
Is sent.

The selector 138 receives the channel number 0 from the S / P conversion circuit 136 according to the signal NKON = "1".
7-bit pitch / sustain-level data for 8 stages / 7-bit shift register 1
Supply to 40.

The shift register 140 constitutes the circulating memory circuit 142 together with the selector 138, and takes in the selection data of the selector 138 according to the timing signal φ _AB and shifts it. In this case, the shift register 140 is Pitch corresponding to channel number 0
Sustain level data is sent in a time division manner. Then, the 4-bit pitch designation signal PIT from the shift register 140 is supplied to the rhythm tone generator circuit 144 together with the 5-bit instrument name designation signal GS from the ROM 132. Since the pitch designation signal PIT can be made different at each sounding timing, it is possible to raise or lower the pitch depending on the sounding timing even for the sound of the same dop cymbal.

The rhythm sound source circuit 144 is provided with a waveform memory storing digital waveform data corresponding to a number of rhythm sound waveforms or an arithmetic circuit for generating such waveform data by calculation. The instrument name designating signal GS and the pitch are designated. The rhythm sound waveform data designated by the designation signal PIT is transmitted. The instrument name designation signal GS acts to designate a read address in the case of the waveform memory system, and acts to designate a timbre constant in the case of the arithmetic system.

As described above, assuming that the instrument name designating signal GS and the pitch designating signal PIT are generated in correspondence with the top cymbal of channel number 0, the rhythm sound source circuit 144 outputs from the rising of the top cymbal to the decay. The waveform data for each sample is transmitted in a time division manner and supplied to the volume control circuit 146.

The S / P conversion circuit 148 outputs the volume control signal LV from the panel data interface 58 (FIG. 1) to S.
/ P conversion, and supplies an 8-bit noise volume level designating signal NLEV and an 8-bit drum volume level designating signal DLEV to the selector 150.

The selector 150 selects the signal NLEV or DLEV according to the noise system / drum system designation signal BAL from the ROM 132, and the selected signal is supplied to the volume control circuit 146 as the volume level control signal VLC. Thus, it becomes possible to control the volume considering the noise / drum system volume balance by the volume 24 and the total volume by the volume 26.

The envelope generator 152 outputs a tone generation command signal NKON = "1" from the S / P conversion circuit 136, a sustain short / long designation signal S / L from the shift register 140, and a 5-bit instrument name from the ROM 132. The envelope signal E is time-divided according to the designated signal GS.
The NV is formed and supplied to the volume control circuit 146. Since the signal S / L can be made different at each sounding timing, the sustain can be lengthened or shortened depending on the sounding timing even for the sound of the same top cymbal.

The 3-bit volume level designating signal LEV is also supplied from the shift register 140 to the volume control circuit 146, which enables volume control in consideration of the strength of each sound.

The volume control circuit 146 performs volume control by multiplying the waveform data for each sample by the volume level control signal VLC, the envelope signal ENV and the volume level designation signal LEV, and for each volume-controlled sample. Waveform data is supplied to the distribution circuit 154. The distribution circuit 154 outputs the waveform data for each sample to the center speaker signal S _C or the left speaker signal S _L according to the center speaker / left speaker designation signal CHA from the ROM 132.
To be supplied to the P / S conversion circuit 156.
A serial digital rhythm sound signal RTS is sent from the / S conversion circuit 156. That is, in the above-mentioned example, the waveform data corresponding to the top cymbal is the distribution circuit 1
The signal is distributed as a signal S _L for the left speaker at 54, is converted into a serial signal RTS at the P / S conversion circuit 156, and is sent out.

The above is the rhythm sound signal generating operation for one sound at the first sounding timing, but the rhythm sound signal generating operation for a plurality of sounds (up to eight sounds) is similarly performed. Then, such a rhythm sound signal generating operation is similarly performed at each sounding timing after the second.

When the rhythm stop or rhythm change operation is performed as described above while the rhythm performance is proceeding in this way, the S / P conversion circuit 136 in FIG. 11 causes the clear signal CLR = “1”. Is sequentially transmitted for 8 channels to reset the envelope generator 152. Therefore, generation of all rhythm sounds is stopped.

In the case of changing the rhythm, the serial data OPC including the sounding command is supplied thereafter.
In the same manner as described above, the rhythm sound is played according to the newly selected rhythm pattern.

[0110]

As described above, according to the present invention, the tone colors of a plurality of tone generation channels are set for each tone color group, and the channel designating data of a small number of bits is stored as the tone color data in the performance pattern data. As a result, it is possible to obtain the effect of enabling automatic performance with a variety of tones (rich in tone color variation) with a small storage capacity.

[Brief description of drawings]

FIG. 1 is a block diagram of an electronic musical instrument having an automatic rhythm playing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing rhythm instrument sounds that can be played by the automatic rhythm playing device, classified by instrument group (rhythm type).

FIG. 3 is a diagram showing a format of rhythm pattern data.

FIG. 4 is a diagram showing a format of data used for automatic rhythm performance.

5 is a flow chart for explaining the operation of the electronic musical instrument of FIG.

FIG. 6 is a flowchart of interrupt processing.

FIG. 7 is a circuit diagram of a rhythm interface.

FIG. 8 is a flowchart showing a rhythm set subroutine.

FIG. 9 is a flowchart showing details of interrupt processing.

FIG. 10 is a flowchart showing a rhythm pattern processing subroutine.

FIG. 11 is a circuit diagram of a rhythm sound generation circuit.

[Explanation of symbols]

18B ... Operator for rhythm, 42 ... Central processing unit, 48 ...
Rhythm pattern memory, 54 ... Rhythm interface, 56 ... Rhythm sound generation circuit, 58 ... Panel data interface, 132 ... Instrument name / noise system / drum system /
Central speaker / left speaker designation data ROM, 142 ...
Circulating memory circuit 144 ... Rhythm sound source circuit.

Claims (1)

[Claims] 1. A tone generation means having a plurality of tone generation channels each capable of setting a tone color, and a plurality of tone colors for designating tone colors of the plurality of tone generation channels for each tone color group of the plurality of tone color groups. A first storage means for storing data; a plurality of performance pattern data respectively corresponding to the plurality of tone color groups; and a tone color group designation data for designating a tone color group corresponding to each performance pattern data. 2 storage means, each performance pattern data includes channel designation data for designating a desired one of the plurality of tone generation channels for a plurality of tone to be generated, and generation timing for the plurality of tone. Of the plurality of performance pattern data. A first pattern reading means for selecting an arbitrary pattern, a performance pattern data selected by the pattern selection means, and tone color group designation data corresponding to the performance pattern data are read out from the second storage means. Reading means for reading a plurality of tone color designation data corresponding to a tone color group designated by the tone color group designation data read from the second storage means from the first storage means; One of the tone color of the plurality of tone generation channels is set in accordance with a plurality of tone color designating data read from one storage means, and the performance pattern data in the performance pattern data is read according to the timing data in the performance pattern data read from the second storage means. Control means for instructing the tone signal generation in the tone generation channel specified by the channel designation data of Automatic performance apparatus.