JPH0749793A - Interrupt controller - Google Patents

Abstract

PURPOSE:To contribute to the improvement of processing efficiency of a central controller by varying the interrupt level to a prescribed interrupt request signal by the interrupt level set signal from the central controller to perform the optimum priority control of interrupt requests. CONSTITUTION:When the interrupt level set signal is inputted from the central controller to a level decoder 3, the level decoder 3 makes only the level signal, which corresponds to the interrupt level corresponding to this interrupt level made signal, active. Two inputs to two-input OR circuits 5-0 to 5-7 are the level signal from the level decoder 3 and the inputted interrupt request signal, and the interrupt request signal is inputted to a priority encoder 20 through only the two-input OR circuit to which the level signal made active is inputted. Cunsequently, it is set to the interrupt level corresponding to this two-input OR circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt controller in a microcomputer or the like, and more particularly to an interrupt controller whose interrupt level can be changed by software.

[0002]

2. Description of the Related Art Conventionally, during execution of a program, a central control unit (CPU) suspends the execution of the program by a processing request asynchronously generated from peripheral hardware, and executes the program in response to the processing request. Interrupt control for starting is performed, and an interrupt controller is known as a device for performing the interrupt.

In this conventional interrupt controller, the interrupt level for determining the priority of the interrupt is uniquely determined beforehand for the interrupt factor (source of the interrupt request), and the interrupt level is determined according to the interrupt level. An interrupt signal was sent to the CPU. The CPU performs processing according to the order of the interrupt signals.

[0004]

However, in the conventional interrupt controller, since the interrupt level is determined in advance by hardware, there is a disadvantage that the processing efficiency cannot be improved depending on the processing contents of the CPU. . Considering a printer, for example, if the interrupt level is set so that serial data has a higher interrupt priority than parallel data, serial data will always have a higher priority than parallel data. Will also be prioritized and interrupted. However, if the control system changes due to differences in the connected peripherals, etc.
It may be preferable in terms of PU processing efficiency. Even in such a case, in the conventional device, the parallel data is always postponed, and this interrupt priority is not suitable for the purpose of the system.

That is, in the conventional interrupt controller in which the priority order is fixed with respect to the interrupt factor, it is impossible to perform the priority control of the interrupt request most suitable for the importance of each interrupt factor which is different for each application. It was SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an interrupt controller that aims to solve the above-mentioned problems, by making it possible to easily change the interrupt level, thereby contributing to the improvement of the processing efficiency of the central controller.

[0006]

The interrupt controller according to the present invention, which has been made to achieve the above object, centrally controls an input interrupt request signal in accordance with an interrupt priority order based on a predetermined interrupt level. An interrupt controller for interrupting a device, which is provided corresponding to a plurality of interrupt levels that can be set, receives a predetermined interrupt request signal as one input, and outputs a plurality of 2 connected to a priority encoder. An input OR circuit,
A level decoder which outputs a level signal to be the other input to each 2-input OR circuit, inputs an interrupt level setting signal from the central control unit, and activates only the level signal corresponding to the interrupt level setting signal By including the above, the interrupt level for the predetermined interrupt request signal is made variable by the interrupt level setting signal from the central control unit.

In addition to the 2-input OR circuit according to claim 1, the interrupt controller according to claim 2 outputs a level signal which is the other input to each 2-input OR circuit, and the level thereof. By providing a dip switch capable of arbitrarily setting which of the signals is activated, the interrupt level for the predetermined interrupt request signal is made variable by the operation of the dip switch.

In the interrupt controller according to the first or second aspect, the number of interrupt request signals for which the interrupt level is variable is not limited. There may be only one, or the interrupt level may be variable for all interrupt request signals. According to the first aspect of the invention, the plurality of two-input O is provided for each target interrupt request signal.
An R circuit and a level decoder are provided, and the R circuit and the level decoder are provided.
In the case of the description, the plurality of 2-input OR circuits and the DIP switch are provided for each interrupt request signal.

The two-input OR circuit is provided corresponding to a plurality of interrupt levels that can be set, but the "plurality of interrupt levels that can be set" may be two or more types. Considering that the interrupt controller itself has 8 interrupt levels, any 2 of the 8 interrupt levels
From type to all eight types are applicable.

[0010]

According to the interrupt controller having the above structure, when the interrupt level setting signal is inputted from the central control unit to the level decoder, the level decoder causes the level corresponding to the interrupt level corresponding to the interrupt level setting signal. Activate only the signal. The two inputs to the 2-input OR circuit are an interrupt request signal input with the level signal from the level decoder, and the interrupt request signal passes through only the 2-input OR circuit to which the activated level signal is input. , Input to the priority encoder.

Therefore, it is possible to set the interrupt level corresponding to the passed 2-input OR circuit. That is, the interrupt level of the predetermined interrupt request signal can be changed by the interrupt level setting signal from the central controller. For more clarity, consider a printer, for example. In the initial setting, the interrupt level of serial data is set to "4", the interrupt level of parallel data is set to "3", and the serial data is set to have a higher interrupt priority.
It is assumed that the higher the interrupt level, the higher the priority.

If the control system changes due to differences in the connected peripheral devices, it may be preferable in terms of processing efficiency of the central control unit to interrupt the parallel data first. The interrupt level is set to "5" for the level decoder provided corresponding to the parallel data which is one of the interrupt request signals.
The interrupt level setting signal is output. Then, only the 2-input OR circuit corresponding to the interrupt level "5" becomes active, and the interrupt request signal is input to the terminal corresponding to the interrupt level "5" of the priority encoder.

By setting the interrupt level of the parallel data to "5" in this way, the interrupt is given priority over the serial data. In other words, even if the importance of each interrupt factor differs depending on the state in which the central controller is placed, it becomes possible to perform optimal priority control of interrupt requests, and improve the processing efficiency of the central controller. Can contribute to.

On the other hand, according to the interrupt controller of the second aspect, which of the level signals to the 2-input OR circuit is activated can be arbitrarily set by the DIP switch. Therefore, by changing the interrupt level with respect to a predetermined interrupt request signal by operating the DIP switch, the importance of each interrupt factor depends on the state in which the central control unit is placed, etc., as in the case of the above-mentioned claim 1. Even if the degree is different, it is possible to perform the optimal priority control of the interrupt request, which can contribute to the improvement of the processing efficiency.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a schematic configuration of the interrupt controller 1 which is an embodiment of the present invention. The interrupt controller 1 is mainly composed of an interrupt control circuit 10 and a priority encoder 20, and the priority encoder 20 is connected to a central control unit (hereinafter referred to as CPU) 30. Then, the interrupt request signals INTa to INTn are input to the interrupt controller 1, and the interrupt request signals INTa to INTn are input INT0 to INT7 of the priority encoder 20 via an interrupt control circuit 10 described later.

Of these inputs INT0 to INT7, INT
0 means that there is no interrupt, so there is no change in interrupt operation when connected to "H" or "L", but IN
By connecting the T0 input to "L", the output of the priority encoder 20 is in the enable state instead of the high impedance state. Further, INT1 to INT7 indicate that the interrupt levels are inputs of "1" to "7", respectively, and the priority level "1" is the lowest and the level "7" is the highest. Priority encoder 2
With 0, interrupts below the level at which the interrupt request is issued are ignored. In this way, the interrupt request signals INTa to INTn are transmitted to the priority encoder 20.
The interrupt level is determined by which of the inputs INT0 to INT7 of the input.

Then, the interrupt controller 1 of this embodiment
Indicates that the interrupt level can be changed by an interrupt level setting signal (FIG. 1) from the CPU 30. Hereinafter, a configuration for changing the interrupt level will be described. However, for ease of understanding, the description will be given taking as an example a case where only the interrupt request signal INTa can be changed. Therefore, for the interrupt request signals INTb to INTn other than INTa, the interrupt control circuit 10
In, through without passing through a special circuit,
Inputs INT0-IN of a predetermined interrupt level as in the past
It is assumed that it is preset to T7.

FIG. 1 shows only the configuration related to the interrupt request signal INTa in the interrupt control circuit 10 of FIG. Eight two-input OR circuits 5-0 to 5-7 are provided, and the output side thereof is connected to the priority encoder 20. The output of the 2-input OR circuit 5-0 becomes the level input INT0 of the priority encoder 20, and similarly, the output of the 2-input OR circuit 5-1 is connected to the level input INT1, and so on, to the eight level inputs INT0 to 7, respectively. Has been done.

On the other hand, one of the two inputs of each 2-input OR circuit 5-0 to 5-7 is the interrupt request signal INTa, and the other input is from the level decoder 3.
There are eight output ports Q0 to Q7 of the level decoder 3,
The output signal from the output port Q0 is a 2-input OR circuit 5-0.
Input to the output port and the output signal from the output port Q1 is a 2-input OR
The input signals to the circuit 5-1 are such that the output signals from the eight output ports Q0 to Q7 are eight 2-input OR circuits 5.
Input to -0 to 5-7 respectively.

The level decoder 3 has an internal register 4
The signal from 0 is input, and the three select inputs S0 to S2 are provided. If the interrupt level setting signal from the CPU 30 is "1" (S2, S1, S0)
Becomes (0, 0, 1), and the output port Q1 becomes active. If the interrupt level setting signal is "7", (S
2, S1, S0) becomes (1,1,1), and the output port Q7 becomes active. In this way, the CPU 30
Output port Q0 corresponding to the interrupt level setting signal from
Only the ~ Q7 port is active.

Therefore, when the interrupt level setting signal for setting the interrupt level to "3" is sent from the CPU 30, the internal register 40 outputs (S2, S1, S0).
= (0,1,1), the level decoder 3 activates only the corresponding output port Q3. Therefore, the interrupt request signal INTa passes through only the 2-input OR circuit 5-3 to which the activated level signal is input, and becomes the level input INT3 of the priority encoder 20. Similarly, if a setting signal of interrupt level "5" is sent from the CPU 30, the interrupt request signal I
NTa is the level input I of the priority encoder 20
It will be NT5.

Thus, the interrupt level of the interrupt request signal INTa can be changed by the interrupt level setting signal from the CPU 30. To clarify the effect of changing the interrupt level, consider a printer as a specific example. In the initial setting, the interrupt level of serial data is set to "4", the interrupt level of parallel data is set to "3", and the serial data is set to have a higher interrupt priority.
Further, it is assumed that the interrupt request signal INTa described above relates to parallel data.

If the control system changes due to the difference in the connected peripheral devices, it may be preferable in terms of the processing efficiency of the CPU 30 to preferentially interrupt the parallel data. Therefore, in such a case, the CPU 30 outputs the interrupt level setting signal for setting the interrupt level to "5" to the level decoder 3 provided corresponding to the parallel data which is the interrupt request signal INTa. Then, the 2-input OR circuit 5-corresponding to the interrupt level "5"
Only 5 becomes active and the interrupt request signal becomes the level input INT5 corresponding to the interrupt level "5" of the priority encoder 20.

When the interrupt level of the parallel data is set to "5" in this way, the interrupt is preferentially interrupted over the serial data having the interrupt level of "4". That is, even when the importance of each interrupt factor differs depending on the state in which the CPU 30 is placed, it becomes possible to perform the optimum priority control of interrupt requests, and contribute to the improvement of the processing efficiency of the CPU 30. You can

In the above embodiment, only one interrupt request signal, INTa (corresponding to parallel data), whose interrupt level is variable is used, but the number is not limited. Only one, in the case of the above example, both the ones corresponding to parallel data and serial data may have variable interrupt levels, or the interrupt levels may be variable for all interrupt request signals INTa to INTn. . In that case, the target interrupt request signal I
For each of NTa to INTn, the above eight 2-input OR circuits 5-
0-5-7 and the level decoder 3 will be provided.

In the above embodiment, eight 2-input ORs are used.
The circuits 5-0 to 5-7 are provided and connected to all the level inputs INT0 to INT7 of the priority encoder 20, but this connection may be two or more types. For example, considering that the priority encoder 20 has eight interrupt levels as in the above embodiment, any two of the eight interrupt levels may be used, or all eight kinds may be used as in the above embodiment.

The embodiment of the present invention has been described above.
The present invention is not limited to these examples, and it goes without saying that the present invention can be implemented in various modes without departing from the spirit of the present invention. For example, in the above embodiment,
The level setting signal from the CPU 30 controls which of the level signals to the 2-input OR circuits 5-0 to 5-7 is activated. However, instead of the level decoder 3, a dip switch or the like is used to arbitrarily set the level signal. It may be set. By changing the interrupt level for a predetermined interrupt request signal by operating the DIP switch,
Similar to the above embodiment, even when the importance of each interrupt factor is different depending on the state where the CPU is placed, it is possible to perform the optimum priority control of interrupt requests.
The effect that it can contribute to improvement of processing efficiency is produced.

[0028]

As described above in detail, according to the information processing apparatus of the present invention, the interrupt level can be easily changed, so that the interrupt factor of each interrupt factor can be changed according to the state in which the central control unit is placed. Even if the degrees of importance are different, it is possible to perform optimum priority control of interrupt requests, which can contribute to improvement of the processing efficiency of the central controller.

Particularly, according to the interrupt controller of the first aspect, it can be arbitrarily changed by the interrupt level setting signal from the central control unit. Further, according to the interrupt controller of the second aspect, it can be easily changed by the DIP switch.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration related to an interrupt request signal INTa in an interrupt control circuit 10.

FIG. 2 is a block diagram showing a schematic configuration of an interrupt controller which is an embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Interrupt controller, 3 ... Level decoder 5-0-5-7 ... 2-input OR circuit, 10 ... Interrupt control circuit, 20 ... Priority encoder, 30 ... Central control unit (CPU)

Claims (2)

[Claims] 1. An interrupt controller for interrupting an input interrupt request signal to a central control unit according to an interrupt priority order based on a predetermined interrupt level, which corresponds to a plurality of interrupt levels that can be set. A plurality of two-input ORs, each of which has a predetermined interrupt request signal as one input and whose output side is connected to the priority encoder
Circuit, and a level signal which is the other input to each 2-input OR circuit is output, an interrupt level setting signal is input from the central control unit, and only the level signal corresponding to the interrupt level setting signal is activated. An interrupt controller, wherein the interrupt level for the predetermined interrupt request signal is made variable by an interrupt level setting signal from the central control unit. 2. An interrupt controller for causing an input interrupt request signal to be interrupted by a central control unit in accordance with an interrupt priority order based on a predetermined interrupt level, corresponding to a plurality of interrupt levels that can be set. A plurality of two-input ORs, each of which has a predetermined interrupt request signal as one input and whose output side is connected to the priority encoder
And a dip switch capable of arbitrarily setting which of the level signals is to be activated as well as outputting a level signal which is the other input to each two-input OR circuit, An interrupt controller characterized in that an interrupt level for a predetermined interrupt request signal is made variable by operating the dip switch.