JPH0749859Y2 - Ceramic electronic components - Google Patents
Ceramic electronic componentsInfo
- Publication number
- JPH0749859Y2 JPH0749859Y2 JP1986086296U JP8629686U JPH0749859Y2 JP H0749859 Y2 JPH0749859 Y2 JP H0749859Y2 JP 1986086296 U JP1986086296 U JP 1986086296U JP 8629686 U JP8629686 U JP 8629686U JP H0749859 Y2 JPH0749859 Y2 JP H0749859Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- ceramic substrate
- insulating coating
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000919 ceramic Substances 0.000 title claims description 56
- 239000000758 substrate Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 238000009413 insulation Methods 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 description 28
- 238000000576 coating method Methods 0.000 description 28
- 229910052709 silver Inorganic materials 0.000 description 15
- 239000004332 silver Substances 0.000 description 15
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 14
- 238000005242 forging Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000005012 migration Effects 0.000 description 5
- 238000013508 migration Methods 0.000 description 5
- 239000000428 dust Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 150000003378 silver Chemical class 0.000 description 1
Landscapes
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
【考案の詳細な説明】 産業上の利用分野 本考案は、互いに間隔を隔て内側の電極を外側の電極で
取り囲むように入出力の各電極をセラミック基板の同一
平面上に設けるセラミック電子部品の改良に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Industrial Field of the Invention The present invention is an improvement of a ceramic electronic component in which input and output electrodes are provided on the same plane of a ceramic substrate so that inner electrodes are surrounded by outer electrodes with a space therebetween. It is about.
従来の技術 例えば、セラミックフィルタや圧電セラミック振動子等
のセラミック電子部品を例示すると、これはセラミック
基板を備え、そのセラミック基板の片面には絶縁間隔を
隔て内側の電極を外側の電極で取り囲むよう入出力の各
電極を同一平面上に設け、他面には全面電極を設けるこ
とにより構成されている。2. Description of the Related Art For example, a ceramic electronic component such as a ceramic filter or a piezoelectric ceramic resonator is illustrated, which has a ceramic substrate, and one surface of the ceramic substrate is surrounded by an insulating electrode with an inner electrode surrounded by an outer electrode. The output electrodes are provided on the same plane, and the entire surface is provided on the other surface.
従来、この種のセラミック電子部品を製造するときには
銀ペーストをセラミック基板の平坦面にスクリーン印刷
した後焼付処理することにより電極が形成されている。
唯、その電極は印刷，焼付処理しただけであると表面が
凹凸で、内部にはポーラス層が介在するため、電極の焼
付処理後にバレル研摩で鍛造処理することにより表面を
平坦にし、ポーラス層をなくすることから電極強度を向
上することが行なわれている。Conventionally, when manufacturing a ceramic electronic component of this type, electrodes are formed by screen-printing a silver paste on a flat surface of a ceramic substrate and then baking it.
However, if the electrode is only printed and baked, the surface will be uneven, and a porous layer will be present inside. Therefore, after the electrode is baked, the surface will be flattened by forging by barrel polishing to form the porous layer. The electrode strength has been improved by eliminating it.
然し、その電極の鍛造処理に伴って電極形成材料の銀が
電極の間隔内におけるセラミック基板の平坦面上で近接
方向に延伸し、また、電極形成材料の金属粉カスが該セ
ラミック基板の平坦面に付着することによりセラミック
基板の平坦面が汚れて絶縁性を損なう事態を招き易い。However, as the electrode is forged, silver of the electrode forming material extends in the proximity direction on the flat surface of the ceramic substrate within the distance between the electrodes, and metal dust of the electrode forming material is flat surface of the ceramic substrate. Adhesion to the surface of the ceramic substrate tends to contaminate the flat surface of the ceramic substrate and impair its insulating property.
また、電極の鍛造処理に伴う弊害ばかりでなく、電極形
成材料の銀が高温，高湿度中で析出し、この銀が電極の
間隔内におけるセラミック基板の板面上で移動すること
により銀マイグレーション現像を生ずる虞れもある。In addition to the adverse effects associated with the electrode forging process, silver as the electrode forming material is deposited in high temperature and high humidity, and this silver moves on the plate surface of the ceramic substrate within the interval between the electrodes to develop silver migration. May occur.
その絶縁距離を確保するだけであるならば電極の面積を
小さし、電極間の間隔を広くすることが考えられる。然
し、セラミックフィルタのように共振周波数がセラミッ
ク基板の面積で決まり、等価回路の容量が電極の面積で
決まるものでは唯単に電極の面積を小さくすることによ
り電極間の間隔を広くするということはできない。ま
た、入力側の電極は駆動電極でもあるので面積を小さく
すると、電気機械変換効率が下がり、挿入損失が増加す
るところから特性の悪化を招くことになる。If only the insulation distance is secured, it is conceivable to reduce the area of the electrodes and widen the distance between the electrodes. However, in the case where the resonance frequency is determined by the area of the ceramic substrate and the capacitance of the equivalent circuit is determined by the area of the electrodes like the ceramic filter, it is not possible to increase the distance between the electrodes simply by reducing the area of the electrodes. . Further, since the electrode on the input side is also a drive electrode, if the area is reduced, the electromechanical conversion efficiency is lowered and the insertion loss is increased, resulting in deterioration of characteristics.
考案が解決しようとする課題 本考案は、バレル研摩で鍛造処理を電極に施しても電極
間の絶縁性を確実に保て、銀マイグレーション現像も防
げるセラミック電子部品を提供することを目的とする。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention An object of the present invention is to provide a ceramic electronic component capable of reliably maintaining insulation between electrodes even when a forging process is performed by barrel polishing and preventing silver migration development.
また、本考案はセラミック基板の決められた面積の中で
電極の面積を小さくしなくても絶縁距離を確保できるよ
う改良したセラミック電子部品を提供することを目的と
する。Another object of the present invention is to provide a ceramic electronic component improved so that the insulation distance can be secured without reducing the area of the electrode within the determined area of the ceramic substrate.
課題を解決するための手段 本考案に係るセラミック電子部品においては、互いに間
隔を隔て内側の電極を外側の電極で取り囲むよう入出力
の電極をセラミック基板の同一平面上に設け、その各電
極の全面を被覆することなく、電極間のセラミック基板
の平坦面と、少なくとも片側の電極の縁部とを低密度な
ソルダーレジスト材で絶縁被覆し、且つ、各電極をバレ
ル研摩で鍛造処理することにより構成されている。Means for Solving the Problems In a ceramic electronic component according to the present invention, input / output electrodes are provided on the same plane of a ceramic substrate so that inner electrodes are surrounded by outer electrodes with a space between each other, and the entire surface of each electrode is provided. Insulating the flat surface of the ceramic substrate between the electrodes and the edge of at least one of the electrodes with a low-density solder resist material, and forging each electrode by barrel polishing. Has been done.
作用 （１）このセラミック電子部品は、入出力電極の間隔内
においてセラミック基板の平坦面がソルダーレジスト材
の絶縁被膜で被覆されている。Action (1) In this ceramic electronic component, the flat surface of the ceramic substrate is covered with the insulating coating of the solder resist material within the space between the input and output electrodes.
a.そのため、バレル研摩で鍛造処理を電極に施しても、
電極形成材料が電極間の間隔内におけるセラミック基板
の平坦面上で近接方向に伸延するのを絶縁被膜の膜厚で
阻止することができる。a. Therefore, even if the electrode is forged by barrel polishing,
The thickness of the insulating coating can prevent the electrode forming material from extending in the proximity direction on the flat surface of the ceramic substrate within the space between the electrodes.
b.この電極の鍛造処理で電極形成材料の金属粉カスが生
じても、電極の間隔内におけるセラミック基板の平坦面
には金属粉カスが付着するのをソルダーレジストの絶縁
被膜で防げる。また、その金属粉カスがソルダーレジス
トス材の被膜表面に付着したとしても、その絶縁被膜は
緻密に形成されているので洗浄等で容易に除去すること
ができる。b. Even if a metal powder residue of the electrode forming material is generated by the forging process of this electrode, the insulating film of the solder resist can prevent the metal powder residue from adhering to the flat surface of the ceramic substrate within the interval between the electrodes. Even if the metal powder dust adheres to the surface of the solder resist material film, it can be easily removed by washing or the like because the insulating film is densely formed.
従って、絶縁性を損なうことなく、バレル研摩で鍛造処
理を電極に施せるので、電極の表面を平坦にししかもポ
ーラス層をなくすることにより電極強度の向上を図るこ
とができる。Therefore, the forging process can be performed on the electrode by barrel polishing without impairing the insulating property, so that the electrode strength can be improved by flattening the surface of the electrode and eliminating the porous layer.
c.上述したセラミック基板の平坦面は、ソルダーレジス
ト材の絶縁被膜で吸湿するのも防げる。このため、電極
形成材料中の銀が高温，高湿度中で析出しても、電極の
間隔内に移動するのを防げて銀マイグレーション現象の
発生を抑えることができる。c. The flat surface of the ceramic substrate described above can also be prevented from absorbing moisture by the insulating coating of the solder resist material. Therefore, even if silver in the electrode forming material is deposited at high temperature and high humidity, it is possible to prevent the silver from moving within the interval between the electrodes and suppress the occurrence of the silver migration phenomenon.
（２）絶縁被膜は、入出力電極の少なくともいずれか片
側の電極縁部にもソルダーレジスト材を被せることによ
り設けられている。このソルダーレジスト材を電極の縁
部に被せた幅分だけ電極の面積を確保できしかも電極間
の沿面絶縁距離も長く取れるので、電気機械変換効率を
下げずに絶縁性を確保するという両面から特性を満足さ
せることができる。(2) The insulating coating is provided by covering the electrode edge portion of at least one of the input / output electrodes with a solder resist material. The area of the electrodes can be secured by the width of the edges of the electrodes covered with this solder resist material, and the creeping insulation distance between the electrodes can be made long, so it is possible to secure insulation without lowering the electromechanical conversion efficiency. Can be satisfied.
（３）絶縁被膜は、各電極の夫々全面を被覆しないよう
設けられているため、ソルダーレジスト材による質量的
負荷を各電極に与えるのを抑えることができる。また、
その絶縁被膜は低密度のソルダーレジスト材で形成され
ているから、セラミック基板の機械的振動を阻害するの
も防げる。(3) Since the insulating coating is provided so as not to cover the entire surface of each electrode, it is possible to suppress applying a mass load due to the solder resist material to each electrode. Also,
Since the insulating coating is made of a low-density solder resist material, it can prevent the mechanical vibration of the ceramic substrate from being disturbed.
以上総じ、本考案に係るセラミック電子部品は特性に優
れて信頼性の高いものに構成することができる。In general, the ceramic electronic component according to the present invention can be configured to have excellent characteristics and high reliability.
実施例 以下、添付図面を参照して説明すれば、次の通りであ
る。Embodiments The following will be described with reference to the accompanying drawings.
第１及び第２図のセラミック電子部品は略正方形のセラ
ミック基板１を用い、例えばAM用455kHzのセラミックフ
ィルタを構成する場合が示されてる。The ceramic electronic components shown in FIGS. 1 and 2 use a substantially square ceramic substrate 1 to form a ceramic filter of 455 kHz for AM, for example.
セラミック基板１の片面には、銀ペーストを全面に付着
することにより全面電極２が設けられている。また、他
面側には互いに所定の間隔３を隔て内側の電極４を外側
の電極５で取り囲むよう入出力の各電極4,5が同一平面
上に設けられている。これら各電極２、4,5は、銀ペー
ストを８±２μｍ厚程度の膜厚に付着することにより夫
々形成されている。On one surface of the ceramic substrate 1, a full surface electrode 2 is provided by depositing silver paste on the entire surface. Further, on the other surface side, input and output electrodes 4 and 5 are provided on the same plane so as to surround the inner electrode 4 with the outer electrode 5 with a predetermined gap 3 therebetween. Each of these electrodes 2, 4 and 5 is formed by depositing silver paste in a thickness of about 8 ± 2 μm.
その各部の構成に加えて、ソルダーレジスト材の絶縁被
膜６が設けられている。この絶縁被膜６は入出力電極4,
5の全面を被覆することなく、少なくとも入力側の電極
４の縁部７と、入出力の各電極4,5を隔てる間隔３内に
おけるセラミック基板１の平坦面とを被覆するよう形成
されている。また、その絶縁被膜６はセラミック基板１
の機械的振動を阻害しないよう低密度のソルダーレジス
ト材を用いて0.2mm厚程度の膜厚に付着形成されてい
る。In addition to the structure of each part, an insulating coating 6 of a solder resist material is provided. This insulating film 6 is used for input / output electrodes 4,
It is formed so as to cover at least the edge portion 7 of the electrode 4 on the input side and the flat surface of the ceramic substrate 1 in the space 3 separating the input and output electrodes 4 and 5 without covering the entire surface of 5. . Moreover, the insulating coating 6 is formed on the ceramic substrate 1.
Is formed to a thickness of about 0.2 mm using a low-density solder resist material so as not to hinder the mechanical vibration of.
このように構成するセラミック電子部品は、第３図で示
すように各工程処理後各部品単位体毎にスリット分割す
る多数個取りのセラミック基板を用いて一括成形するよ
うにできる。The ceramic electronic component thus configured can be collectively molded by using a multi-cavity ceramic substrate which is slit-divided into each component unit after each process as shown in FIG.
その一括製造工程中で、電極２、4,5並びに絶縁被膜６
が設けられたセラミック基板１をガラスボール或いはプ
ラスチックボールと共に回転バレルに入れて回転させる
ことにより電極の鍛造処理を施す。この際、各電極4,5
の間隔３内にはソルダーレジスト材による絶縁被膜６が
設けられているため、電極4,5を形成する銀が電極4,5の
間隔内においてセラミック基板１の平坦面上で近接方向
に伸延するのを絶縁被膜６の膜厚で阻止することができ
る。In the batch manufacturing process, the electrodes 2, 4, 5 and the insulating coating 6
The ceramic substrate 1 provided with is placed in a rotary barrel together with a glass ball or a plastic ball and is rotated to forge the electrode. At this time, each electrode 4,5
Since the insulating coating 6 made of the solder resist material is provided in the interval 3 of, the silver forming the electrodes 4, 5 extends in the proximity direction on the flat surface of the ceramic substrate 1 within the interval of the electrodes 4, 5. Can be prevented by the thickness of the insulating coating 6.
その電極の鍛造処理で電極形成材料のポーラス量が皆無
となり、また、電極形成材料の金属粉カスが生じたとし
ても、各電極4,5の間隔３は絶縁被膜６で被覆されてい
るため、この絶縁被膜６で被覆されたセラミック基板１
の平坦面には金属粉カスが付着することはない。但し、
金属粉カスが絶縁被膜６の表面に付着しても、その絶縁
被膜６はソルダーレジスト材で緻密なものに形成されて
いるから洗浄等で容易に除去することができる。Even if the electrode forming material has no porous amount due to the forging process of the electrode and metal dust of the electrode forming material is generated, the space 3 between the electrodes 4 and 5 is covered with the insulating coating film 6. Ceramic substrate 1 covered with this insulating coating 6
No metal dust is attached to the flat surface of the. However,
Even if the metal powder residue adheres to the surface of the insulating coating film 6, the insulating coating film 6 can be easily removed by washing or the like because the insulating coating film 6 is formed of a dense solder resist material.
また、上述したセラミック基板１の平坦面は高温，高湿
度中でも吸湿するのをソルダーレジスト材の絶縁被膜６
で防ぐことができる。このため、電極形成材料の銀が高
温，高湿度中で析出しても、その銀が各電極4,5の間隔
内に移動するのを防げて銀マイグレーション現象が生ず
るのを防止することができる。Further, the flat surface of the ceramic substrate 1 described above absorbs moisture even in high temperature and high humidity so that the insulating coating 6 of the solder resist material
Can be prevented with. Therefore, even if silver of the electrode forming material is deposited in high temperature and high humidity, it is possible to prevent the silver from moving within the interval between the electrodes 4 and 5 and prevent the silver migration phenomenon from occurring. .
それに加えて、絶縁被膜６は少なくとも片側電極４の縁
部７を被覆するよう形成されている。これにより、第４
図で示すように絶縁被膜６を設けないものの沿面絶縁距
離l1よりも、第５図に示す如く絶縁被膜６が電極４の縁
部７に被さる幅分だけ電極4,5の面間における沿面絶縁
距離l2を長く取ることができる。また、この絶縁被膜６
が電極４の縁部７に被さる分たけ電極４の面積を確保で
き、電極４の面積を小さくしなくても沿面絶縁距離l2を
長く取ることができる。従って、電気機械変換効率が下
がることによる特性の悪化も防ぐことができる。In addition, the insulating coating 6 is formed so as to cover at least the edge portion 7 of the one-sided electrode 4. As a result, the fourth
As shown in FIG. 5, the creeping distance between the surfaces of the electrodes 4 and 5 is larger than the creepage insulation distance l 1 without the insulating coating 6 by the width covered by the edge 7 of the electrode 4 as shown in FIG. The insulation distance l 2 can be long. Also, this insulating film 6
It is possible to secure the area of the divided electrode 4 that covers the edge portion 7 of the electrode 4, and it is possible to increase the creeping insulation distance l 2 without reducing the area of the electrode 4. Therefore, it is possible to prevent deterioration of characteristics due to a decrease in electromechanical conversion efficiency.
各電極4,5は夫々全面が絶縁被膜６で被覆されていない
ため、絶縁被膜６による質量的負荷を電極4,5に与える
のを抑えることができる。また、絶縁被膜６は低密度の
ソルダーレジスト材で形成されているから、セラミック
基板１の機械的振動を阻害するのも妨げる。Since the entire surface of each of the electrodes 4 and 5 is not covered with the insulating coating 6, it is possible to prevent the insulating coating 6 from exerting a mass load on the electrodes 4 and 5. Further, since the insulating coating 6 is formed of the low-density solder resist material, it also prevents the mechanical vibration of the ceramic substrate 1 from being disturbed.
上述した実施例では絶縁被膜６を入力側の電極４の縁部
７に被せることにより形成したが、この絶縁被膜６は出
力側の電極５の縁部に被せて形成してもよく、或いは両
電極4,5の各縁部に共に被せて形成してもよい。また、
上述した実施例ではセラミックフィルタを構成する場合
を例示したが、それ以外に圧電ブザー，圧電スピーカー
等の圧電セラミック振動子を構成する場合にも適用する
ことができる。In the embodiment described above, the insulating coating 6 is formed by covering the edge 7 of the input side electrode 4, but the insulating coating 6 may be formed by covering the edge 7 of the output side electrode 5, or both. It may be formed by covering both edges of the electrodes 4 and 5 together. Also,
In the above-described embodiments, the case of forming a ceramic filter is illustrated, but the invention can be applied to the case of forming a piezoelectric ceramic vibrator such as a piezoelectric buzzer or a piezoelectric speaker.
考案の効果 以上の如く、本考案に係るセラミック電子部品に依れ
ば、セラミック基板の同一平面上に間隔を隔てて設ける
入出力の各電極をソルダーレジスト材の絶縁被膜で確実
に絶縁でき、銀マイグレーション現象の発生も防ぐこと
ができる。Effect of the Invention As described above, according to the ceramic electronic component of the present invention, the input and output electrodes provided on the same plane of the ceramic substrate with a space therebetween can be reliably insulated by the insulating coating of the solder resist material. The occurrence of migration phenomenon can also be prevented.
また、電極の縁部に被さる絶縁被膜の幅分だけセラミッ
ク基板の決められた面積の中で電極の面積を確保でき、
各電極の面間における沿面絶縁距離も長く取ることがで
きる。Also, the area of the electrode can be secured within the determined area of the ceramic substrate by the width of the insulating coating covering the edge of the electrode,
The creeping insulation distance between the surfaces of the electrodes can be increased.
各電極は鍛造処理で強度を向上でき、絶縁被膜は入出力
の電極に加わえる質量負荷を少なく抑え、セラミック基
板の機械的振動も阻害しないことから、特性に優れて信
頼性の高いセラミック電子部品として構成することがで
きる。The strength of each electrode can be improved by forging, the insulating coating suppresses the mass load applied to the input and output electrodes, and it does not interfere with the mechanical vibration of the ceramic substrate, so it is a highly reliable and reliable ceramic electronic component. Can be configured as.
第１図は本考案に係るセラミック電子部品の一例を示す
平面図、第２図は同部品の側断面図、第３図は同部品の
製造工程を示す説明図、第4,5図は電極間の沿面絶縁距
離を比較して示す説明図である。 1:セラミック基板、2:全面電極、3:電極間隔、4,5:入出
力の各電極、6:ソルダーレジスト材の絶縁被膜、7:電極
の縁部。FIG. 1 is a plan view showing an example of a ceramic electronic component according to the present invention, FIG. 2 is a side sectional view of the same, FIG. 3 is an explanatory diagram showing a manufacturing process of the same, and FIGS. It is explanatory drawing which compares and shows the creepage insulation distance between them. 1: Ceramic substrate, 2: Full surface electrode, 3: Electrode spacing, 4,5: Input / output electrodes, 6: Insulating coating of solder resist material, 7: Edge of electrode.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭53−65685（ＪＰ，Ａ) 実開 昭59−61626（ＪＰ，Ｕ) 実開 昭57−91332（ＪＰ，Ｕ) 実開 昭55−124916（ＪＰ，Ｕ) 実開 昭62−169534（ＪＰ，Ｕ) 特公 昭44−14316（ＪＰ，Ｂ１) 特公 昭60−3245（ＪＰ，Ｂ２) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-53-65685 (JP, A) Actually open 59-61626 (JP, U) Actually open 57-91332 (JP, U) Actually open 55- 124916 (JP, U) Actually open Sho 62-169534 (JP, U) Japanese Patent Sho 44-14316 (JP, B1) Japanese Official Sho 60-3245 (JP, B2)
Claims (1)
で取り囲むよう入出力の各電極をセラミック基板の同一
平面上に設けるセラミック電子部品において、 各電極の全面を被覆することなく、電極間のセラミック
基板の平坦面と、少なくとも片側の電極の縁部とを低密
度のソルダーレジスト材で絶縁被覆し、且つ、各電極を
バレル研摩で鍛造処理してなることを特徴とするセラミ
ック電子部品。1. A ceramic electronic component in which input and output electrodes are provided on the same plane of a ceramic substrate so as to surround inner electrodes with outer electrodes spaced apart from each other. 2. A ceramic electronic component, characterized in that the flat surface of the ceramic substrate and the edge of at least one of the electrodes are insulation-coated with a low-density solder resist material, and each electrode is forged by barrel polishing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986086296U JPH0749859Y2 (en) | 1986-06-06 | 1986-06-06 | Ceramic electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986086296U JPH0749859Y2 (en) | 1986-06-06 | 1986-06-06 | Ceramic electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62198718U JPS62198718U (en) | 1987-12-17 |
| JPH0749859Y2 true JPH0749859Y2 (en) | 1995-11-13 |
Family
ID=30942469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986086296U Expired - Lifetime JPH0749859Y2 (en) | 1986-06-06 | 1986-06-06 | Ceramic electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0749859Y2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5838005B2 (en) * | 1976-11-24 | 1983-08-19 | 松下電器産業株式会社 | piezoelectric vibrator |
| JPS55124916A (en) * | 1979-03-16 | 1980-09-26 | Mitsubishi Electric Corp | Method of removing foreign material of gas insulated electric device |
| JPS5791322U (en) * | 1980-11-26 | 1982-06-05 | ||
| JPS5961626U (en) * | 1982-10-14 | 1984-04-23 | 株式会社村田製作所 | Chip type piezoelectric resonator structure |
| JPS62169534U (en) * | 1986-04-17 | 1987-10-27 |
-
1986
- 1986-06-06 JP JP1986086296U patent/JPH0749859Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62198718U (en) | 1987-12-17 |
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