JPH0750847B2 - Bias circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a feedback-type bias circuit used in, for example, a semiconductor circuit (particularly a semiconductor integrated circuit).

[Technical background of the invention and its problems]

In an electronic circuit, the bias circuit determines the operating condition of the electronic circuit and is indispensable. First
A feedback type bias circuit which is most often used in a semiconductor integrated circuit is shown in FIG.

Transistors Q ₁ to Q ₃ in the place surrounded by the broken line, the resistor R ₁ to R
₃ constitutes a bias circuit, and the transistor Q ₄ and the resistor R ₄ and the transistors Q ₅ and R ₅ are the current sources driven by the bias circuit, which determine the operating currents of the circuit 1 and the circuit 2, respectively. ing. The emitter current I _E3 of the transistor Q ₃ is However, V _BEn : _{Base of} transistor Q _n (n = 1,2, ...)
It becomes the forward drop voltage between the emitters. Since the transistor Q ₃ and the transistors Q ₄ , Q ₅ ... Form a current mirror circuit, the transistors Q ₄ , Q ₅ ,
The emitter current I _E4 , I _E5 , ... of Becomes Therefore, an arbitrary bias current can be obtained by determining the emitter current I _E3 by the bias circuit and determining the resistance value ratio of the resistors R ₃ , R ₄ , R ₅ , ...

The advantage of this feedback type bias circuit is that the impedance at the point A can be made extremely low by the feedback loop, so even if the load connected to the point A (the bases of the transistors Q ₄ , Q ₅ , ... In the figure) becomes heavy, Transistor determined in (1)
It means that the emitter current I _{E3 of} Q ₃ hardly changes. For example, the transistors Q _4, Q ₅ is connected to the point A, it is possible to cascaded transistors ... etc., and these transistors Q _4, Q _5, ... of the h _FE (grounded emitter current amplification factor) is Even if it decreases, the influence hardly appears on the bias circuit and the emitter currents of the transistors Q ₄ , Q ₅ , ....

However, this feedback type bias circuit performs negative feedback of 100%, so the stability of the circuit is poor. The point becomes a capacitive load, and there is a disadvantage that the gain margin and the phase margin are lost in a high frequency region, and oscillation often occurs.

Therefore, conventionally, a feedback type bias circuit as shown in FIG. 2 or 3 has been used.

First, the circuit shown in FIG. 2, removes the circuit shown in Figure 1 of the above transistor Q _2, the resistor R _2, the transistor Q ₁
The emitter current transistor Q ₃ (and Q _4, Q _5, ...) and in loop gain very low, high frequency transistors Q _{1 T (Transition} Frequency) by only to base current extremely small It is smaller and the phase margin is larger.

The circuit of FIG. 2 is stable and does not oscillate, but since _T of the transistor Q ₁ is made low, the impedance at the point A rises at a high frequency, causing interference between circuits often connected to the point A. There is a defect that causes it. For example, a transistor
Circuit 1 and circuit 2 interfere via the base-collector capacitance of Q ₄ and Q ₅ .

In the circuit shown in FIG. 3, a capacitor C is connected between the collector of the transistor Q ₃ and the ground (GND), and an integrator circuit composed of the resistor R ₁ and the capacitor C reduces the loop gain at high frequencies to reduce the phase margin. It is a big one.

Although this method also stabilizes the circuit, it requires a capacitor and is not preferable for a semiconductor integrated circuit.

[Object of the Invention]

This invention operates stably without using a capacitor,
It is an object of the present invention to provide a bias circuit suitable for forming a semiconductor integrated circuit having an extremely low output impedance even in a high frequency region.

[Outline of Invention]

According to the present invention, a load resistance is added to the collector of the emitter follower in the feedback loop to create an equivalent capacitance by the Miller effect and perform phase compensation.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a circuit diagram of one embodiment. In FIG. 4, a point different from the original FIG. 1 is that a resistor R _M is inserted between the collector of the transistor Q ₁ forming the emitter follower and the power supply V _CC . Explaining the connection configuration of each part in detail, the collector of the transistor Q ₁ is connected to the power supply V _CC via the resistor R _M , and the emitter is connected to the collector and base of the transistor Q ₂ . The emitter of transistor Q ₂ is a resistor R ₂
Grounded through. The base of transistor Q ₂ is connected to the base of the transistor Q _3, the collector of the transistor Q ₃ are connected through a resistor R ₁ to the power supply V _CC, and the emitter is grounded through a resistor R _3. Also transistors
The base of Q ₁ is connected to the collector of transistor Q ₃ .

By adding a resistor R _M for explaining the operation in the above configuration, the gain G from the base to the collector of the transistor Q ₁ is Becomes However, r _en is the emitter internal impedance of the transistor Q _n . Here, if the collector-base capacitance of the transistor Q ₁ is C _cb , the capacitance C _M equivalently seen from the base of the transistor Q ₁ is Becomes This capacitance C _M is equivalently connected between the base of the transistor Q ₁ and the ground as shown in FIG. If the value of R _M is chosen to be large just before the transistor Q ₁ saturates, the capacitance C _M will be the largest, as can be seen from equation (4). This circuit electrically operates in exactly the same way as the circuit described in FIG.

Now, let's consider using actual constants.

When V _CC = 5V, I _E2 = I _E3 = 0.1 mA, and the potential at point A is 1 V, the resistance values are R ₁ = 33 kΩ, R ₂ = R ₃ = 3 kΩ. However, V _BEn is 0.7V. Furthermore, if the collector-emitter voltage of the transistor Q ₁ is set to 1 V, then R _M = 30 kΩ. The collector-base capacitance C _cb of transistor Q ₁
If it is 0.3 pF, the capacitance C _M can be calculated from equation (4). Becomes However, Is calculated as Here, k: Boltzmann's constant, q: electron load, T: absolute temperature 300 ° K.

In this case, the frequency _P of poles made by R ₁ and C _M is In the region of the frequency (100MHz to 200MHz) that normally oscillates, the loop gain becomes sufficiently small and the phase margin becomes sufficiently large.

The emitter current I _E1 of the transistor Q ₁ can also be made to flow sufficiently, it is possible to set high _T of the transistor Q _1, the impedance of an A point is lower at higher frequencies.

FIG. 5 shows a second embodiment of the present invention. The illustrated embodiment differs from the embodiment of FIG. 4 in that a resistor R _S is inserted between the connection point of the resistor R ₁ and the collector of the transistor Q _{3 and} the base of the transistor Q ₁ . In this case, the pole frequency _P is created by the combined resistance (R ₁ + R _M ) and the capacitance C _M ,
Therefore, this can be made even lower than that of the embodiment of FIG.

FIG. 6 shows a third embodiment of the present invention. In the illustrated embodiment, the transistor Q ₂ is omitted from the embodiment of FIG. 4, and the emitter of the transistor Q ₁ is connected to the base of the transistor Q ₃ and is also connected to the ground via the resistor R ₂ . It is a thing. In this case, as compared with FIG. 4, the value of the resistor R ₂ becomes large and the Miller effect becomes small, so that the pole frequency _P becomes high, but phase compensation is possible.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.
In the embodiment shown in the figure, similarly to the modification of FIG. 4 as shown in FIG. 5, a resistor R _S is added to FIG. 6 to lower the pole frequency.

In addition, although not shown, in addition to this, when the resistors R ₂ and R ₃ are removed in FIGS. 4 and 5, the emitters of the transistors Q ₂ and Q ₃ are directly grounded, and in FIGS. Resistance R _{3 in} Fig. 7
Is eliminated and the emitter of the transistor Q ₃ is directly grounded, a larger phase compensation effect can be obtained.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a bias circuit that operates stably without using a capacitor and that has a very low output impedance even in a high frequency range and that is suitable for a semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first example of a conventional bias circuit,
FIG. 2 is a circuit diagram showing a second example of a conventional bias circuit,
FIG. 3 is a circuit diagram showing a third example of a conventional bias circuit,
FIG. 4 is a circuit diagram showing a first embodiment of the bias circuit according to the present invention, FIG. 5 is a circuit diagram showing a second embodiment of the present invention, and FIG. 6 is a third embodiment of the present invention. Circuit diagram,
FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention. Q ₁ ~Q ₃ ...... _{transistor, R 1 ~R 3, R M} , R S ...... resistance, C _cb,
C _M …… Capacity

Claims (1)

[Claims] 1. A first transistor having a collector connected to a power source through a first resistor, an emitter connected to a reference potential terminal, and a base connected to an output terminal; and a collector connected through a second resistor. A second transistor whose emitter is connected to the base of the first transistor as a negative feedback path and whose base is connected to the collector side of the first transistor. , A bias circuit having a phase margin for preventing oscillation by an integrating circuit formed by a second resistor and a parasitic capacitance associated with the first and second transistors.