JPH0752379B2 - Personal computer system - Google Patents

Abstract

This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access. <IMAGE>

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer, and more particularly to a personal computer capable of supplying continuous processing by generating a RESET signal while preventing a system failure.

[0002]

BACKGROUND OF THE INVENTION General personal computer systems and IBM personal computers have become widely used, especially to provide computer power to many parts of modern society. Personal computer systems typically include a single system processor with associated volatile and non-volatile memory, a display monitor,
As a desktop, floor standing, or portable microcomputer consisting of a system unit with a keyboard, one or more diskette drives, fixed disk storage and an optional printer,
Can be specified. One of the salient features of these systems is the use of motherboards or system planers to connect these elements together. These systems are primarily designed to give independent computer power to a single user and are inexpensive for personal or small business purchases. Examples of such personal computer systems include IBM personal computer AT and IBM personal system /
2 Models 25, 30, L40SX, 50, 55, 6
5, 70, 80, 90 and 95.

These systems fall into two general families. The first family, commonly referred to as the Family I model, is the IBM personal computer AT
And other "IBM compatible" machines. The second family, referred to as the Family II model, uses IBM's Micro Channel Bus Architecture embodied by IBM's Personal System / 2 models 50-95. In the early days, the Family I models were typically Intel's 8 popular system processors.
A 088 or 8086 microprocessor was used.
These processors have the ability to address 1 megabyte of memory. Recent Family I and Family II models are faster than Intel's 8028
6, 80386 and 80486 microprocessors are commonly used, which are the slower Intel 80
It can operate in real mode to emulate an 86 microprocessor or, for some models, in protected mode, which extends the address range from 1 megabyte to 4 gigabytes. In summary,
The real mode features of the 80286, 80386 and 80486 processors provide hardware compatibility with software written for the 8086 and 8088 microprocessors.

In all such personal computers that use Intel's X86 microprocessor, the microprocessor that serves as the system CPU is the system's initialization power-up or some operating condition (the latter example is sometimes known as the HOTRSET signal). ), Reset by the appropriate RESET signal. Resetting the X86 processor completes any operations in progress and returns the processor to a known state. Anomalous completion of an ongoing cycle causes a disruption in computer system operation for several different reasons. This is especially true when the computer system is an advanced system such as one of the Family II systems described above. For example, if the microprocessor is receiving a HOLD signal while the RESET signal is also received by the microprocessor, the response HLDA acknowledge signal of the microprocessor may be missing or missing and the normal flow of processing by the system. Is damaged. Similarly, by receiving a HOLD during a reset interval triggered by RESET, the initial HLD that is subsequently lost.
A acknowledgment will be obtained, with similar results as the first error mentioned above. A RESET received during an active bus cycle causes a bus cycle truncation and again causes a system error that leaves the slave device in an unrecoverable state. Finally, if the system involved contains an alternate master on the local processor bus, receipt of a RESET by the default system processor (usually the CPU) causes the processor to state the local processor bus associated with the alternate master. Acquire a local bus that is being reset regardless.

Such problems with Intel's X86 processor have been previously recognized. One solution is 198
U.S. Pat. No. 4,783 of Curry assigned to Compaq Computer Corporation, issued Nov. 22, 1996
No. RES, proposed in US Pat. No. 7,031, until pending microprocessor HOLD signal is provided.
The ET signal is also required to wait. However, with this proposed solution, the HLDA signal may be lost, cycle truncation may occur, or unnecessary contention between the skip master and the alternate master may leave parts of the system in an indeterminate state.

[0006]

In view of the above points,
The object of the invention is to ensure a continuous sequence of processing, even if a RESET signal is received which may interrupt normal processing.

[0007]

In order to achieve the objects of the present invention, to recognize that a RESET signal has been provided, to verify the state of the microprocessor and associated local processor bus, and so on. By doing so, provision is made for validating the RESET signal only when the normal processing flow can be continued.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENT A microcomputer embodying the present invention is shown at 10 in FIG. The computer 10 has an accompanying monitor 11, a keyboard 12, and a printer or plotter 14. The computer 10 has a cover 15. The cover 15, as shown in FIG. 2, cooperates with a chassis 19 that defines an enclosed and shielded capacity to receive power-driven data processing and storage elements for processing and storing digital data. . At least certain of these elements may be mounted in a multilayer planar 20 or mother board mounted on a chassis 19, as disclosed above, as well as floppy disk drives, direct access storage devices, accessory cards or boards. Provide means for electrically interconnecting the elements of computer 10, including other associated elements of various forms such as.

The chassis 19 has a base and rear panel (FIG. 2) and defines at least one open compartment for receiving data storage devices such as disk drives for magnetic or optical disks, tape backup drives and the like. In the illustrated form, the upper compartment 22 is used to house a first size (known as 3.5-inch drive-like) peripheral drive. A floppy disk drive that is a removable media direct access storage device that houses a diskette inserted therein and that can be used to receive, store and transmit data as is generally known using the diskette. Are supplied to the upper compartment 22.

Before relating to the above configuration of the present invention, it is worth reviewing the general operation of personal computer system 10. In FIG. 3, the planar 2
Personal computer system describing various elements of a computer system, such as system 10 according to the present invention, including components mounted on a computer, connection of a planar to I / O slots, and other hardware of the personal computer system. A block diagram of is shown. C
The PU 32 is connected to the planar. Any suitable microprocessor can be used as the CPU 32, but one suitable microprocessor is the 80386 sold by Intel. CPU32 is high-speed CP
U local bus 34 allows bus interface controller 35, single in-line memory module (SIMM
s) a volatile random access memory (RAM) 36 shown here and a BIOS ROM storing instructions for basic input / output operations to the CPU 32.
38. The BIOS ROM 38 includes a BIOS used as an interface between the I / O device and the operating system of the CPU 32. The instructions stored in the ROM 38 are stored in the RAM 36 to reduce the execution time of the BIOS.
Can be copied.

The present invention is described below with particular reference to the system block diagram of FIG. 3, and it is contemplated that the apparatus and method according to the present invention may also be used with other hardware structures of a planar board. It will be understood at the beginning of the description. For example, the system processor is an Intel 80486 microprocessor.

Returning to FIG. 3, CPU local bus 34 (consisting of data, address and control elements) also couples numerical or mathematical coprocessor 39 and small computer system interface (SCSI) controller 40 to CPU 32. As known to those skilled in the computer design and operation arts, SCSI controller 40 is facilitated by read only memory (ROM) 41, RAM 42 and the I / O connections shown on the right side of the figure. Various types of suitable external devices. SCS
The I-controller 40 functions as a storage controller for control storage memory devices such as fixed or removable media electromagnetic storage devices (known as hard and floppy disk drives), electro-optical, tape and other storage devices.

Bus interface controller (BI
C) 35 connects the CPU local bus 34 and the I / O bus 44, and functions as a protocol translator, a memory controller, a DMA controller, etc. of the functions. By means of the bus 44, the BIC 35 is provided with a plurality of I / Os for accommodating microchannel adapter cards 45 which are further connected to I / O devices and memories (not shown).
It is coupled to an optional functional bus such as a Micro Channel bus with slots. The I / O bus 44 contains address, data and control elements. The I / O bus 44 has a bus specification configuration other than the Micro Channel specification.

The I / O bus 44 has a video RAM (VRAM) for storing character-based information (shown at 48) and also for storing graphic or image-based information (shown at 49). Various I / O elements such as an associated video signal processor 46 are coupled. The video signal exchanged with the processor 46 is supplied to a monitor or other display device via a digital-analog converter (DAC) 50. Provision is made to couple the VSP 46 directly with what is referred to herein as a natural image input / output, which may take the form of a video recorder / reproducer, camera, etc. The I / O bus 44 is also
It is coupled to a digital signal processor (DSP) 51. The DSP 51 has a DSP 51 and an associated instruction RAM 52 and data RAM 54 that can store software instructions for signal processing with data included in such processing. The DSP 51 provides audio input and output processing provided by the audio controller 55 and processing of other signals provided by the analog interface controller 56. Finally, the inputs and outputs are replaced by conventional peripheral devices including floppy disk drives, printers or plotters 14, keyboards 12, mice or pointing devices (not shown), and by serial port means, I / O The O-bus 44 is coupled to an I / O controller 58 associated with an electrically erasable / programmable read only memory (EEPROM) 59.

Before returning to the more details of the functional description given to the personal computer 10, it is appropriate to first consider the support by the personal computer known as multiple masters or bus masters. As used herein, a "master" is a processor or circuit designed to obtain control over the bus as well as drive address, data and control signals on the bus. Having such functionality allows the master device to transfer information between the system memory and other devices.

It has been proposed to classify masters into three types. In other words, the system master (usually CP
U), a DMA controller and a bus master. The system master controls and processes the system configuration. There is usually an abbreviated master in the system. The default master owns the bus when no other master needs it. D
The MA master transfers data between the DMA slave and the memory slave, and is an arbiter D without arbitrating the bus.
It is a special type of master that serves MA slaves. As used herein, a bus master arbitrates bus usage and supports transferring information to I / O slaves or memory slaves.

Since the bus master does not necessarily need a processor, it may be confusing as to what makes a device a "bus master". Also, when accessed by another bus master, the bus master is required to respond as a slave. Bus masters are distinguished by their ability to gain control of the bus through arbitration and control of the execution of defined bus cycles. Generally, there are three types of bus masters. That is, full function, special function controller and programmable special function controller.
These basic differences are flexibility, functionality and cost. Full-function bus masters are the most flexible and functional and costly. Full-featured bus masters typically have their own programmable CPU and can control all system resources, including operating system software. The specific function controller is
It lacks the most flexibility and functionality and is inexpensive. Typically, a specific function controller uses logic circuitry rather than a CPU to perform a specific function and requires little or no assistance from other masters. The programmable special function controller resides in the area between the other two. The fundamental difference between a special function and programmable special function controller is the ability to change the functionality and / or the execution characteristics of the bus master. Such changes can be accomplished through the use of processing units or settable registers.

In the definition given here, the CPU 32,
The MCPU 39 and SCSI controller 40 all function as a master coupled to or directly on the local bus 34. On the other hand, the I / O controller 5 mounted in the micro channel slot
8, DSP51, VSP46 and accessory board 45
All function as masters to or directly on the I / O bus 44.

According to the present invention, the X86 RESET or CPU The signal known here as the RESET signal corresponds to RESET or HOTRESET, B
Generated by IC 35 and only after BIC 35 gains control of local processor bus 34 and I / O bus 44. Bus interface controller 35
Recognizes receipt of a reset signal to initiate a reset of CPU microprocessor 32, and access to local processor bus 34 and I / O bus 44 by any device potentially requesting such access. Until the bus interface controller inhibits
Delay delivery of the RESET signal to the microprocessor. BIC35 is a bus (ARBUS0, 1, 2,
3; PREPEMPT #; and BURST #) by exchanging certain signals to function as a central arbitration control point (CACP) for the I / O bus 44 and also to the local processor bus 34 (ARBUS 0, 1, 2, 3). ; PREE
MPT #; BURST #; BRQ1 # to BRQn #;
BGT1 # to BGTn #; CACP HOLD; CA
CP HLDA; CPU HOLD; and CPU HL
CACP, I / O bus 44 directly coupled to DA)
And acts as a Local Bus Arbitration Control Point (LBACP) by exchanging certain signals at the master. Some of these signals are shown in FIGS. 4 and 5, where an exemplary operational sequence for personal computer 10 in accordance with the present invention is shown. 4 and 5
In each of the figures, the passage of time is indicated by the clock cycle on line CLK2.

In the sequence of FIG. 4, the omitted master is
HOTRSET is required while controlling the I / O bus 44.
Required (first position shown in 1) and pending
Will be In that case, the BIC 35 is shown in (2).
CPU in second position Activate the HOLD signal
It The processor then acknowledges in the third position (3).
Ridge signal CPU Release the bus by issuing HLDA
To service pending RESET requests
Prepare BIC35. CPU RESET is BIC
35, the reset procedure is CL
K2 (shown between 4 and 5 which are the 4th and 5th positions
) For 40 cycles. Reset
When the bus master request is pending,
If not, the system has reached the initial state and BIC3
5 is a CPU Make HOLD inactive.

The sequence of FIG. 5 is H during the arbitration cycle.
The reception of the OTRESET signal is shown. In the first position (1)
As shown, ARB / GNT # is high or active.
HOTRESET is requested by the system during
To be done. CPU HOLD is then moved to the second position (2)
Is activated in the processor, then the third place
Let go of the bus at step (3). CPU RESET is that
From CLK2 (4 and 5 which are the 4th and 5th positions).
40 cycles of (between), it becomes active by BIC35.
Be done. After internal initialization, the processor is in the sixth position.
In (6), the hold state is set. Then enter / exit the bus
7th position (7) to give force master request
Therefore, the CACP function of the BIC 35 is free.

[0022]

According to the present invention, sequential processing can be continued even if a RESET signal that may interrupt normal processing is received.

[Brief description of drawings]

FIG. 1 is a perspective view of a personal computer embodying the present invention.

2 is an exploded perspective view of certain elements of the personal computer of FIG. 1 including a chassis, a cover and a planar plate and showing certain relationships between these elements.

FIG. 3 is a schematic diagram of specific elements of the personal computer of FIGS. 1 and 2.

FIG. 4 is a timing chart showing the personal computer of FIG. 3 when a reset signal is generated according to the present invention.

5 is a timing chart showing the personal computer of FIG. 3 when a reset signal according to the present invention is generated.

[Explanation of symbols]

 34 high-speed CPU local bus 35 bus interface controller 44 I / O bus 58 I / O controller

Front Page Continuation (72) Inventor Eric Mattissen Northwest Seventh Street 800, Boca Raton, Florida, United States 800 (72) Inventor Dennis Lee Muller Southridge Road, Delray Beach, Florida 2531 (72) Inventor Jonathan Henry Raymond 5394 (72) Inventor Esmile Tachakori, Essec Junction, Vermont, USA United States, Delray Beach, FL, USA, Southwest Twentysequen Avenue 2935 No. 102 (56) Reference JP 2 -89154 (JP, A)

Claims (3)

[Claims] 1. A personal computer system comprising: (a) a high speed local processor data bus; (b) an input / output data bus; and (c) a resettable microprocessor connected to the local processor data bus. (D) a bus interface controller connected to the local processor data bus and the input / output data bus for controlling communication between the local processor data bus and the input / output data bus, An interface controller includes: (i) the resettable microprocessor for access to the local processor data bus;
Arbitration with another master device connected to the local processor data bus, (b) connecting to the local processor data bus and the input / output data bus for access to the input / output data bus Arbitration with the device, (re) receive a reset signal (HOTRESET) to initiate resetting of the microprocessor, and using a hold signal (CPU_HOLD) and a hold acknowledge signal (CPU_HLDA), A personal computer system characterized by delaying the output of a reset signal (CPU_RESET) to the microprocessor until the bus interface controller itself acquires control of the local processor data bus and the input / output data bus. 2. A personal computer system, comprising: (a) a high speed data bus; (b) an input / output data bus; (c) a resettable microprocessor connected to the high speed data bus. ) A volatile memory coupled to the high speed data bus for temporary storage of data; (e) a storage memory device for non-volatile storage of data; (f) the high speed data bus and the storage memory. A storage device controller coupled to the storage memory device for coordinating communication with a device; and (g) the high speed data bus for controlling communication between the high speed data bus and the input / output data bus. And a bus interface controller connected to the input / output data bus, wherein the bus interface controller is (i) For access to the fast data bus,
Arbitration between the resettable microprocessor and the storage device controller, and (b) connected to the high speed data bus and the input / output data bus for access to the input / output data bus. Arbitration with the device, (re) receive a reset signal (HOTRESET) to initiate the reset of the microprocessor, and use the hold signal (CPU_HOLD) and hold acknowledge signal (CPU_HLDA) A reset signal (CPU--
A personal computer system characterized by delaying the output of RESET). 3. A personal computer system comprising: (a) a high speed data bus; (b) a microprocessor connected to the high speed data bus; and (c) a numerical coprocessor connected to the high speed data bus. (D) a volatile memory coupled to the high speed data bus for temporary storage of data, (e) a storage memory device for non-volatile storage of data, (f) the high speed data bus, A storage device controller coupled to the storage memory device to coordinate communication with the storage memory device; (g) an input / output data bus; and (h) an input connected to the input / output data bus. / Output controller, (i) a digital signal processor connected to the input / output data bus, and (j) video connected to the input / output data bus. A signal processor and (k) a bus interface controller connected to the high speed data bus and the input / output data bus for controlling communication between the high speed data bus and the input / output data bus, The bus interface controller is (i) for accessing the high-speed data bus,
Arbitration between the resettable microprocessor and the storage device controller, and (b) with the input / output controller, the digital signal processor and the video signal processor for access to the input / output data bus. Arbitration between, and (H) receives a reset signal (HOTRESET) to initiate a reset of the microprocessor, and uses a hold signal (CPU_HOLD) and a hold acknowledge signal (CPU_HLDA) to A reset signal (CPU--
A personal computer system characterized by delaying the output of RESET).