JPH0755961A - Solar cell clock - Google Patents

Abstract

PURPOSE:To obtain a solar cell clock which enables charging of a capacitor of a large capacity even under a low illuminance and of which the driving characteristic of a motor is stable. CONSTITUTION:In a solar cell clock equipped with a capacitor 3 of a large capacity and a capacitor 11 of a small capacity, a time division signal preparing circuit is provided and the capacitor 3 of the large capacity and the capacitor 11 of the small capacity are charged alternately by a division signal when re-irradiation of light is started after the capacitor 3 of the large capacity finishes discharge, while a motor is driven in the state of the capacitor 11 of the small capacity being cut off from a solar cell 1, at the time of a quick start. Accordingly, the capacitor 3 of the large capacity can be charged even under a low illuminance and, besides, the driving characteristic of the motor is made stable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charging characteristic of an electronic timepiece having a motor load driven by a solar cell, a large-capacity capacitor as a condenser, and a small-capacity capacitor for a quick start. The present invention relates to improvement of motor driving characteristics.

[0002]

2. Description of the Related Art Conventionally, by combining a solar cell and an electric double layer type large-capacity capacitor, a long-life electronic timepiece that does not require battery replacement has been commercialized. However, since the large-capacity capacitor has a large capacity, once it is completely discharged by leaving the electronic timepiece in a dark place,
There is a problem that it takes too long to start the operation of the timepiece because it takes a long time to charge up to the operation start voltage of the timepiece circuit even if it is put out in a bright place and exposed to light. However, the proposal to solve this problem is Japanese Patent Fair 4-8.
It is carried out in Japanese Patent Publication No. 0355 and will be described below with reference to the drawings.

FIG. 4 is a block diagram of a conventional solar cell timepiece, 1 is a solar cell, 2 is a diode for preventing backflow to the solar cell, 3 is an electric double layer type large capacity capacitor, and 4 is a timepiece. Circuit, 5 is a constant voltage circuit, 6 is a discharge diode,
Reference numeral 7 is a voltage detection circuit, 8 is a charging circuit, 9 is a diode for preventing backflow, 10 is a charging transistor, and 11 is a small capacity capacitor. The generated voltage of the solar cell 1 is
When the forward voltage of the gate 2 is exceeded and the minimum operating voltage or more is reached, the clock circuit 4 starts to function. Here, the charging transistor 10 does not turn on until the voltage detection circuit 7 detects a voltage level at which the clock circuit 4 can sufficiently operate and generates a detection signal. When the voltage detection circuit 7 detects that the voltage generated by the solar cell 1 is at a sufficiently high voltage level, the charging transistor 10 is turned on and the excess current generated by the solar cell 1 charges the large-capacity capacitor 3. Done. When the terminal voltage of the large-capacity capacitor 3 rises due to sufficient charging, the constant voltage circuit 5 controls the rated voltage. or,
When the illuminance is lowered, the clock circuit 4 is driven by the charges accumulated in the large-capacity capacitor 3 via the diode 6.

While the illuminance is low as in the above configuration, the small capacity capacitor 1 is turned off by turning off the charging circuit 8 and the charging transistor 10 while the voltage detection circuit 7 is detecting.
The clock circuit 4 is driven only by 1 and when the voltage detection circuit 7 detects a voltage increase more than that for maintaining the clock function, the charging transistor 10 is turned on to charge the large-capacity capacitor 3 with the surplus current of the solar cell 1. The clock circuit 4 can be quickly started without waiting for the charging time of the large-capacity capacitor 7.

According to the configuration shown in FIG. 4, it is basically possible to perform a quick start without waiting for the charging time of the large-capacity capacitor 3 even when the large-capacity capacitor 3 is once discharged and then exposed to light. Becomes However, in the above configuration, there is a problem in that the large-capacity capacitor 3 will not be charged forever, depending on the irradiation condition when the light is applied from the discharged state. That is, considering the case where the place where the solar cell clock is re-irradiated with light is a room with low illuminance, the condition of this room is such that the generated voltage of the solar cell maintains the minimum operation start voltage. If not obtained, the clock circuit 4 starts its operation by the small capacity capacitor 11, but the voltage detection circuit 7 cannot generate a detection signal, so that the charging transistor 10 is not turned on and the large capacity capacitor 3 is charged. Not done.

Therefore, while the solar cell 1 is exposed to the light, the small-capacity capacitor 11 operates the clock circuit 4, but if the light is not exposed to light, the large-capacity capacitor 3 does not supply the voltage. The operation of the clock circuit 4 will stop. That is, the large-capacity capacitor 3 does not function as a secondary battery in an office under a slightly dark illumination or in a store.

A method for solving the above problem is disclosed in Japanese Patent Laid-Open No. 1-21.
No. 536 is proposed. This method charges the large-capacity capacitor and the small-capacity capacitor in a time-division manner and drives the motor load with the small-capacity capacitor charged by the solar cell at the time of quick start. It is possible to reliably charge the large-capacity capacitor even under lighting under bad conditions.

[0008]

However, JP-A 1-2
In the method of Japanese Patent No. 536, a small capacity capacitor and a solar cell are connected at the time of quick start.
If the incident light on the solar cell fluctuates greatly during driving of the motor load, the motor driving voltage becomes unstable, and in severe cases, the driving characteristics of the motor may be adversely affected. An object of the present invention is to solve the above problems and to provide a solar cell timepiece capable of charging a large-capacity capacitor even under slightly dark illumination and without impairing motor driving characteristics.

[0009]

The structure of the present invention for achieving the above object is as follows. In order to drive the solar cell, a small capacity capacitor having a relatively small capacity to be charged by the solar cell, a large capacity capacitor charged from the solar cell via the switch means, the small capacity capacitor and the large capacity capacitor in a time division manner. And a clock circuit having a drive signal generation circuit for outputting a motor drive signal,
In the electronic timepiece which is quick-started by the small-capacity capacitor at the start of charging of the solar cell, at the time of the quick-start, the time-division signal is output while the drive signal generating circuit is outputting the motor drive signal. It is characterized in that the small-capacity capacitor and the solar cell are substantially separated from each other by a time-division signal output from the preparation circuit.

Further, a solar cell, a small-capacity capacitor having a relatively small capacity connected to the solar cell via a backflow blocking diode, and a solar cell connected to the solar cell via a backflow blocking diode and switch means. A large-capacity capacitor, a time-division signal generation circuit for generating a time-division signal for time-divisionally driving the small-capacity capacitor and the large-capacity capacitor, and a clock circuit having a drive signal generation circuit for outputting a motor drive signal. In an electronic timepiece that starts quick by the small-capacity capacitor at the start of charging of the solar cell, during the quick start, the time-division signal is output while the drive signal generating circuit is outputting the drive signal. It is characterized in that the switch means is held in an ON state by a time division signal output from the preparation circuit.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram of a solar cell timepiece according to the invention, in which 1 is a solar cell, 3 is a large-capacity capacitor, 40 is a timepiece circuit, and has a function for driving a motor coil 50. A constant voltage circuit 55 limits the charging voltage to a limit voltage Vre for preventing the clock circuit 40 from being destroyed. Reference numeral 6 is a discharge diode, 7 is a voltage detection circuit, TN is a charging transistor, 11 is a small-capacity capacitor, and 2 and 9 are backflow blocking diodes. In the above configuration, the same numbers as those in FIG. 4 indicate the same elements and perform the same operations.

Next, the operation of FIG. 1 will be described.
When the generated voltage exceeds the forward voltage of the diode 2 and becomes equal to or higher than the operation start voltage of the clock circuit 40, the small capacity capacitor 11 is charged in a short time and the clock circuit 40 starts operating. As a result, the clock circuit 40 outputs a divided signal Pc described later to intermittently turn ON / OFF the charging transistor TN, so that the voltage generated by the solar cell 1 is applied to the large-capacity capacitor 3 only while the divided signal Pc is ON. Goes charged. That is, while the divided signal Pc is OFF, the small-capacity capacitor 11 is rapidly charged to operate the clock circuit 40, and while the divided signal Pc is ON, the large-capacity capacitor 3 is connected via the charging transistor TN. Goes charged.

When the charging voltage of the large-capacity capacitor 3 rises and becomes higher than the operation start voltage by continuing the above operation, the voltage detection circuit 7 outputs the detection signal Pk and inputs it to the clock circuit 40. Clock circuit 40
The divided signal Pc from is stopped, and the charging transistor TN
Keeps the ON state of the small capacitor 11
And the large-capacity capacitor 3 are connected in parallel.

FIG. 2 is a block diagram showing details of the clock circuit 40 in FIG. Reference numeral 41 is a crystal oscillator circuit, 42 is a frequency dividing circuit, 43 is a motor drive signal generation circuit, 44 is a motor drive circuit, and 45 is a time division signal generation for inputting a signal from the frequency division circuit 42 and outputting a division signal Pc. Circuit,
When the voltage detection signal Pk supplied to the control terminal C is H, the division signal Pc is output to the output terminal Q, and the detection signal Pk is L.
At the time of, the Vdd signal is output to the output terminal Q.

Next, the operation will be described with reference to the waveform diagram of FIG.
Charging is started by shining light from the state where the solar cell clock is completely discharged, and the voltage generated by the solar cell clock is changed to the clock circuit 4.
When the operation start voltage of 0 is reached, the clock circuit 40 starts to operate, and the crystal drive circuit 41, the frequency divider circuit 42, and the motor drive signal generation circuit 43 shown in FIG. 2 output the motor drive signal Pm. However, at this point in time, the charging voltage has not become sufficiently high, so the voltage detection circuit 7 detects a voltage drop and the detection signal Pk is H. In this state, as is well known, the warning drive signal Pml for intermittently moving the hand for 2 seconds to warn the voltage drop is output, and the coil terminals O1 and O1, respectively.
Drive signals Po1 and Po2 are supplied to the motor coil 50 via O2.

Further, the time division signal forming circuit 45 forms the division signal Pc by the frequency dividing circuit 42 and supplies it to the output terminal Ot. The division signal Pc is controlled by the detection signal Pk, and the detection signal Pk is H. Output only when the detection signal P
When k is L, the Vdd signal is output. The divided signal P
Since the charging transistor TN whose gate signal is c is off when the division signal Pc is L, the solar cell 1
The voltage generated by the
1 is charged, and the clock circuit 40 is operated by the charging voltage of the small-capacity capacitor 11.
When H becomes H, the charging transistor TN is turned ON, so that the generated voltage of the solar cell 1 also charges the large-capacity capacitor 3 through the diode 9 and the charging transistor TN. At this time, the small-capacity capacitor 11 is connected in parallel via the diode 2, but during the quick start, the charging voltage of the large-capacity capacitor 3 is low and the charging voltage of the small-capacity capacitor 11 is high. The generated voltage of the solar cell 1 is charged in the large-capacity capacitor 3 having a low voltage, and as a result, the diode 2 is reverse-biased so that the small-capacity capacitor 11 is not charged.
Separated from.

That is, when the illuminance is low and the detection signal Pk is in the H state, the clock circuit 40 is operated in the quick start state by the voltage charged in the small capacity capacitor 11 while the divided signal Pc is L. While the divided signal Pc is H, the voltage of the large capacity capacitor 3 is gradually increased by charging the large capacity capacitor 3. Further, the warning drive signal Pml is generated at the timing when the division signal Pc is H, so that the motor load is driven with the small-capacity capacitor 11 in the charged state disconnected from the solar cell 1. I have to.

When the large capacity capacitor 3 is sufficiently charged to increase the terminal voltage, the voltage detection circuit 7 inverts the detection signal Pk to L. As a result, the motor drive signal generation circuit 43 outputs the normal drive signal Pmh for performing the normal 1 second cycle hand movement by releasing the warning display mode, and the time division signal generation circuit 45 outputs the detection signal Pk of L
Then, the Vdd signal (H level) is output instead of the divided signal Pc, so that the charging transistor TN is turned on.
The small-capacity capacitor 11 and the large-capacity capacitor 3 are connected in parallel while being held in the state. Then, when the charging voltage rises due to the further increase in illuminance, the constant voltage circuit 55 eventually operates and the clock circuit 40 becomes a stable driving condition.

Next, the relationship between the motor drive timing and the motor drive characteristic will be described with reference to FIGS. FIG. 5 is a waveform diagram when a conventional driving method is performed using the circuit of FIG. 1, (a) is incident light on the solar cell 1, (b) is a motor driving signal Pml, (c). Is the divided signal Pc, (d) is the charging waveform Vcs of the small capacity capacitor 11, and (e) is the motor drive voltage Vcsm of the charging waveform Vcs.

In FIG. 5, during the T period, the motor drive signal Pm
1 shows the pulse width of 1 and shows the case where the incident light largely fluctuates by turning the direction of the clock to the light source side within this T period. In the conventional method, the divided signal Pc is in the L state as shown in (c), and the solar cell 1 is connected in parallel to the small capacity capacitor 11, so that the charging waveform V of the small capacity capacitor 11 is shown in (d).
The cs gradually rises from the reference voltage Vo, sharply rises in the T period with a large fluctuation of the incident light, and is eventually limited by the limiting voltage Vre. As a result, as shown in (e), the motor drive voltage Vcsm becomes a distorted waveform due to the large fluctuation of the incident light, and the drive by such a distorted drive waveform makes the drive characteristics of the motor unstable. Will result in

On the other hand, FIG. 6 is a waveform diagram when the drive system of the present invention is performed using the circuit of FIG. 1, and the waveforms (a) to (e) show the same waveforms as in FIG. In FIG. 6, FIG.
The difference is that the divided signal Pc shown in (c) is switched from L to H at the timing of t before the T period,
In the motor drive signal Pml shown in (b), the division signal Pc is H.
It occurs at the timing of. Therefore (d)
As shown in, the charging waveform Vcs of the small-capacity capacitor 11 gradually increases from the reference voltage Vo, but since the small-capacity capacitor 11 is disconnected from the solar cell 1 at the timing of t, the subsequent charging is not performed and the charging waveform Vcs Will maintain the voltage value at time t. As a result, as shown in (e), the motor drive voltage Vcsm is not affected by the large fluctuation of the incident light and has a rectangular waveform maintaining a substantially constant voltage level, so that the motor drive characteristic is unstable. There is nothing to do.

As described above, in the present invention, the division signal Pc is OF
The voltage charged in the small-capacitance capacitor 11 during F is used, and while the division signal Pc is ON, the movement of the division signal Pc is ON while maintaining the hand movement operation during the quick start of the electronic timepiece. The large capacity capacitor 3 is gradually charged, and when the large capacity capacitor 3 is sufficiently charged, the small capacity capacitor 11 and the large capacity capacitor 3
And are connected in parallel for stable operation of the clock circuit 40.

[0023]

As described above, according to the present invention, the small capacity capacitor and the large capacity capacitor are charged by the time division signal even when the illuminance is low. It is possible to charge the large-capacity capacitor even when the illuminance at which the generated voltage is maintained at the minimum operation start voltage is obtained, and it is possible to maintain stable operation against large fluctuations of the incident light on the solar cell. -Since it is possible to drive a load, it has a great effect on improving the reliability of the solar cell timepiece.

[Brief description of drawings]

FIG. 1 is a block diagram showing a solar cell timepiece of the invention.

FIG. 2 is a block diagram showing details of a clock circuit according to the present invention.

FIG. 3 is a waveform diagram of the present invention.

FIG. 4 is a block diagram showing a conventional solar cell timepiece.

5 is a waveform diagram when a conventional driving method is performed using the circuit of FIG.

FIG. 6 is a waveform diagram when the drive system of the present invention is performed using the circuit of FIG.

[Explanation of symbols] 1 solar cell 3 large-capacity capacitor 4, 40 clock circuit 7 voltage detection circuit 11 small-capacity capacitor 44 motor drive signal generation circuit 45 time division signal generation circuit TN charging transistor

Claims (2)

[Claims] 1. A solar cell, a small-capacity capacitor having a relatively small capacity charged by the solar cell, a large-capacity capacitor charged from the solar cell via a switch means, the small-capacity capacitor, and a large-capacity capacitor. A time-division signal generating circuit for generating a time-division signal for time-division driving, and a clock circuit having a drive signal generating circuit for outputting a motor drive signal are provided. In the quick start electronic timepiece, during the quick start, while the drive signal generating circuit is outputting the motor drive signal, the small capacity is generated by the time division signal output from the time division signal generating circuit. A solar cell clock characterized in that the capacitor and the solar cell are substantially separated. 2. A solar cell, a small-capacity capacitor having a relatively small capacity connected to the solar cell via a backflow blocking diode, and a solar cell connected to the solar cell via a backflow blocking diode and a switch means. A large-capacity capacitor, a time-division signal generation circuit for generating a time-division signal for time-divisionally driving the small-capacity capacitor and the large-capacity capacitor, and a clock circuit having a drive signal generation circuit for outputting a motor drive signal. In an electronic timepiece that starts quick by the small-capacity capacitor at the start of charging of the solar cell, during the quick start, the time-division signal is output while the drive signal generating circuit is outputting the drive signal. A solar cell timepiece characterized in that the switch means is held in an ON state by a time division signal output from a preparation circuit.