JPH0764677A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] The detection value of the power supply voltage can be lowered to extend the life of the battery, and the oscillation circuit can be operated reliably even after the detection of the drop in the power supply voltage. The purpose is to prevent the warning operation of battery exhaustion and to prevent data destruction of memory. [Constitution] A step-down circuit 14 for stepping down the battery voltage VDD and outputting the voltage VCC, a power supply voltage detection circuit 11 for detecting that the battery voltage VDD has reached a predetermined value or less, and the step-down voltage VCC and the battery voltage VSS A switching circuit 19 that is supplied and outputs one of the voltages according to the detection output of the power supply voltage detection circuit 11,
It is composed of a crystal oscillating circuit 13 that operates using the voltage output from the switching circuit as one voltage, and a CPU 15 that operates in synchronization with the clock signal XTOSC output from the crystal oscillating circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an oscillator circuit and used in a system driven by a battery.

[0002]

2. Description of the Related Art Consumer semiconductor integrated circuit devices (hereinafter referred to as L
In SI), the miniaturization of elements is progressing, and products with high added value are required. Above all, there is a strong market demand for low voltage and low power consumption, and even an 8-bit CPU is required to have power consumption as low as a calculator. Such low power consumption is due to LS
This is realized by reducing the current consumption of an oscillation circuit that consumes a large amount of current during the I operation.

FIG. 10 is a block diagram showing a configuration of an electronic notebook which is an example of a system using an LSI having a conventional oscillation circuit and having a low current consumption. In the figure, 10 is an LSI main body, and a high-potential-side power supply voltage VDD and a low-potential-side power supply voltage VSS are supplied to the LSI main body 10. In the LSI body 10, a power supply voltage detection circuit 11 for detecting the value of the power supply voltage VDD, a CR oscillation circuit 12 for initial operation, a crystal oscillation circuit (crystal oscillation circuit) 13, and a power supply voltage VDD are stepped down. A step-down circuit 14 that outputs an internal power supply voltage Vcc, a CPU (arithmetic processing unit) 15 that executes various arithmetic processes, and a liquid crystal display drive circuit 16 that generates a display signal based on data generated by the CPU are provided. .

Further, outside the LSI body 10, there are provided a key input section 17 for inputting various data, a liquid crystal display section 18 to which a display signal generated by the liquid crystal display drive circuit 16 is supplied, and the like. There is.

The CR oscillating circuit 12 becomes active when the battery is inserted into the electronic notebook for the first time or when the battery is replaced.
A clock signal CROSC is generated and supplied to the CPU 15 as a synchronizing signal.

The crystal oscillator circuit 13 starts operating simultaneously with the CR oscillator circuit 12. When the oscillation operation of the crystal oscillation circuit 13 becomes stable, the operation of the CR oscillation circuit 12 becomes
It is stopped based on the control signal CRSTOP from 15 and then the clock signal XT generated by the crystal oscillation circuit 13 is generated.
The OSC will be used by the CPU 15.

The step-down circuit 14 operates on the basis of the clock signal HCLK output from the CPU 15 after the battery is turned on, and steps down the power supply voltage VDD from the battery to, for example, 1/2 and outputs it. Therefore, when the voltage VDD of the battery is 3V, the step-down voltage V
CC becomes 1.5V. This step-down voltage VCC is a crystal oscillation circuit
13 and the liquid crystal display drive circuit 16.

The power supply voltage detection circuit 11 detects a decrease in the battery voltage VDD, and when the value of VDD drops below a predetermined value, a detection signal DEF is generated and supplied to the CPU 15. When the CPU 15 receives this signal DEF, it determines that the battery voltage has dropped,
Performs an operation to notify the user visually or audibly that the battery is dead.

In the electronic notebook having such a structure, for a circuit that consumes a particularly large amount of power, that is, for the crystal oscillation circuit 13,
The external power supply voltage VDD is not supplied as it is, but the voltage VCC which is stepped down by the step-down circuit 14 is supplied to reduce the voltage, thereby reducing the power consumption. In addition,
The step-down voltage Vcc is also supplied to the liquid crystal display drive circuit 16, because the liquid crystal display drive circuit 16 requires a ternary voltage to form a display signal.

By the way, the detected voltage value in the power supply voltage detection circuit 11 is set higher than the minimum operating voltage value of the LSI main body 10 or the minimum operating voltage value of the external circuit. When the detected voltage value is set higher than the minimum operating voltage value of the external circuit, the minimum operating voltage value of the LSI body 10 must be lower than the minimum operating voltage value of the external circuit. Further, from the viewpoint of extending the life of the battery, there is a strong tendency that the detection voltage value of the power supply voltage detection circuit 11 is set as low as possible.

On the other hand, in general, consumer type LSIs often use CR type coin type manganese dioxide / lithium batteries which have a wide range of use. Figure 11 shows this manganese dioxide
An example of the load characteristic of a lithium battery is shown. To explain the explanation of FIG. 11 in the circuit configuration of FIG. 10, the period of t1 is a period during which the LSI main body 10 operates without any problem.
The voltage drop is detected by the power supply voltage detection circuit 11 after the period of (3) is finished, and the subsequent period of t2 becomes a battery dead warning operation period. For the LSI body 10, t3
Operation guarantee is required during the period of (= t1 + t2).

Here, it is assumed that the detection voltage of the power supply voltage detection circuit 11 is 2.5 V (point A in FIG. 11). Also,
LS including variations in the detection voltage of the power supply voltage detection circuit 11
The operation guarantee voltage of I body 10 is 2.2V (point B in FIG. 11)
And At this time, the operating voltage supplied to the crystal oscillating circuit 13 in the LSI body 10, that is, the minimum operating voltage is the step-down circuit 14
It is the step-down voltage Vcc which is formed in step 2.2 and becomes 1.1V which is 2.2 steps down.

[0013]

As described above, due to the extension of the battery life, the crystal oscillation circuit at the time of low voltage operation.
The difference between the operating voltage of 13 and the threshold voltage of the transistor inside the crystal oscillating circuit 13 becomes small, so that the low voltage operation of the crystal oscillating circuit 13 cannot be expected during the period of t2 in FIG. That is, the crystal oscillating circuit 13 does not operate stably, and as a result, there is a problem that the CPU 15 cannot reliably perform the warning operation of the dead battery.

Further, inside the CPU 15, a memory in which data can be rewritten, that is, a static RAM is usually provided.
(S-RAM) is provided, and if necessary, LSI
An S-RAM is also provided outside the main body 10, but this CP cannot be guaranteed because the battery dead warning operation cannot be performed reliably.
There is also a problem that the data protection in the U15 internal or external memory cannot be performed.

The present invention has been made in consideration of the above circumstances, and an object thereof is to lower the detection value of the power supply voltage to prolong the life of the battery and to detect the decrease of the power supply voltage. It is an object of the present invention to provide a semiconductor integrated circuit device capable of performing a reliable operation of an oscillation circuit even afterward and preventing a battery exhaustion warning operation and a memory data destruction.

[0016]

A semiconductor integrated circuit device according to the present invention comprises a step-down circuit for stepping down a high potential side voltage of a power supply,
A voltage detection circuit for detecting that the high-potential-side voltage of the power supply has reached a predetermined value, and the output of the step-down circuit is the first input voltage, and the low-potential-side voltage or the high-potential-side voltage of the power supply is the second input voltage. Of the first and second input voltages according to the detection output of the voltage detection circuit, and the voltage output from the power supply voltage switching circuit. An oscillator circuit which operates using a potential difference between a high potential side voltage or a low potential side voltage of a power source as a power source voltage, and an arithmetic processing circuit which operates in synchronization with an output signal of the oscillator circuit. .

[0017]

When the value of the high potential side voltage of the power supply is higher than the value detected by the voltage detection circuit, the step-down output voltage of the step-down circuit is switched and output from the power supply voltage switching circuit and supplied to the oscillation circuit. On the other hand, when the value of the high potential side voltage of the power supply reaches the detection value in the voltage detection circuit, the power supply voltage switching circuit switches and outputs the high potential side voltage or the low potential side voltage of the power source and supplies the voltage to the oscillation circuit.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment when the present invention is applied to an LSI used in an electronic notebook as in the conventional case. It should be noted that the same reference numerals are given to the portions corresponding to those in the related art for description.

In the figure, 10 is an LSI main body, and a high-potential-side power supply voltage VDD and a low-potential-side power supply voltage VSS are supplied to the LSI main body 10. Above LSI
In the main body 10, a power supply voltage detection circuit 11 for detecting the value of the power supply voltage VDD, a CR oscillation circuit 12 for initial operation, a crystal oscillation circuit (crystal oscillation circuit) 13, a power supply voltage VDD is stepped down, and an internal power supply voltage VCC is supplied. There is provided a step-down circuit 14 for outputting, a CPU (arithmetic processing unit) 15 for executing various arithmetic processes, and a liquid crystal display drive circuit 16 for generating a display signal based on the data generated by the CPU.

A key input unit 17 for inputting various data, a liquid crystal display unit 18 to which a display signal generated by the liquid crystal display drive circuit 16 is supplied, and the like are provided outside the LSI body 10. There is.

Further, in this embodiment, a switching circuit 19 is newly provided in the LSI body 10. The switching circuit 19 is supplied with the ground voltage VSS and the step-down voltage VCC from the step-down circuit 14, and outputs both of the voltages on the basis of the switching signal SW output from the CPU 15 to the crystal oscillator circuit 13 as an operating voltage. Supply as.

The CR oscillating circuit 12 is activated when the battery is first inserted into the electronic notebook or when the battery is replaced, and the clock signal CROSC is generated and supplied to the CPU 15 as a synchronizing signal.

The crystal oscillator circuit 13 starts operating simultaneously with the CR oscillator circuit 12. When the oscillation operation of the crystal oscillation circuit 13 becomes stable, the operation of the CR oscillation circuit 12 becomes
It is stopped based on the control signal CRSTOP from 15 and then the clock signal XT generated by the crystal oscillation circuit 13 is generated.
The OSC will be used by the CPU 15.

The step-down circuit 14 operates based on the clock signal HCLK output from the CPU 15 after the battery is turned on and reduces the power supply voltage VDD from the battery to, for example, 1/2. The step-down voltage Vcc is supplied to the switching circuit 19 and the liquid crystal display drive circuit 16.

The CPU 15 is provided with an S-RAM 15a which is a memory in which data can be rewritten, a ROM 15b which is a read-only memory in which various instructions are stored, and the like. Then, various operations as an electronic notebook, warning operation of battery exhaustion when the power supply voltage drops, and the like are achieved by executing the instructions stored in the ROM 15b.
Further, the CPU 15 outputs the switching signal SW when the power supply voltage drops.

The LSI main body 10 is formed on, for example, an N-type semiconductor substrate, each circuit portion operates in a state where the power supply voltage VDD on the high potential side is grounded, and each circuit except the crystal oscillation circuit 13 Operates with the potential difference between the voltages VDD and VSS as the power supply voltage, and the crystal oscillation circuit 13 operates with the potential difference between the voltage VDD and the output voltage from the switching circuit 19, that is, VCC or VSS as the power supply voltage. .

In the electronic notebook having such a structure, as in the conventional case, the power supply voltage detection circuit 11 detects the decrease of the battery voltage VDD, and the value of VDD is a predetermined value, for example, as in the conventional case.
When the value of DD falls below 2.5V, the detection signal DEF is output. The CPU 15 receives the signal D from the power supply voltage detection circuit 11.
When EF is received, it is determined that the battery voltage has dropped, and the ROM
By executing the command stored in 15b, the user is visually or audibly informed that the battery is dead. For example, predetermined data is sent to the liquid crystal display drive circuit 16, where a display signal is formed and an external liquid crystal display section is formed.
By supplying to 18, the display corresponding to the dead battery is made. Alternatively, the CPU 15 sends a signal to a warning sound generating unit (not shown), and generates a warning sound here. Also,
The CPU 15 prevents the destruction of the memory data by prohibiting the key input capturing operation from the key input unit 17 and the data writing operation to the S-RAM 15a.

When the value of the battery voltage VDD is equal to or higher than the voltage detected by the power supply voltage detection circuit 11, the switching circuit 19 causes the step-down circuit 14 to operate.
The voltage Vcc reduced by is output to the crystal oscillation circuit 13. That is, when the detected voltage in the power supply voltage detection circuit 11 is 2.5 V as in the conventional case, the switching circuit 19 keeps the step-down voltage Vcc from the step-down circuit 14 until the value of VDD falls below 2.5 V. The output is switched and supplied to the crystal oscillation circuit 13.
Here, the step-down circuit 14 reduces the battery voltage VDD to 1 /
If the voltage stepped down to 2 is output as VCC, the crystal oscillator circuit 13 outputs VDD and the step-down voltage from the step-down circuit 14 during the period t4 when the value of the step-down voltage VCC has not reached 1.25V as shown in FIG. It operates by the potential difference between it and Vcc.

On the other hand, when the value of the battery voltage VDD falls below the detection voltage 2.5V in the power supply voltage detection circuit 11 and the detection signal DEF is output from the power supply voltage detection circuit 11, the CPU
Reference numeral 15 performs a switching signal SW output operation in addition to the battery exhaustion warning operation and the memory data destruction prevention operation. When the signal SW is input, the switching circuit 19 switches the step-down voltage VCC from the step-down circuit 14 and outputs the voltage VSS by switching. Therefore, after the value of the battery voltage VDD in the power supply voltage detection circuit 11 becomes lower than the detected value, the crystal oscillation circuit 13 receives the voltage V
Since SS is supplied, the crystal oscillator circuit 13
Operating voltage is the potential difference between VDD and VSS, which is 2.5
Rise to V. For this reason, since it is sufficiently higher than the operation guarantee voltage of 2.2V of the LSI main body 10 including the variation of the detection voltage of the power supply voltage detection circuit 11 mentioned above, the period of the above t4 has elapsed and the value of VDD is 2 Figure 2 until it reaches below 2V
The crystal oscillation circuit 13 can operate stably during the period of t5. Therefore, during this period of t5, the crystal oscillation circuit 13
The stable clock signal HCLK is supplied to the CPU 15 from the above, and the warning operation of the battery exhaustion in the CPU 15 thereafter can be surely performed. In addition, S-RA inside CPU15
Data protection in the M15a and the external memory can be surely performed.

Although not specifically described in the above embodiment, when the crystal oscillation circuit 13 is started up, the stepped down voltage VCC is
Instead, the voltage VSS is supplied to control the operation of the switching circuit 19 so that a sufficiently large potential difference between VDD and VSS is supplied to the crystal oscillation circuit 13, so that the crystal oscillation circuit 13 can be easily started. You may

Next, a detailed configuration of each circuit portion of the circuit of the above embodiment will be described. FIG. 3 shows a detailed configuration of the power supply voltage detection circuit 11. This circuit includes a power supply voltage dividing circuit 21 for dividing the external power supply voltage VDD and an external power supply voltage V
It is composed of a reference voltage generation circuit 22 for generating a constant reference voltage from DD, a voltage comparison circuit 23 for comparing the output voltages of both circuits and generating the signal SW, and the like.

In such a configuration, when the value of the divided voltage in the power supply voltage dividing circuit 21 is larger than the value of the reference voltage, the output signal SW of the voltage comparison circuit 23 becomes "L" level, and the value of the divided voltage is the reference. When the voltage becomes lower than the voltage value, the signal SW is inverted to the “H” level.

FIG. 4 shows a detailed structure of a part of the step-down circuit 14. In this circuit, one P-channel MOS transistor 31 and three N-channel MO transistors 31 in which the source and drain are inserted in series between the voltage VDD and the voltage VSS.
S-transistors 32-34, a capacitor 35 connected between the series connection point of two N-channel MOS transistors 32, 33 and the voltage VSS, a P-channel MOS transistor 31 and an N-channel MOS transistor 32. The capacitor 35 is connected between the series connection point and the series connection point of the two N-channel MOS transistors 33 and 34, and is composed of the capacitor 36 having the same value as that of the capacitor 35.

In the circuit having such a configuration, the MO
As shown in FIG. 5, the gates of the S transistors 31 to 34 are supplied with the two-phase clock signals .phi.1 and .phi.2 and their inverted signals so that the "H" level periods do not overlap each other. A stepped-down voltage VCC corresponding to 1/2 of VDD is output from the series connection point of 33.

The two-phase clock signals φ1 and φ2 are used.
Is a step-down circuit 14 using the clock signal HCLK in FIG.
Formed within. FIG. 6 shows a detailed configuration of the crystal oscillation circuit 13. This circuit is connected between two external terminals 41 and 42 provided on the LSI main body 10 between a crystal oscillator 43 and the external terminals 41 and 42, and has a P channel and N channel MOS. A CMOS inverter 44 composed of a transistor, a feedback resistor 45 connected between the input and output terminals of the inverter 44, and two CMOs for waveform shaping.
It is composed of S-type inverters 46 and 47.

In order to reduce the power consumption in the crystal oscillation circuit 13, the switching output voltage of the switching circuit 19 is applied to the source (not shown) of the N-channel side MOS transistor forming the CMOS type inverter 44. Vcc or Vss is supplied.

FIG. 7 shows a detailed structure of the switching circuit 19. This circuit is composed of an inverter 51 for inverting the switching signal SW, P-channel and N-channel MOS transistors, and is controlled by the output of the switching signal SW and the inverter 51, and is a CMO for switching and outputting the step-down voltage VCC.
An S-transfer gate 52 and an N-channel MO gated by the switching signal SW to switch and output the voltage VSS.
It is composed of an S-transistor 53.

In the circuit having such a configuration, the switching signal SW
Is "L" level, CMOS transfer gate 52
Is turned on, and the voltage Vcc is output as the switching output voltage.
On the other hand, when the switching signal SW is at "H" level, the CMOS transfer gate 52 becomes non-conductive and the N-channel MO
The S-transistor 53 becomes conductive, and the voltage V is output as the switching output voltage.
SS is output.

FIG. 8 shows a detailed structure of the CR oscillation circuit 12. This circuit, as is well known,
Two inverters 61 and 62 connected in series and a two-input NAND gate 63 for controlling oscillation, a resistor 64 for feedback, a capacitor 65 for feedback, and two inverters 66 for waveform shaping,
It consists of 67 and.

The circuit having such a configuration is a NAND gate.
Control signal CRSTOP input to one input terminal of 63
When the control signal CRSTOP is at the "L" level, the oscillation operation is performed to generate the clock signal CROSC, and the oscillation operation is stopped when the control signal CRSTOP is at the "L" level.

FIG. 9 is a block diagram showing the configuration of the second embodiment of the present invention. In the first embodiment shown in FIG. 1, the detection signal DEF of the power supply voltage detection circuit 11 is once changed to CP.
Although the case where the switching signal SW is received under the control of the CPU 15 is received by U15 has been described, in this embodiment, the detection signal DEF of the power supply voltage detection circuit 11 is directly supplied to the switching circuit 13 as the switching signal SW. It was done.

The circuit of this embodiment is the same as that of the first embodiment except for the points described above, and the obtained effect is also the same as that of the first embodiment, and the detailed structure of each circuit section. Is also the same as in the first embodiment.

Needless to say, the present invention is not limited to the above-mentioned embodiments but can be variously modified. For example, in the above-described embodiment, the LSI body 10 is formed on an N-type semiconductor substrate, and each circuit portion operates in a state in which the power supply voltage VDD on the high potential side is grounded.
Each circuit except 13 operates by using the potential difference between this voltage VDD and VSS as the power supply voltage, and the crystal oscillation circuit 13 operates with the above voltage V
The case where the output voltage from the DD and the switching circuit 19, that is, the potential difference between Vcc or Vss is used as the power supply voltage has been described, but when the LSI main body 10 is formed on a P-type semiconductor substrate, The power supply voltage VSS on the low potential side
Operate with the potential difference between the voltage VDD and VSS as the power supply voltage, and the switching circuit 19 switches between the step-down voltage VCC and the voltage VDD for output. The crystal oscillation circuit 13 operates using the potential difference between the voltage VSS and the output voltage from the switching circuit 19, that is, VDD or VCC as the power supply voltage.

[0044]

As described above, according to the present invention,
It is possible to extend the life of the battery by lowering the detected value of the power supply voltage, and it is possible to operate the oscillation circuit reliably even after the detection of the power supply voltage drop. It is possible to provide a semiconductor integrated circuit device capable of preventing the data destruction of.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a waveform diagram of the output voltage of the switching circuit in the first embodiment.

FIG. 3 is a circuit diagram showing a detailed configuration of a power supply voltage detection circuit in the first embodiment.

FIG. 4 is a circuit diagram showing a detailed configuration of a step-down circuit according to the first embodiment.

5 is a waveform diagram of a clock signal used in the step-down circuit of FIG.

FIG. 6 is a circuit diagram showing a detailed configuration of a crystal oscillating circuit in the first embodiment.

FIG. 7 is a circuit diagram showing a detailed configuration of a switching circuit in the first embodiment.

FIG. 8 is a circuit diagram showing a detailed configuration of a CR oscillator circuit in the first embodiment.

FIG. 9 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional circuit.

FIG. 11 is a diagram showing load characteristics of a manganese dioxide / lithium battery.

[Explanation of symbols]

10 ... LSI main body, 11 ... Power supply voltage detection circuit, 12 ... CR oscillation circuit, 13 ... Crystal oscillation circuit (crystal oscillation circuit), 14 ...
Step-down circuit, 15 ... CPU (arithmetic processing unit), 15a ... SR
AM (static RAM), 15b ... ROM, 16 ... Liquid crystal display drive circuit, 17 ... Key input section, 18 ... Liquid crystal display section, 19 ...
Switching circuit.

Claims (5)

[Claims] 1. A step-down circuit for stepping down a high-potential-side voltage of a power source, a voltage detection circuit for detecting that the high-potential-side voltage of the power source has reached a predetermined value, and an output of the step-down circuit having a first input. As the voltage, the low potential side voltage or the high potential side voltage of the power source is supplied as the second input voltage, and either one of the first input voltage and the second input voltage is output according to the detection output of the voltage detection circuit. A power supply voltage switching circuit, an oscillating circuit that operates using a potential difference between a voltage output from the power supply voltage switching circuit and a high-potential-side voltage or a low-potential-side voltage of the power supply as a power supply voltage, and an output signal of the oscillating circuit And a processing circuit that operates in synchronization with the semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the voltage switching operation in the power supply voltage switching circuit is controlled by the detection output of the voltage detection circuit. 3. The semiconductor integrated device according to claim 1, wherein a voltage switching operation in the power supply voltage switching circuit is controlled by an output signal of the arithmetic processing circuit which receives a detection output of the voltage detection circuit. Circuit device. 4. A step-down circuit for stepping down the high-potential-side voltage of the power source, a voltage detection circuit for detecting that the high-potential-side voltage of the power source has reached a predetermined value, and the output of the step-down circuit is a first input. As the voltage, the low potential side voltage or the high potential side voltage of the power source is supplied as the second input voltage, and either one of the first input voltage and the second input voltage is output according to the detection output of the voltage detection circuit. A power supply voltage switching circuit; and an oscillating circuit that operates using a potential difference between a voltage output from the power supply voltage switching circuit and a high-potential-side voltage or a low-potential-side voltage of the power supply as a power supply voltage. Integrated circuit device. 5. A battery power source, a step-down circuit for stepping down the high-potential side voltage of the power source, a voltage detection circuit for detecting that the high-potential side voltage of the power source has reached a predetermined value, and an output of the step-down circuit. Is supplied as the first input voltage, the low-potential-side voltage or the high-potential-side voltage of the power supply as the second input voltage, and either the first or second input voltage is supplied depending on the detection output of the voltage detection circuit. A power supply voltage switching circuit that outputs one of the two; and an oscillation circuit that operates using the potential difference between the voltage output from the power supply voltage switching circuit and the high-potential-side voltage or the low-potential-side voltage of the power supply as the power-supply voltage. A semiconductor integrated circuit device characterized by the above.