JPH0766332A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0766332A
JPH0766332A JP5210694A JP21069493A JPH0766332A JP H0766332 A JPH0766332 A JP H0766332A JP 5210694 A JP5210694 A JP 5210694A JP 21069493 A JP21069493 A JP 21069493A JP H0766332 A JPH0766332 A JP H0766332A
Authority
JP
Japan
Prior art keywords
chip
semiconductor device
metal
metal member
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5210694A
Other languages
Japanese (ja)
Inventor
Yuugo Koyama
裕吾 小山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP5210694A priority Critical patent/JPH0766332A/en
Publication of JPH0766332A publication Critical patent/JPH0766332A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】 【構成】半導体チップ5と半導体装置のICチップの周
囲に配されたインナーリード3と、半導体チップ5とイ
ンナーリード3とをワイヤ2によりボンディングしてい
る、樹脂封止された半導体装置において、保護膜で覆わ
れたICチップ上に複数の金属性突起部(金属バンプ)
8が設けられそれぞれに金属部材(金属棒)6が載置さ
れていることを特徴とする半導体装置。また、前記金属
部材がパッケージ表面から外部へ露出している。金属部
材と金属性突起部とが非導電性の接着剤等で固定されて
いる。金属部材と金属性突起部とが、ダイパッド裏面に
も載置されていること等を特徴とする。 【効果】ICチップ5上で発生した熱が保護膜上に載置
された金属バンプ8上に延びた金属棒6を伝導して外部
へ放出され、従来PKGでは達成されなかった高放熱性
を具備させることができる。
(57) [Summary] [Structure] Inner leads 3 arranged around the semiconductor chip 5 and the IC chip of the semiconductor device, and the semiconductor chip 5 and the inner leads 3 are bonded by the wires 2, which are resin-sealed. In a semiconductor device, a plurality of metallic protrusions (metal bumps) are formed on an IC chip covered with a protective film.
8. A semiconductor device, wherein: 8 are provided, and a metal member (metal rod) 6 is placed on each. Further, the metal member is exposed to the outside from the package surface. The metal member and the metallic projection are fixed with a non-conductive adhesive or the like. It is characterized in that the metal member and the metallic projection are also placed on the back surface of the die pad. [Effect] The heat generated on the IC chip 5 is conducted to the outside through the metal rods 6 extending on the metal bumps 8 mounted on the protective film, and a high heat dissipation property which is not achieved by the conventional PKG is provided. It can be provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【産業上の利用分野】本発明はICパッケージの構造に
関する。
FIELD OF THE INVENTION The present invention relates to the structure of IC packages.

【従来の技術】従来の半導体装置は図2に示すように表
面に保護膜7が載置されたICチップ5がリードフレー
ムのダイパッド部4上に載置され、ICチップ上からイ
ンナーリード3へ導電性細線2を用いて接続されたもの
が樹脂1で覆われている構造を取っていた。
2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 2, an IC chip 5 having a protective film 7 mounted on its surface is mounted on a die pad portion 4 of a lead frame, and from the IC chip to the inner leads 3. The structure is such that those connected by using the conductive thin wire 2 are covered with the resin 1.

【発明が解決しようとする課題】電流Iが固有抵抗Rを
持つ配線上を流れるとそこにジュール熱Qが発生し、Q
=RI2(J)で与えられる熱量が発生する。近年、I
Cチップは製造工程でのサブミクロン加工技術の進歩に
よりその集積度が増し、またその処理スピードが非常に
速いものになっている。ICチップの集積度が増し且つ
処理スピードも増せばその分単位時間当たりのIC単位
表面積上を通過する電流量が増加するから、上記で説明
したジュール熱Q=RI2の電流Iが△I増加すれば発
熱量Qも△Q=R△I2増加する。ICチップのpn接
合部で発生した熱量△Qが寄与する接合部温度上昇△T
により接合部温度Tがその定格を越えると、リーク電流
の増大、長期信頼性の低下、等を引き起こす。また、I
Cチップ並びに封止樹脂等の膨張に伴い、それぞれ異な
った熱膨張率を有するパッケージ内部の各要素は、半田
による基盤接合の際の熱履歴の際の冷却時に収縮し、そ
の熱膨張率の差から各要素間に間隙が発生し、外部から
水分等異物が侵入する。この状態でパッケージに熱をか
ければ内部に侵入した水分等の異物が膨張してパッケー
ジを破壊してしまう、という問題が生じる。
When the current I flows on the wiring having the specific resistance R, Joule heat Q is generated there and Q
= The amount of heat given by RI 2 (J) is generated. In recent years, I
The progress of the submicron processing technology in the manufacturing process has increased the degree of integration of the C chip, and its processing speed has become extremely fast. As the integration degree of the IC chip increases and the processing speed increases, the amount of current passing over the IC unit surface area per unit time increases accordingly, so that the current I of Joule heat Q = RI 2 explained above increases by ΔI. Then, the heat generation amount Q also increases by ΔQ = RΔI 2 . Increase in junction temperature ΔT contributed by the amount of heat ΔQ generated at the pn junction of the IC chip
As a result, if the junction temperature T exceeds the rating, leakage current increases, long-term reliability deteriorates, and the like. Also, I
With the expansion of the C chip and the sealing resin, each element inside the package having a different coefficient of thermal expansion contracts at the time of cooling during the heat history at the time of base joining by solder, and the difference in the coefficient of thermal expansion. Therefore, a gap is generated between each element, and foreign matter such as water enters from the outside. If heat is applied to the package in this state, foreign matter such as moisture that has penetrated into the package will expand and destroy the package.

【課題を解決するための手段】上記課題を解決するため
本発明の半導体装置は、保護膜で覆われたICチップ表
面に複数の金属性突起部が設けられそれぞれに金属部材
が載置されていることを特徴とする。
In order to solve the above-mentioned problems, a semiconductor device of the present invention has a plurality of metallic projections provided on the surface of an IC chip covered with a protective film, and a metallic member is placed on each of the metallic projections. It is characterized by being

【実施例】図1は本発明の実施例を説明した要部の図で
ある。リードフレームのダイパッド4上に載置されたI
Cチップ5上の出力パッドから金属性の細線2がリード
フレームのインナーリード3に接続されその周りを非導
電性の樹脂材(モールド材)1で覆っている。チップ表
面は配線保護のための保護膜(例えばポリイミド膜)7
で覆われており、その上面に金属部材8、例えば銅材質
のもの、がメッキ或いは蒸着などで載置されており、そ
の上面には金属性棒6、例えば銅材質のもの、が載置さ
れている。熱の流れを考えれば、ICチップで発生した
熱量は封止樹脂あるいはICチップ上に載置された金属
部材、金属性棒に移動し、そこに停留するか外気に移動
するかするが、金属性棒の方が封止樹脂よりも熱伝導率
が良いため、金属性棒へ移動する熱量の方が多くなり、
IC自体またはPKG自体に熱を拘留させにくくなる。
そのためpn接合部での接合部温度を定格以下に抑え込
む事が可能になるため、ICの誤動作を防ぐ事ができ
る。又パッケージまたはパッケージ構成各要素に熱膨張
或いは冷却による収縮が起きにくくなるため、各要素間
に発生すると考えられる間隙が発生しにくくなり異物の
侵入の危険性が少なくなる。図3にこの方式で構成した
パッケージの上方向からみた平面図を示す。モールド樹
脂1で覆われたリードフレーム3で外部回路とICチッ
プが接続されモールド樹脂表面には放熱用の金属性棒が
頭を覗かせている。さらに放熱効果を高めるためには図
4のようにICチップ5上に保護膜7を介して載置され
た金属部材8上にある金属性棒6が封止樹脂1表面より
突き出ておりその突き出た部分に金属片9、例えば銅材
質のもの、をポリイミドテープ等で接着する。金属片は
その外気との接触面積が大きければ大きいほど放熱効果
は上がるため、なるべく大きな面積を持つ金属片が望ま
しい。また図5のように金属片9表面に凹凸を持たせれ
ば凹凸分だけの高さ方向の表面積が増加する。この放熱
用の金属棒6はチップ表面側に載置するだけでなく、図
6のようにチップ裏面側のダイパッド4の裏面にも金属
部材8を設け、そこから金属棒6をPKG外部にまで延
長させ露出させることで片側よりも大きな放熱効果が達
成される。またこのような構造をとる事でモールド時に
発生するダイパッドのパッケージ構造に対する上下方向
の絶対位置を固定させる事が出来る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram of a main part for explaining an embodiment of the present invention. I placed on the die pad 4 of the lead frame
A thin metal wire 2 is connected to the inner lead 3 of the lead frame from the output pad on the C chip 5 and is surrounded by a non-conductive resin material (mold material) 1. The chip surface is a protective film (for example, a polyimide film) 7 for wiring protection.
And a metal member 8, for example, made of copper, is placed on the upper surface by plating or vapor deposition, and a metal rod 6, for example, made of copper is placed on the upper surface. ing. Considering the flow of heat, the amount of heat generated in the IC chip moves to the sealing resin or the metal member or metal rod mounted on the IC chip, and either stays there or moves to the outside air. Since the heat conductivity of the flexible rod is better than that of the sealing resin, the amount of heat transferred to the metal rod increases,
It becomes difficult to confine heat to the IC itself or the PKG itself.
Therefore, the junction temperature at the pn junction can be suppressed below the rated value, and malfunction of the IC can be prevented. Further, thermal expansion or contraction due to cooling is less likely to occur in the package or each element constituting the package, so that a gap that is considered to occur between the elements is less likely to occur and the risk of foreign matter entering is reduced. FIG. 3 shows a plan view of the package configured by this method as seen from above. An external circuit is connected to an IC chip by a lead frame 3 covered with a mold resin 1, and a metal rod for heat dissipation is looking through the mold resin surface. In order to further enhance the heat dissipation effect, as shown in FIG. 4, the metallic rod 6 on the metal member 8 placed on the IC chip 5 via the protective film 7 protrudes from the surface of the sealing resin 1 and the protrusion thereof. A metal piece 9, for example, made of a copper material is adhered to the open portion with a polyimide tape or the like. The larger the contact area of the metal piece with the outside air, the higher the heat dissipation effect. Therefore, the metal piece having the largest possible area is desirable. If the surface of the metal piece 9 is provided with irregularities as shown in FIG. 5, the surface area in the height direction corresponding to the irregularities increases. This metal rod 6 for heat dissipation is not only placed on the front surface side of the chip, but also a metal member 8 is provided on the back surface of the die pad 4 on the back surface side of the chip as shown in FIG. By extending and exposing it, a greater heat dissipation effect than on one side is achieved. Further, by adopting such a structure, it is possible to fix the absolute position of the die pad, which occurs at the time of molding, in the vertical direction with respect to the package structure.

【発明の効果】本発明の半導体装置を用いることによ
り、従来のパッケージ構造では達成できなかった高放熱
性をパッケージに備えさせることができるため、半導体
装置の信頼性を向上させる事ができ、またモールド時の
ダイパッドの上下方向の移動も抑える事ができる。
By using the semiconductor device of the present invention, it is possible to provide the package with a high heat radiation property which cannot be achieved by the conventional package structure, and therefore the reliability of the semiconductor device can be improved, and The vertical movement of the die pad during molding can also be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明した要部の断面図。FIG. 1 is a sectional view of an essential part for explaining an embodiment of the present invention.

【図2】従来のパッケージ断面図。FIG. 2 is a sectional view of a conventional package.

【図3】本発明のパッケージを上部から見た図。FIG. 3 is a view of the package of the present invention seen from above.

【図4】本発明のパッケージに放熱板を付随させた図。FIG. 4 is a diagram in which a heat sink is attached to the package of the present invention.

【図5】本発明のパッケージに凹凸を持つ放熱板を付随
させた図。
FIG. 5 is a diagram showing a package of the present invention with a heat sink having irregularities attached thereto.

【図6】本発明のパッケージの上下に放熱用の金属性棒
を載置した図。
FIG. 6 is a view in which a metal rod for heat dissipation is placed on the top and bottom of the package of the present invention.

【符号の説明】[Explanation of symbols]

1 樹脂 2 金属細線 3 インナーリード 4 ダイパッド 5 ICチップ 6 金属性棒 7 保護膜 8 金属性突起部 9 金属片 1 Resin 2 Metal Fine Wire 3 Inner Lead 4 Die Pad 5 IC Chip 6 Metal Rod 7 Protective Film 8 Metal Projection 9 Metal Piece

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ICチップとその周囲に配されたインナ
ーリードと、半導体チップとインナーリードとを結線し
ている導電性細線とを樹脂封止している半導体装置にお
いて、保護膜で覆われたICチップ上に複数の金属性突
起部が設けられそれぞれに金属部材を載置していること
を特徴とする半導体装置。
1. A semiconductor device in which an IC chip, an inner lead arranged around the IC chip, and a conductive thin wire connecting the semiconductor chip and the inner lead are resin-sealed, and covered with a protective film. A semiconductor device, wherein a plurality of metallic projections are provided on an IC chip and a metal member is mounted on each of them.
【請求項2】 請求項1記載の金属部材がパッケージ表
面から外部へ露出している事を特徴とする半導体装置。
2. A semiconductor device, wherein the metal member according to claim 1 is exposed from the package surface to the outside.
【請求項3】 請求項1記載の金属部材と金属性突起部
とが非導電性の接着剤等で固定されている事を特徴とす
る半導体装置。
3. A semiconductor device, wherein the metal member according to claim 1 and the metallic projection are fixed by a non-conductive adhesive or the like.
【請求項4】 請求項1記載の金属部材と金属性突起部
とが、ダイパッド裏面にも載置されていることを特徴と
する半導体装置。
4. A semiconductor device, wherein the metal member and the metallic projection of claim 1 are also mounted on the back surface of the die pad.
JP5210694A 1993-08-25 1993-08-25 Semiconductor device Pending JPH0766332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5210694A JPH0766332A (en) 1993-08-25 1993-08-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5210694A JPH0766332A (en) 1993-08-25 1993-08-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0766332A true JPH0766332A (en) 1995-03-10

Family

ID=16593559

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5210694A Pending JPH0766332A (en) 1993-08-25 1993-08-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0766332A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100386870C (en) * 2003-08-06 2008-05-07 罗姆股份有限公司 Semiconductor device
WO2012019173A1 (en) * 2010-08-06 2012-02-09 Conexant Systems, Inc. Systems and methods for heat dissipation using thermal conduits
EP1729341A3 (en) * 2005-06-01 2014-03-26 TDK Corporation Semiconductor IC and its manufacturing method, and module with embedded semiconductor IC and its manufacturing method
KR20190136852A (en) * 2018-05-31 2019-12-10 한국전력공사 Corugated pipe for underground cable
CN112074934A (en) * 2018-06-14 2020-12-11 德州仪器公司 Stress buffer layer in embedded package
US20230093341A1 (en) * 2021-09-22 2023-03-23 Infineon Technologies Austria Ag Semiconductor Package Comprising a Cavity with Exposed Contacts and a Semiconductor Module
EP4283665A4 (en) * 2021-01-19 2024-07-24 Beji Sasaki ELECTRONIC DEVICE AND PRODUCT
US12621961B2 (en) 2021-01-19 2026-05-05 Beji Sasaki Electronic device and product

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100386870C (en) * 2003-08-06 2008-05-07 罗姆股份有限公司 Semiconductor device
EP1729341A3 (en) * 2005-06-01 2014-03-26 TDK Corporation Semiconductor IC and its manufacturing method, and module with embedded semiconductor IC and its manufacturing method
WO2012019173A1 (en) * 2010-08-06 2012-02-09 Conexant Systems, Inc. Systems and methods for heat dissipation using thermal conduits
US20120032350A1 (en) * 2010-08-06 2012-02-09 Conexant Systems, Inc. Systems and Methods for Heat Dissipation Using Thermal Conduits
KR20190136852A (en) * 2018-05-31 2019-12-10 한국전력공사 Corugated pipe for underground cable
CN112074934A (en) * 2018-06-14 2020-12-11 德州仪器公司 Stress buffer layer in embedded package
CN112074934B (en) * 2018-06-14 2025-03-07 德州仪器公司 Stress buffers in embedded packages
EP4283665A4 (en) * 2021-01-19 2024-07-24 Beji Sasaki ELECTRONIC DEVICE AND PRODUCT
US12621961B2 (en) 2021-01-19 2026-05-05 Beji Sasaki Electronic device and product
US20230093341A1 (en) * 2021-09-22 2023-03-23 Infineon Technologies Austria Ag Semiconductor Package Comprising a Cavity with Exposed Contacts and a Semiconductor Module
US12506051B2 (en) * 2021-09-22 2025-12-23 Infineon Technologies Austria Ag Semiconductor package comprising a cavity with exposed contacts and a semiconductor module

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