JPH0767191A - Exchange interface system and communication method of synchronous digital data communication network - Google Patents

Abstract

PURPOSE: To perform full duplex synchronous communication between two arbitrary terminal stations of a network through a pair of wire connections without requiring any additional connection for a clock pulse or a phase-locked pulse. CONSTITUTION: The transmission of synchronous digital data to a network terminating device 50B of a slave from a master control unit 50A is wholly performed through a pulse width-modulated data flow containing a pulse width- modulated binary pulse having a pulse width-modulated synchronized pulse having prescribed leading transition at the same point in each cycle of a master clock signal. The terminating device 50B draws out clock signals from the received pulse width-modulated binary data flow, decodes the clock signal and synchronously transmits the clock signals from the slave and the terminating device 50B to the master control unit 50A in a non-self clocking way. Phase synchronization is maintained between the transmission and reception of the control unit by using a phase synchronized pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a switching system for controlling communication between transmitting and receiving information sources of a telecommunications network, and more particularly to timing synchronization information directly encoded into transmitted and received digital information. Regarding such a method.

[0002]

2. Description of the Prior Art In modern digital telephone switching systems, audio signals between individual subscriber units are PCM coded and transmitted and received on a time division multiplexed basis. A circuit known as a network terminator interfaces with a group of analog or digital telephone lines to connect these lines to a corresponding group of channels in a time division multiplexing scheme, namely time slots,
It has a means for segmenting. Voice information or digital data on any incoming telephone line in the telephone line group is assigned to other transmitting / receiving units in the system during the corresponding time slot in the group of time slots and continuously exchanges it. Is done. The data in the multiple time slots is then provided to a control unit that exchanges information from any incoming channel to the selected outgoing channel. These control units include a central processing element that controls this switching operation and provides a central time base for synchronizing the switching operations.

Therefore, it will be appreciated that some other type of information must be transmitted between each control unit and its associated network terminator. In order to maintain frequency synchronization between the network terminator and the central time base of the control unit, the clock reference from the central time base must be transmitted from the control unit to the network terminator. In order to maintain phase synchronization between the network terminator and the control unit central time base, a phase reference must be passed from the control unit to the network terminator. Of course, there must also be a voice or data path from the network terminator to the control unit and vice versa. A control data link is also provided between the network terminating device and the control unit in order to control its operation through a message to the network terminating device and on the other hand to pass a message from the network terminating device to the control unit in response to a command from the control unit. There must be.

When using independent wires for the above-mentioned various data, six different wires are required for each pair of the control unit and the network terminating device. In the large switching system, the total number of wires and connections is excessive even if there are 24 channels per network termination device. This fact becomes even more critical as the size of the individual control units and network terminators is reduced by the miniaturization of the circuits, thereby reducing the space available for the wire connectors of these units. Therefore, there is a strong need to minimize the number of wire connections between the control unit and the network terminator pair.

Of course, it is generally known to reduce the number of wires required to transmit heterogeneous information by time division multiplexing. Referring to FIG. 1A, a data coding method generally called Manchester coding and a bi-phase unipolar coding method are also known, in which synchronized information is uniquely carried by transmitted data, that is, self-clocking. Thus, one wire can carry data and clock information at the same time. Binary 1s and 0s are represented by negative and positive transitions, which occur only once in each cycle, but it is not clear whether the transition is positive or negative, so a full clock extraction is performed. It is necessary to detect both types of transitions. Moreover, the transition occurs in the middle of the clock period rather than at the beginning of each cycle. RZ
Another method known as (return to zero) binary bipolar coding is self-clocking. However, the binary 1's and 0's are represented by positive and negative voltage pulses at the beginning of each cycle, which is inconsistent with modern telephone switching circuits and thus has the disadvantage of requiring a bipolar voltage source. The scheme known as RZ binary unipolar coding does not require a bipolar voltage source, but is only partially self-clocking because no pulses occur during each clock cycle. Clock detection for such an RZ data source is assigned to the assignee of the present invention by Torglin in US Pat. No. 3,894, Jul. 8, 1973.
No. 246. No other encoding method using pulse formats, which is self-clocking or phase-synchronized, is known, so any known unipolar data line must be accompanied by a companion synchronization line.

[0006]

Accordingly, it is an object of the present invention to provide a synchronization, digital communication device and method using digital pulse width modulation coding that overcomes the disadvantages of using the known self-clocking coding. Is the purpose of.
A non-self-clocking binary signal is pulse-width coded to produce a predetermined sense (preferably positive or negative) transition and a fully self-clocking unipolar data stream is generated at the beginning of each clock cycle. A pulse width modulated pulse is generated at. In the most basic application, a binary one corresponds to a pulse having a width of one and a binary zero corresponds to a positive pulse of another width. In order to perform not only timing synchronization but also phase synchronization, a third pulse having a width different from the width of binary 1 and binary 0 once in each byte or twice in another block of data is phased. It is generated as a synchronization pulse.

Using the coding method of the present invention for data and clock pulses, there is a pair of wire connections between any two end stations of the network without the need for additional connections for clock pulses and phase synchronization pulses. An advantageous communication method of a synchronous digital communication network capable of performing full-duplex and synchronous communication is provided. According to the method, a series of non-self-clocking digital pulses from one end station are binary 1, binary 0 and phase lock pulses each of variable width before being transmitted to the other end station. Converted to the self-clocking format represented. At the other terminal, a clock signal is extracted from the positive transition of the pulse occurring at the beginning of each clock cycle, which then extracts the pulse width modulated data pulse into a non-self clocking form. Used to return. The synchronization pulse is used to maintain phase synchronization between the stations.

The object of the invention is achieved in part by applying the method to a switching system for controlling inter-source communication in a telecommunication network of transmitting and receiving information sources. According to one aspect of the invention, the switching scheme comprises a control unit connected to some sources and a network terminator connected to other sources. The control unit includes means for encoding information from the source in a serial, pulse width binary format and means for serially transmitting pulse width binary encoded pulses of the encoded information at a predetermined transmission bit rate. There is. A network terminator is responsive to the serially transmitted pulse width binary coded pulse for extracting a clock signal therefrom and synchronously decoding the serially transmitted pulse width binary coded pulse in response to the clock signal. It includes means for sending to said other source to which the network terminator is connected.

According to another aspect of the present invention, a network terminator provides means for encoding data from an information source connected thereto into a pulse format and frequency-synchronizing the encoded data with the transmission bit rate in response to a clock signal. It also has a means for transmitting to the control unit.

It is also an object of the present invention to provide a switching scheme that allows both timing and phase synchronization using synchronization pulses. In this method, the control unit comprises means for encoding the information from said source as a series of data pulses, means for generating pulse width coded synchronization pulses, and said series of data pulses and pulse width coded. Means for transmitting the synchronizing pulses together at a predetermined bit rate on a time division multiplexed basis. The network terminator is means for deriving a clock signal in response to at least the pulse width coded synchronizing pulse; And a means for controlling the synchronization between the synchronous decoding means of the network terminator and the coding means of the control unit in response to said pulse width coded synchronizing pulse. .

[0011]

Preferably, the network terminator comprises means for transmitting data from the other source connected thereto to the control unit. It includes means for maintaining phase synchronization of the data transmitted to the control unit in response to the synchronization pulse and the pulse width coded synchronization pulse from the control unit. A phase synchronization acquisition circuit is provided, which is associated with the decoding means, for generating a synchronization pulse reception signal in response to receiving the synchronization pulse from a control unit; and the synchronization pulse reception signal. In response to the counter of the encoding means for counting clock pulses in phase with the synchronizing pulse, and in response to the counter when the counter is in phase with the synchronizing pulse and when the next synchronization Means for generating a synchronization control signal indicating whether a control pulse should be received, and an out-of-sync signal in response to the synchronization pulse reception signal and the synchronization control signal which are not generated within a predetermined period of each other Including means. Means are provided for resynchronizing the counter in response to the out of sync signal.

[0012] Preferably, full-duplex synchronous communication is performed between the control unit and the network terminating device. It comprises means for encoding information from a series of data pulses, means for decoding the information received in the series of data pulses, means for generating a synchronization pulse of a predetermined width different from the width of the data pulse, and This is accomplished by providing the control unit with means for transmitting the coded information and the synchronization pulse together at a predetermined bit rate. Similarly, the network terminator at least means for deriving a clock signal in response to the synchronization pulse and for synchronously encoding information from one of the other sources in response to the clock signal to the control unit. Means for transmitting and means for controlling the encoding of the network terminator and the phase synchronization of the transmitting means and the decoding means of the control unit in response to the synchronization pulse.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings, and in particular to FIGS. 1B and 2, the ternary coding scheme which enables many of the advantageous features of the present invention uses three pulses of different widths. Preferably, the logic 0 pulse 20 has the narrowest width, the logic 1 pulse 22 has approximately twice the width of the logic 0 pulse 20, and synchronization, ie, sync, pulse 24 is the logic 0 pulse 2.
It has the widest width of about 3 times 0. Preferably, the total clock period 26 is four times the width of the logic zero pulse so that no logic one pulse remains in at least one-quarter of the clock period even if the sync pulse 24 occurs. Unlike the method shown in FIG. 1A, the pulses 20, 22
Alternatively, the leading edge of 24 coincides with the beginning of each timing period and the time between the leading edges of successive pulses is always 26 clock periods.
be equivalent to. In addition, a code pulse is generated for each clock pulse.

Referring now to FIG. 3, the present invention is used to interface with various elements of network subsystem 29, network subsystem 2
9 is then connected to the SBX bus 30 of the control subsystem and the elements of the network termination subsystem. Communication between the subsystem elements and the central controller and central memory (not shown) of the telephone switching system occurs over the SBX bus 30. Preferably, the control subsystem of bus 30 is simplex or duplex 68020/6803.
It is a 0 microprocessor-based multiprocessor, distributed processing system. The network subsystem 29 has a system clock, CK, 32 and each is a single stage,
Non-blocking, 772 channel timeslot interchanger, ie 4 interactive switching / control modes consisting of TSI 34 (only 2 shown)
It consists of Most of these channels 768 are divided into 32 groups of 24 channels that interface with the transition circuits of the network termination subsystem 27 via a constrained serial interface known as a network link. TSI3
A network self-controller, i.e., NSC circuit 36, connected to 4 provides 2 Mbytes of DRAM 68000, which provides the ability to handle signal activity on 768 channels in each switch mode.
It has a microprocessor. Within the NSC circuit 36, 768 channels parallel time division multiplexing for TSI circuits (not shown), ie TDM, 32 channels for network termination subsystem 27, 24 channels 3.088 MH.
z serial link, or network link. The TSI circuit 34 provides access to high level processing for itself and the NSC circuit 36 provides access to the SBX circuit resident on the control subsystem secondary bus 30 via an SBX interface (not shown). . The central controller memory and central controller are loaded via this secondary bus 30.

The circuitry forming the network termination subsystem 27 is a DA that provides tone, announcements and messages.
S, ie digital audio source 37, basic rate line, ie BRL, circuit 38, primary rate interface circuit, ie PRI 40, one or more DS
I port circuit 42 and digital signal processing, namely D
It includes an SP and a circuit 44. The BRL circuit 38 provides system access to the agent and supervisor consoles, and the PRI circuit 40 terminates the 24 64K bit channels of the TI digital trunk and has all the features of the DSI port circuit 42. DSI port circuitry 42 provides digital TI trunk access to the system. The PCM channel is appropriately formatted and sent to the DS1 transmission link 46. DS1 Link 46
Input information from is recovered, buffered and sent to the network link for access to the network. The digital signal processing circuit 44 includes three separate TMs for accessing 8 out of the 24 system channels that the DSP circuit 44 accesses to the network via its link.
An S320C25 digital signal processor circuit is provided. The DSP44 processor receives functions for MF and DTMF signals and can be used for tone measurement functions in system diagnostics. Each element of the network termination subsystem 27 is connected to the differential NS by the link 47 of only four lines.
It can be seen that it is advantageously connected to C36, and in the non-differential system only two wires are connected.

Wire link 47 is enabled by the network link interface of FIG. 8, ie, NLI, integrated circuit 50. As shown in FIG. 9, each network termination subsystem element 37, 38, 40, 42, 44 includes one or more NLI circuits 50 that act as network terminator 50B and act as control unit 50A. A number of NLI circuits are included in NSC circuit 36 of subsystem 29. Therefore, preferably, the present invention is one NLI that can operate in different modes depending on the application, as described below.
Implemented by circuit 50. Although it is possible to provide a separate integrated circuit package for each different mode of operation instead of one package, preferably the NLI circuit is
It is implemented in a large scale integrated circuit package having the input / output terminals shown in the figure.

For convenience of explanation, referring to FIG. 4A, the network link interface circuit 50 is a DS1 port circuit 4.
Another network link interface circuit which operates one of 2, 2 and 8 as a control unit, 9th
It is shown as a network terminator, slave, circuit 50B that interfaces with a master unit 50A.

The DPC 42 terminates one DS1 trunk and interfaces its 24 channels to the network. The DPC 42 not only monitors the performance of the DS1 line, but also recovers the received DS1 clock, controls the frame, and buffers the received PCM and AB (CD) signal data. Via the elastic buffer 53, the received PCM of the DS1 line and the signal data received on the DS1 line 46 are synchronized with the system clock generated on the line 51A. The data read from the elastic buffer 53 is transmitted to the network via the network link 47.
The information sent to the outgoing DS1 line 46 is also the network link 4
Received from the network via 7. The microprocessor monitors the bit error rate and slip performance of the DS1 line, monitors alarm conditions, controls loopbacks and other diagnostic facilities, and maintains communication with the control system via the data link within the network link 47. To do.

Office repeater rack (ORB), channel service unit (CSU), or galaxy (g)
A DS1 signal received from an audio voice circuit (GVC) port interface device is transformer coupled and terminated at DPC 42 as shown. Similarly,
Each transmitted DS1 signal is transformer coupled to the line. Three
Each VLSI device is the core of the DS1 interface function of the DPC 50B, that is, the line interface device 51, the DS1 transceiver 52, and the elastic buffer 53.
To form. These three VLSI devices are programmable by the DPC microprocessor 54.

In addition to the programmable line built-out function, the DPC line interface device 51 has a DS1
Proper termination of the line interface 46 and line driver circuitry are provided. Line interface device 51 also recovers the clock signal on receive line 46A and provides this clock and 1.544 MHz serial data to DS1 transceiver 52 via lines 51A and 51B, respectively. Similarly, the line interface device 51 uses the line 5
DS1 transceiver 52 to 1.544M via 2A
The Hz serial data is received and sent to the outgoing DS1 line 46. The DS1 line clock extracted and received by the line interface device 51 can also be output from the DPC 42 and communicated as a reference input to a clock control circuit of the network (not shown).

The DS1 transceiver 52 locks on to the framing pattern of the receiving DS1 line 46A and performs PCM.
And each channel of signal data to the elastic buffer 53 device. The received DS1 line bit error counts and alarm conditions are maintained by the DS1 transceiver 52.
Similarly, a PCM sent via outgoing DS1 line 46B
And signaling data is provided from NLI 50B to DS1 transceiver 52 for framing.

Elastic buffer 53 buffers the received PCM and signal information for each channel to allow for variations between the DS1 line and the system clock. This data is read from the buffer by the NLI 50B in synchronization with the system clock. Preferably, the elastic buffer device 5
3 is programmed to perform signal integration and freeze functions, if desired.

NSC 36 encodes the system clock and synchronization signals onto network link 47, which are N signals.
It is decoded by the LI50B and the accompanying phase synchronization circuit. NLI50B is 24 channels of PCM and DPC4
It provides a mechanism for connecting the two signal data to the network. The NLI 50B also enables the microprocessor 54 to NSC over the 768 Kbps data link of the network link 47.
A means for communicating with 36 microprocessors is provided.
In the redundancy scheme, NLI 50B is connected to NSC 36 in each network copy.

DPC 40 operates at 6 MHz 6800
It includes a 68008 microprocessor 54 which is an 8 IC. The main function of the microprocessor 54 is NLI5
Program the 0B DS1 interface circuit to D
Monitor the S1 line 40 and detect error and alarm status
Report to C36. Microprocessor 54
Interacts with NLI 50B to communicate with NSC 36. In such cases, the DS1 transceiver 52
Controls facility data link 51A in DS1 applications. Also, for remote agent applications, N
LI 50B controls the data link to remote facility 57B maintained on one of the 64 kbps channels of DPC 42.

The DPC 42 contains 64 Kbytes of non-standby EPROM 55 for bootloading and diagnostic code. DPC42 is optional 96K
It contains 32K bytes of non-standby RAM 56 that can be expanded to bytes. The RAM 56 can be write protected with an 8K byte block. Several registers are also provided in the address space of microprocessor 54 to control and monitor various functions.

The microprocessor 54 is an NLI 50B,
DS1 transceiver 52, line interface device 5
1. N interrupts from the serial communication controller 57
It can be received by the 10 mS signal occurring in the LI50B.

To provide remote agent capabilities, the DPC 42 has a DS1 for facilitating'D 'channel control in an ISDN'23B + D' environment.
Access to one of the 24 64 Kpps channels on line 46 is provided. The received 64 Kbps data is D
Z1 via SLI transceiver 52 via NLI 50B
530 serial communication device or data link 57A and 57B controlled by microprocessor 54. The device 57 serializes the 64 Kbps data stream and sends it out to the DS1 transceiver 52 via the NLI 50B and out to the DS1 line 46B. At the remote location there is another DPC 42 as the source and sink for this'D 'channel information.

The DPC contains a redundant -48VDC input and includes a DC / DC power converter to derive the + 5V required for its logic.

Next, referring to FIG. 4B, the NLI 50
A is an NSC 36 that interfaces the network subsystem 29 with the elements of the network termination subsystem of FIG.
Master inside, ie control unit, 50A
It turns out that it is used as. NSC36 is a switching network 3
It occupies a mid-level position in the layer distribution processing architecture. The primary role of the NSC 36 is call processing, during which it interfaces with the higher order microprocessors of the controller system via SBX interface means shared with the associated TSI 34. The NSC 36 also uses the DAS in the network termination subsystem 27 via the network link means.
37 and DSP 44. The AB (CD) signaling bits on lines and trunks and the special B signaling messages (special B signaling) on fine line consoles are controlled directly by NSC microprocessor 58. 'ABSB IC' to facilitate NSC control of this signaling information
An ASIC is being developed. NLI50A is developed for communication between a network and a network terminating element.
SIC. NSC 36 contains 32 NLI 50A.

NSC operates at 10 MHz 68000
It is controlled by the microprocessor 58. NSC36
64 Kbps of EPROM 59 accessible in one standby for bootloading and diagnostic code
Is included. This circuit is also configured as a 1M × 16 2M DRAM 60M accessible in a non-standby state.
It also includes bps. Parity is also maintained on byte boundaries for the entire DRAM 60. Software can be downloaded to this DRAM 60 and executed. The protection logic 61 allows the 8K byte segment of DRAM 60 to be write protected and designated to be opcode fetched, designated as supervisor or user space. Attempting to violate the specified protection for a given DRAM segment will result in a bus error indication to the microprocessor 58.

N containing four 8-bit counters that can be configured to provide two 16-bit counters.
The 68901 multifunction peripheral 62 can be utilized on the SC. The serial port 62A on the peripheral facilitates an off-card communication link. This serial link is used by the NSC in the control / network channel for communication with the clock of another channel. This serial link is used to download the clock during system initialization as a means of intercommunication with a control system microprocessor (not shown). The I / O pins of the microprocessor 58 are used as priority interrupt inputs and as a latch for error indications coming from the memory protection logic 61. The NSC microprocessor 58 is an SBX interface, NLI50A,
An interrupt from the serial communication circuit of the microprocessor 58 can be received by a 10 mS signal generated in one NLI 50A.

The NSC / TSI interface to the SBX must communicate via the multiplexed address and data bus in response to control signals. There are several registers in the TSI 34 as part of the SBX. The NSC 36 and TSI 34 can be force reset by the SBX when one bit in one of these registers is toggled. The SBX can also interrupt the NSC microprocessor 58 by exciting the other bits in these registers. Furthermore, TS
1K word dual port R accessible by SBX to I34
There is also AM. This dual port RAM is specifically for passing control messages and data between the control system and the NSC card microprocessor 58. This dual port RAM can be accessed simultaneously from both directions, but data can only be transferred to this memory with a software controlled handshake.

The circuitry on TSI 34 must also be capable of converting between SBX bus word oriented parity and NSC / TSI byte oriented parity. 32 N for each NSC 36
It includes a LI array 50A. NLI50A (TS
The converted PCM and signal data (for I34), system clock and sync signals, and the communication link between NSC 36 and the network termination card microprocessor are brought together into a physical link. There are three interfaces to the NLI array. Each NLI 50A operates on a group of 24 channels. For each NLI 50A on NSC 36, an NLI 50B is associated with the network termination circuit.

Network links are used between the NSC 50 and each network termination circuit. Using a network link for each 24 channel group facilitates a maximum failure group size of 24 channels in the duplex scheme. In such a dual configuration,
A given network termination circuit has a network link to each of the two redundant NSCs 36. Network termination circuit is always both NSC3
Send a copy to 6 but "listen" to only one of them at a time
I can't.

A minimum of two physical wires are required for any complete link between the NSC 36 and the network termination circuit, N
A PCM / signal data path from the SC 36 to the network termination circuit and a PCM / signal data path from the network termination circuit to the NSC 36. In addition to the PCM and signal paths, each card residing in the network termination subsystem 27 must have three additional components for proper operation: system clock, system synchronization signals, and ( (Not shown)
This is a communication path with the network control microprocessor. In many systems, these three signal paths are provided on different physically separate wires than for PCM and signal data. In the network of FIG. 3, these functions are PCM.
And the line is designed to be uniquely provided to the same set of wires as for the signal data stream. Since only these two wires are needed from the NSC and network termination connections, a second set of wires for the differential transmission of each signal is used to maintain the required amount of cabling while maintaining reliability of the network link. You can increase the degree.

The network link interface integrated circuit, or NLI 50, is a special purpose integrated circuit designed to control network links as described above. The 3.088 MHz differential link connecting the NSC 36 to the network termination circuit is t
It is called an "o-port link", and the one that connects the network termination card to the NSC is called a "from-port link".

The NLI 50A at the NSC 36 end of the network link is said to operate in "master" timing mode because it has direct access to the system clock provided by the clock. The NLI 50A must derive a copy of the system clock from the pulse width modulation coded network link it receives. Thus, the network termination circuit NLI
The 50B is said to operate in "slave" timing mode. In the network termination circuit, a phase lock circuit is used to recover the 12.352 MHz system clock from the 3.088 MHz timing pulses on the receiving network link. This clock is 333Hz system sync pulse, 24
Channel PCM and accompanying signal data, and 768K
Used to sample coded data on the receiving network link where the bps communication channel is multiplexed. In this way, since the network termination circuit clock is synchronized with the system clock, a similar clock recovery method of decoding the receive network link of NSC circuit 50A is not needed and the data is provided from the master clock at 12.352 MH.
It can simply be sampled by the z clock. However, the phase delay and noise problems associated with long cables limit the length of the network link to 9.14 m (30 ft) for subsequent points. In practice, this maximum cable length is not a constraint, as the network and network termination functions can easily be placed within distance of each other.

Each network termination circuit has its own interface format to the NLI 50B for passing 24-channel data. The NLI 50B is provided with a "mode" select pin for the card on which it resides to specify the desired 24 channel interface.

Next, referring to FIG. 5, a control unit in the NSC 36, that is, a master unit, 5
The NLI circuit 50, which operates as 0A, is simply connected to another NLI circuit 50 of the DPC 42, which is preselected as a network terminator, or slave unit, 50B.

12.352 MH in NSC50A
The z frequency reference and the 333 phase reference are provided to the NLI 50A via lines 80 and 82. Two sets of fixed module counters 63, 64 are driven by these reference inputs. A 12.352 MHz frequency reference is provided as a clock input to each of these counters and a 333 Hz phase reference is provided as a sync (reload) input to each.
The module of the XMT counter 63 is the RCV counter 64
Is exactly the same as the module. Each consists of two steps,
The first stage is an 11-bit counter in the continuous clock input range from count 0 to 1543, and the second stage is a 5-bit counter in the range 0-23. The first stage of each counter must be in the range 0 to 1543 before the second stage can be incremented once. When the first stage counter reaches 1543 counts, the next 12.352 MHz clock input will cause it to go to zero. Similarly, when the second stage counter reaches 23 counts, the second stage count is reset to 0 the next time the first stage counter reaches the maximum value and receives the 12.352 MHz clock. Register is N
It is maintained as an input to these counters in LI50A. 20 and 23 show a microprocessor 58 for counter operation, and FIG. 4B shows an addressable register. These registers are microprocessor 58
Each time the XMT counter 63 and the RCV counter 64 receive a 333 Hz phase reference input on line 80, the values from these registers are inserted as the next count of these counters. In this way, the microprocessor 58 simply assigns different values to each of the associated counter load registers.
A phase difference between the MT counter 63 and the RCV counter 64 can be designated. This is similar to the XMT counter 6
5 is useful in NLI 50B with 5 and receive counter 66. These counter modules are NSC50
It is exactly the same as the A module. XM of NLI50B
T counter 66 and RCV counter 65 have 1
Only the method of adding the 2.352 MHz clock and the 333 Hz sync and possibly the counter load register value set by the microprocessor of the associated circuit when receiving the 333 Hz sync differs from the counter of the NLI 50A.

In the NLI 50A, the voice and control message data are given as inputs to the multiplexer 67 and finally transmitted to the network terminating circuit. The output of XMT counter 63 is used to select which of these inputs should be applied to line encoder 68.
The third input to the multiplexer is 333 to the transmission network link.
It is another output of the XMT counter 63 which indicates when the Hz sync signal should be applied. The line encoder operates on logic 0 or logic 1 data from the voice or control message inputs to produce the coded logic 0 or logic 1 symbols of FIG. To web link syn
Upon receipt of input indicating that the c symbol should be transmitted, the sync symbol of Figure 2 is generated.

At network end 50B, the output of NLI line encoder 68 is received after propagating on interconnect line 84. The received network link data is passed to the delay network 69 and then divided into two circuits 70 such as toggle flip-flops.
Is input to. Since each symbol received from the network link begins with a low to high transition, the once delayed receive network link is used as the clock input for this toggle flip-flop 70. As a result, a 1.544 MHz clock is input from the divide-by-two circuit 70, which is then added as an input to the phase locked loop 71 to 12.352 MH.
Generate the z clock. This 1 from the phase synchronization circuit 71
The property of 2.352MHz output is 3.08 of the receiving network link.
Four times higher in frequency than the 8 MHz data rate and every fourth low-to-high edge of this 12.352 MHz clock is more in phase lag than the low-to-high edge at the beginning of each receive bit interval of the receive network link. To do. The duration of this phase delay is essentially fixed as the duration of the delay block 69.

In this way, each receive network link bit interval was sampled four times using the 12.352 MHz clock and any of the three symbols output by the NSC line encoder 68 during a given bit interval. Can be identified. Sampling and decoding of received bits is a function of the line decoder and demultiplexer circuit 72. 12.352M generated by the phase synchronization circuit 71
The Hz clock is the RCV counter 65 in the network termination circuit.
And as a clock input to the XMT counter 66. When the line decoder and demultiplexer circuit 72 identifies that a sync input is being received from the incoming network link, this sync indication is provided via the phase synchronization acquisition circuit 73 means to the RCV counter 65 and the XMT counter 66.
Is added to the sync (reload) input of.

RCV counter 65 and XMT counter 6
6 operates in the fixed module, and the value to be taken in at the time of receiving the sync is fixed by the microprocessor of the associated network termination circuit by loading the associated counter load register (FIGS. 20 to 23). The acquisition circuit 73 compares the current value of each counter with its load register value and predicts that a sync symbol should be received from the incoming network link as the next input bit. If the next bit received from the incoming network link is not a sync symbol, an out-of-sync condition is indicated on the network termination circuit. If a sync symbol is received on the incoming network link and it is not predicted by comparison of the current value of any counter with its load value, the network termination circuit will again display an out-of-sync condition.

Once the network end RCV counter 65 and the XMT counter 66 are first synchronized with the NSC 36, they must remain synchronized. In the synchronized state, the RCV counter 65 outputs a signal used to demultiplex the decoded voice and control message data received from the line decoder and demultiplexer circuit 72 to the appropriate card circuit.
Similarly, voice and control message data to be sent to the NSC 36 is sent from another network termination card circuit to the network link transmission multiplexer 74. The XMT counter 66 provides another input to this multiplexer 74 which is inserted via the transmission network link during the sync bit interval. The XMT counter 66 output controls which bits of voice, control message or sync type should be sent at a given time.

On the other hand, please note that the network link data transmitted from the network end NLI 50B is not pulse width modulation coded. This output is exactly a logic 0 or a logic 1 throughout the 3.088 MHZ bit interval. X
The sync bit is output by the MT counter 66 to the network link to formulate a unique pattern of logic 0's and logic 1's.

RCV counter 6 on network end NLI 50B
5 is clearly frequency synchronized with its XMT counter 66. The phase difference between these two counters is controlled by the termination circuit microprocessor by specifying the value at the time of receiving the synchronous input. Similarly, NSC36 XMT
Counter 36 is obviously frequency synchronized with its RCV counter 64, and the phase difference is controlled by microprocessor 58 setting the value when sync is applied. Since the RCV counter 65 is synchronized with the XMT counter 63 of the NLI 50A by our pulse width modulation method, the network end XMT counter 65 is the RCV counter 6
4 is synchronized. In this way, the entire system is frequency-synchronized and phase synchronization is also achieved if the values in the load registers of all counters 63-66 are appropriate.

For convenience of explanation, the NLI in the NSC 36
The time delay along the bit output path by the 50A line decoder 68 is the network termination circuit D via the network link cable.
Propagated to SP44, propagated to line decoder and demultiplexer 72, fed back as an input to transmit multiplexer 74, propagated back to NSC via multiplexer and interconnection network link cable, input latch 75.
Shall be received by. With a limited interconnect cable length, the circuit of FIG. 5 allows round trip intervals to be less than 3.088 MHz bit intervals. The ability to easily receive uncoded network link data transmitted from network termination multiplexer 74 with latch 75 of NSC 36 is due to this circuit of FIG. 5 with its own synchronization and controlled time delay and It depends on the method. This latch 75 draws 3.0 from the NSC RCV counter 64 by simply dividing the 12.352 MHz clock that the RCV counter 64 receives.
It is clocked by an 88 MHz signal. The time when the 3.088 MHz output bit interval is started by the NSC line decoder 68 is the same as when the bit is sampled and received by its receive network link latch 75.

The data received by the NSC latch 75 is RC
It is demultiplexed by the demultiplexer 76, which is controlled by the output of the V counter 64, to the appropriate NSC circuit. Moreover, because all systems are synchronized,
It is possible to know in the NSC when the sync bit from the network end is expected. The extreme sync check circuit 77 receives an input from the RCV counter 64 to identify when a logical one level sync bit should be received from the network end and then samples the network link bit output received from the demultiplexer 76. When the end sync check circuit 77 identifies that the logical 1 sync bit from the network link is not received at the expected time or is received at the unexpected time, the network end 50B is directed to the NSC end 50A. Out of sync and the NSC microprocessor 58 is interrupted.

Referring to FIGS. 6A and 6B, network terminations, ie, slaves, transmitter link and receiver link sections of device 50B are shown. They operate with the waveforms shown in Figures 6C, 6D, 6E and 6F.

The circuit of FIG. 6A is incorporated into a single integrated circuit together with the circuit of FIG. 7A. Also, if the device is used as the network link interface 50A at the NSC end rather than as the NLI 50B at the network end, different portions of the circuit of FIG. 6A7A are also applicable. Similarly, if the device has N
Different portions of the circuit of Figure 6B7B are also applicable when used as network link interface 50A at the NSC end rather than as LI 50B.

In FIG. 6A, the relevant points of the network link transmitter at network termination 50B are designated A1-A7. In this example, the master / slave pin of NLI 50, FIG. 8, is fixed at logic 0 (indicating slave mode),
The appropriate NLI 50B portion of the NLI 50 circuit shall be enabled. The NLI receives input from the fixed module XMT counter 66. The XMT 66, FIG. 5, consists of two stages, the first stage is a 11-bit counter in the continuous clock input range of count 0 to 1543 and the second stage is a 5-bit counter in the range of 0 to 23. The first stage of the counter must be in the range 0 to 1543 and the second stage is a 5 bit counter in the range 0 to 23. The first stage of each counter is 0 to 1543 before the second stage can be incremented once.
Must be in the range. The 1st stage counter is 1543
When the count is reached, the next clock input received will cause the counter to go to zero. Similarly, when the second stage counter reaches a count of 23, the second stage count is reset to 0 the next time the first stage counter reaches its maximum value and a clock is received. The first stage counter output 66A is ICV
Although shown in FIG. 6A as AL00-ICVAL10, outputs ICVAL02 and ICVAL03 are not used. The second stage counter output 66B is shown in FIG.
They are indicated by MCT0-IFRMCT4. The XMT counter 66 outputs the output of the XMT counter 66 to ICVAL00,
The same 12.352 forced to the state of ICVAL01 = 0
Clocked by the low-to-high transition of the inverted copy of the MHz clock pulse.

Essentially, the 197, 198 signals are NOR'ed together to produce a network link bit output that lasts for 3.088 MHz. Output 1 if output 195 is low
96 is high. If output 195 is high, then DAT
The data input to the A IN circuit will be transmitted over the network link. However, if the output 196 is high, the output will be at the output 194. Output 194
The signal is network terminated NL while maintaining a unique pattern.
It is a means for outputting a synchronization bit from the I50B to the NSC NLI50A via a network link. Output 194 is output 19 sampled after the change in counter state has subsided.
Equal to 3 signal values. Similarly, the output 195 is equal to the output 192 signal value sampled after the counter state change has subsided. The output 196 is the complement of the output 195.

The following combinatorial logic equations completely describe the operation of the relevant parts of the circuit. Status output [ICVAL10-ICVAL00] = 00000XXXXXX However, only when X = irrelevant 191 = 1 [ICVAL10-ICVAL00] = 00000111XXX However, only when X = irrelevant 192 = 0 [IFRMCT4-IFRMCT0] = 00000 Only 193 = 0 [ IFRMCT4-IFRMCT0] = 00000 Only when sampling at 12.352MHz 194 = 0 [ICVAL10-ICVAL00] = 00000111XXX However, only when sampling at X = irrelevant 12.35MHz 195 = 0 Negative of 196 = 195 [IFRMCT4-IFRMCT0] not = 00000 When sampled at 12.352MHz, and [ICVAL10-ICVAL00] = 00000111XXX, but X = don't care Only when sampled at 12.352MHz, 197 = 1 [ICVAL10-ICVAL00] not = 00000111XXX However, sampled at X = irrelevant 12.352MHz, and 198 = 1 “DATA OUT TO NETWORK LINK” takes the following values only when “DATA IN” = 0. If [ICVAL10-ICVAL00] = 00000111XXX, but sample at 12.352MHz with X = irrelevant, and if [IFRMCT4-IFRMCT0] not = 00000 when sampling at 12.352MHz, “DATA OUT TO NETWORK LINK” = 0 12.352 When sampling at MHz, [ICVAL10-ICVAL00] not = 00000111XXX However, if X = don't care, when “DATA IN” = 0, “DATA OUT TO NETWORK LINK” = 0

Referring to FIG. 6B, the network end NLI 50
The B network link receiver has a logic 0 master / slave input (indicating slave mode) that enables the appropriate portions of the circuit. Data is related to network termination circuit 2
Received from one web link. As for this, the exchange method is redundant N
It keeps pace with the policy of having an SC circuit. The circuit interacts with only one of the network links 101, 102, which is selected by the microprocessor which sets the link select bit which selects the data on input 101 or 102 link A and the RCVD data from network link B. Whichever network link input is received, the data output 104 comes from the inverted output of the flip-flop of FIG. 6B, controlled by the decoding circuit shown. The toggle flip-flop 105 is the two-divided circuit 70 shown in FIG. The multiplexing circuit for selecting between the network link copy and the inherent delay of the toggle flip-flop 105 is represented by the delay circuit 69 in FIG. Since the reception network link data arrives at 3.088 MHz, the output of the flip-flop 105 is 1.544M.
Hz clock signal. This 1.544 MHz clock is applied as an input to the phase lock circuit 71 to output the 12.352 MHz phase lock circuit signal (FROM shown in FIG. 6B).
PLL) and is used to clock the XMT counter 66 and RCV counter 65. Load input signal (C to the XMT counter 66 and RCV counter 65
TR SYNC) is produced by the circuit shown in Figure 6B and which represents the means for achieving system synchronization. CTR SYN
The C signal is generated by the circuit of FIG. 6B upon receipt of the sync24 symbol in the received pulse width modulation coded network link data.

The operation of the circuit of FIG. 6B will be described with reference to FIGS. 6C to 6F.
Shown in the figure. FIG. 6C shows a CTR SYNC for synchronizing the arrival and exchange of sync24 symbols to the receiving network link.
Shows the evolution of the signal. Figures 6D-6F show the continuation of operation during the receive sync24 intersymbol interval for clarity. Looking at the labeled points in the circuit of FIG. 6B,
The following can be seen from FIGS. C to 6F.

Line 7 shows the receiving network link data. The figure starts with the last part of the arrival of the asynchronous bits, and two consecutive syncs
The arrival of 24 symbols continues. In each bit interval on the 7th row, the hatched portion represents a logic 0 and the non-hatched portion represents a logic 1.

The sixth row is T-FF 1.5 for the phase-locked loop.
Represents a 44 MHz output. Lines 1 to 6 represent internal signals of the phase locked loop, and lines 2 are used by the circuit of FIG. 6B.
2.352 MHz is shown and row 5 represents the phase synchronization frequency and phase synchronization with the T-FF output in row 6. 12.352
The MHz clock is a flip-flop of the circuit of FIG. 6B,
It is used to clock the counter and shift register stages directly or in the inverted form.

The 8th row shows the Q output of FF1. Each pulse width modulation bit is sampled four times by FF1 according to the high to low transition of the 12.352 MHz clock.
In this way, each pulse width coded bit is reproduced at the output of FF1 with a slight delay from the actual arrival at the network termination circuit. The Q output of FF1 is applied as a load input to the synchronous 4-bit counter and then clocked by the 12.352 MHz low-to-high transition. Whenever a logic 0 level is a termination card, the Q output of FF1 is applied as a load input to a synchronous 4-bit counter and then clocked by a 12.352 MHz low-to-high transition. Whenever a logic 0 level occurs at the load input of this counter during the 12.352 MHz low-to-high transition, the output of the counter will be [QD-QA] = 000. If the load input of the counter is a logic one during the 12.352 MHz low-to-high transition, the counter increments its count by one.

The 9th row is a continuous 12.352MH when the received network link data matches the pattern of the 7th row.
The output of the 4-bit counter during the z clock cycle is shown. Note that the output of the counter reaches the value [QD-QA] = 0011 only during these intervals when a synch 24 symbol is received from the network link. Flip-flops FF2A and FF2B receive their D inputs directly from the output of this counter. FF2A and FF2B are clocked by the low-to-high transition of the inverted output (XQ) of FF1. The low-to-high transition at the inverted output of FF1 occurs when the delayed and sampled receive network link data inverts from a logic one to a logic zero to complete the positive pulse. Flip-flops FF2A, FF2B and subsequent stages complete this positive pulse at any of the four sample points taken within the 3.088 MHz bit interval to decode the symbol received from the 20, 22, 24 set. Evaluate what to do.

Lines 10 and 11 are FF2A, respectively, when the received network link data matches the pattern of line 7.
The output from FF2B is shown. From FIG. 6B, FF3A,
Note that FF3B receives its D inputs from FF2A and FF2B, respectively. FF3A, FF3B
Is clocked by the low-to-high transition of the actually received network link data (delayed by the multiplexing circuit) so that its output is updated every 3.088 MHz interval. At a given 3.088 MHz, a 4-bit counter counts up once for each time (up to 3 times) the received network link data sampled by FF1 is a logical 1 and the actual network link data is a logical 1 The "highest count" achieved by the 4-bit counter when transitioning to a logical 0 is latched in FF3A and FF3B.

Lines 12 and 13 are FF3 when the received network link data matches the pattern of line 7, respectively.
The outputs of A and FF3B are shown. Flip-flops 4A, 4
B is clocked by a high to low transition of combinatorial logic acting on the outputs of FF3A, FF3B. FF4A
Is the decoded output of each network link bit to the circuitry of the network termination card. FF4A produces a logic one, indicating that a zero symbol 20 has been received. If the first and second quadrants of the received network link bit interval are both logic ones, FF4A outputs a logic one to the circuit to indicate that a zero symbol 20 has been received. XMT counter 66 and RCV
The output of flip-flop FF4B is provided to an 8-bit shift register to determine the appropriate time to provide the CTR LOAD signal to counter 65.

Lines 14 and 16 are respectively FF4 when the received network link data matches the pattern of line 7.
The outputs from A and FF4B are shown.

The 17th row shows the output of the 8-bit shift register [SR] which receives the input from the FF 4B and is clocked by the low-to-high transition of the 12.352MHz clock provided from the phase locked loop.

Line 18 shows the CTR SYNC signal applied to XMT counter 66 and RCV counter 65 to achieve system synchronization. The CTR SYNC signal is formulated by sampling the output of the combinatorial logic driven by the SR output after the stable period of the low to high transition of the 12.352 MHz clock provided by the phase locked loop.

The remaining rows of FIGS. 6C-6F show the synchronized XMT counter 66 and RCV counter 65 outputs. In particular, comparing lines 20 and 25, it can be seen that the 3.088 MHz bit interval is maintained in phase for both the transmitting and receiving network links. 6C to 6F and 7D
The timing diagrams shown are complementary to each other. Taken together, the timing of the switching scheme and its particular time division multiplexing strategy is captured and fully described. The circuit of Figures 6A and 6B is central to this function of the network end 50B of the network link.

Referring to FIGS. 7A and 7B, the transmission link encoder section and the reception link decoder section of the master control unit 50A are shown. These circuits operate according to the waveforms of Figures 7C and 7D.

Referring to FIG. 7A, it is the same as shown in FIG. 6A. Similarly, the circuit of FIG.
It is the same as the circuit of FIG. This is the case when they are made in one integrated circuit. NLI 50 is network end 50B
Different portions of the circuit of Figure 7A (6A) are applicable if they are used at the NSC end of the network link rather than at. Similarly, if the NLI 50 is used at the NSC end of a network link rather than at the end of the network, the different portions of the circuit of Figure 7B (6B) can be applied. In Figure 7A, the master / slave pins of the device are fixed to logic 1 (indicating master mode), enabling the appropriate portions of the circuit. The transmitter of FIG. 7A receives an input from the fixed module XMT counter 63 of FIG. The XMT counter 63 consists of two stages, and the first stage has 11 of the continuous clock input range of 0 to 1543 counts.
It is a bit counter. The second stage is a 5-bit counter in the range 0-23. Until the second stage can be incremented once,
The first stage of each counter must be in the range 0 to 1543. When the first stage counter reaches the count 23, the output of the first stage counter reaches the maximum value next time, and when the clock is received, the output of the second stage returns to 0. The first stage counter output 171 is referred to as ICVAL00-ICVAL10. The ICVAL02 and ICVAL03 outputs are not used. The second stage counter output 172 is shown in FIG.
Called CT0-IFRMCT4. XMT counter 6
3 is clocked by the low-to-high edge of the inverted copy of the same 12.352 MHz clock of FIG. In addition, the data input to the circuit output to the network link is XMT.
Counter 63 output is forcibly forced to ICVAL00, ICVA
Given for a total interval of 3.088 MHz in phase with the high to low edge of the same 12.352 MHz clock pulse with L01 = 00.

Essentially, the 179 signal is inverted to 3.
This produces a network link bit output that lasts for 088 MHz. Note that 179 is equal to the value of 178, which is sampled after the 178 signal has stabilized from the change of state of the counter. 178 signals are signals 174, 175, 176
And 177 are NORed. 17
The 4,175,176 and 177 signals each serve to generate a pulse width modulated output to the network link. 1
The 74 signal is formulated to ensure that the pulse width modulated output during the first quadrant of each 3.088 MHz bit interval will be a logic one during the sync bit time. 177
The signal is formulated to ensure that the second quadrant of the 3.088 MHz bit interval is a logic one during the sync bit time. The 176 signal is formulated to ensure that the third quadrant of the 3.088 MHz bit interval is a logic one during the sync bit time. The 175 signal is formulated to be a logic one for the second quadrant of the 3.088 MHz bit interval during the asynchronous bit time where the data input to the circuit (DATA IN) itself is a logic one. Similarly, the second quadrant of the network link output 3.088 MHz bit interval is forced to be a logic zero when the data input (DATA IN) itself is a logic zero during such an interval.

The following combinatorial logic formula describes the operation of the relevant portions of the circuit of FIG. 7A. Status output [IFRMCT4-IFRMCT0] = 00000 only 171 = 0 [ICVAL10-ICVAL00] = 00000XXXXXX However, only X = irrelevant 172 = 1 [ICVAL10-ICVAL00] = 00000111XXX However, only X = irrelevant 173 = 0 [ ICVAL10-ICVAL00] = XXXXXXXXX00 but only when X = irrelevant 174 = 1 [ICVAL10-ICVAL00] not = 00000111XXX However, only when X = irrelevant and ICVAL1 = 0 and “DATA IN” = 1 175 = 1 FRMCT = 00000 and [ ICVAL10-ICVAL00] not = 00000111XX0 However, only when X = irrelevant FRMCT = 00000 176 = 1 and [ICVAL10-ICVAL00] not = 00000111XXX However, only when X = irrelevant and ICVAL1 = 0 177 = 1 178 = NOR (174, 175 , 176, 177) 179 = 178 Sample at 12.352MHz “DATA OUTPUT TO NETWORK LINK” = 179's complement

Referring to FIG. 7B, in this example NL
The I50A master / slave pin is tied to logic 1 (indicating master mode), enabling the appropriate parts of the circuit. Data comes from network link and NLI
The 12.352 MHz clock and 333 Hz (ISSYNC) sync input to the NLI 50, which is passed to the 50A and from its data output to the NSC 36 circuit, is a NLI X
12 MH for clocking and loading the MT counter 63 and RCV counter 64 respectively to synchronize the switching scheme
Continue to z clock and 333 Hz (SYNC) sync signal.

In FIG. 7B, the data at the input 150 (RCVD DATA FROM NETWORK L
INK) is received synchronously according to the overall timing control of the fact exchange scheme. Input 152 (INPUT DAT
A MAX CONTROL is always set to a logic 1 by the NSC 36 microprocessor and has an input 150 to an output 153 (DATA OUTPUT TO CARD).
CIRCUIT) to the path. NSC
Since the data received from the network link via the NLI 50B is uncoded, one property of the method used is that it does not require any circuitry to decode.

The overall timing control of the exchange system has been described in the examination of FIG. Some of the important factors in achieving the above-described synchronized operation are shown in FIGS. 7B and 7C.
It is shown in the timing diagram of the figure. The various points in FIG. 7B are labeled A, B, C, D, E, F and the timing for each point is shown in FIG. 7C. FIG. 7C shows a 12.352 MHz clock and 333 Hz applied to the circuit.
(ISYNC) Indicates a sync signal. The nature of these signals is that the 12.352 MHz clock toggles indefinitely. 37056 (at 3mS intervals) 12.352M each
Every Hz cycle, the ISYNC signal, which is normally a logic one, transitions to a logic zero for an interval of two cycles of 12.352 MHz at the indicated phase. This pattern of ISYNC signals also continues indefinitely. Exchange method N
The XMT counter 63 and the RCV counter 64 at the SC end are the inversion form (12 MHz) of this 12.352 MHz signal.
Clocked by. The circuit of FIG. 7B forms a load signal (SYNC) which phase synchronizes these two counters, and then system timing control is managed through stages AF. Circuit control 12.352 MHz and signals A to F and SY for ISYNC input timing
NC timing is shown in FIG. 7C.

FIG. 7D shows the circuit shown in FIGS. 7A and 7B, the XMT counter 63 and the RCV counter 6 shown in FIG.
4 shows the relationship among the four and the synchronization operation of transmission / reception network link data.

Referring to FIG. 7D, line 3 shows the timing of the 12.352 MHz clock input to the circuit of FIG. 7B and line 4 shows the timing of the 333 Hz phase synchronization input (ISSYNC) to the circuit of FIG. 7B. Shows,

Row 6 shows the 12 MHz clock input shown in FIG. 7B to the XMT counter 63 and RCV counter 64 of FIG. 5 which controls the overall timing of NSC end 50A operation. Line 7 shows the 333 Hz (SYNC) phase sync input shown in FIG. 7B to the XMT counter 63 and RCV counter 64 of FIG. 5 which controls the overall timing of NLI 50A operation.

Row 10 is 3. RCV counter 64 used by latch 75 shown in FIG. 5 to sample the NLI 50A receive network link data during a low to high transition.
088 MHz output is shown. Row 12 is the XM used at the transition from low to high and to start the network transmission interval of the line encoder 68 of FIG. 5 for each bit output of the NLI 50A.
The 3.088 MHz output of the T counter 63 is shown.

The 13th row is NLI by the latch 75 of FIG.
The timing of the network link data received with 50A is shown. The black portion of this row is an area where the method used for the exchange method stabilizes the propagation delay and guarantees that the data is valid. Lines 14 to 17 show the role of each network link bit received by the time division multiplexing method used in this switching system.

Line 19 shows the timing of the PCM data sent to the circuit of FIG. 7A and output to the network link. 21
The row shows the role of each network link bit transmitted and its role in the time division multiplexing method used in this switching scheme. Each network link bit transmitted is 3.0 as shown in line 12.
It is shown to start on the low-to-high transition of the 88 MHz clock. Pulse width modulation coding is enhanced for each bit transmitted during these 3.088 MHz intervals.

The timing diagrams shown in FIGS. 7D and 6C-6F complement each other. Together, the timing of the switching scheme and its specific time division multiplexing strategy are captured and fully described. The circuit shown in FIGS. 7A and 7B has N
It provides the core of this function of LI50A.

The NLI 50 of FIG. 8 is the control subsystem associated with the line 30 and the network end shelf, or NSC.
A network link connecting the circuits 36 is generated and controlled. 3.
There is an NLI 50 at each end of the 088 MHz network link, and each NLI 50 handles a set of links, one for each transmission direction. In a given card, the NLI 50 converts the PCM, signaling, and message information passed through it into a serial stream and adds some framing and synchronization bits to send this data in coded form to the network link. .. In the other direction, NLI 50 performs line decoding and PC
Extract M, signal, and message information and pass to appropriate card circuitry. The coding used to transmit data from the control subsystem to the network terminator over the network link is a pulse width modulation type, where variable length pulses are used to represent 0, 1, and synchronization digits. on the other hand,
The coding of the network link data sent from the network terminator to the control subsystem is strictly NRZ, FIG. 1A. There are several formats for passing PCM and signaling data for the NLI, and a separate mode of the device is defined for each.

Referring again to FIG. 9, each NLI 50 controls 24 channels of PCM and signaling data. NS
Since the C circuit 36 handles 768 channels, it must have a 32NLI circuit 50 on the board to handle all channels to be addressed. DAS37, third
The figure supports 96 channels and thus requires four NLI circuits 50 per board. The DPC, PRI, BRL and DSP circuits, each supporting 24 channels, require only one NLI circuit 50 per board. In addition to the difference in the number of NLI circuits 50 for each of these circuits, the method of processing the passage of data to each NLI circuit 50 and the method of controlling the internal timing of each NLI circuit 50 are also different. FIG. 9 shows how the NLI 50 is used in the scheme of FIG. 3, and FIG. 10 shows the device data I / O and internal timing control mode used in each card. The NLI 50 I / O mode is specified by the hardwire NLI mode selection pins A and B 81, FIG. The internal timing control of the NLI 50 is N
The LI master / slave pin 80, FIG. 8, is fixed by hard wiring.

NLI 50 and NSC circuit 36 operate in mode 0 as specified by wiring both mode select pins A and B81 to logic 0. In mode 0, the network link transmission data is represented by 11 parallel bits consisting of 8 PCM and 3 "system" bits. The three system bits are a parity bit, a framing bit, and a superframe synchronization signal (SFSS) bit. The same 11-bit parallel format is used to output the data received from the network link. The NLI circuit 50 on the NSC card 36 is set to 1 by the system clock.
A 2.352 MHz clock and a 333 Hz synchronization pulse are provided. To use these signals for master timing control, the master / slave pin 80 of each NLI 50 must be set to logic one.

DS1 port 42, PRI 40 and BRL
NLI circuit 50 on 38 operates in mode 1 as designated by wiring mode pin A to logic 0 and mode pin B to logic 0. In mode 1, PC sent via network link
M data is provided as a 1.544 MHz serial bit stream. The serial PCM stream is organized into frames of 24 8-bit samples, each such set of 192 bits being preceded by a frame bit. The signal data in mode 1 has four parallel inputs (A, B, C, D) to the NLI 50, which coincide in timing with the reception of 8-bit samples of each channel of the serial PCM input stream.
Given as. In Mode 1, the PCM data received from the network link is the same as that used for transmission 1.5
Output by NLI 50 in 44 MHz serial format. However, the signal data received from the network link does not appear on the NLI pin, and this data is not present on the PCM of the serial output stream during the system defined "signal frame".
Is replaced with the least significant bit, LSB. Please note that BRL38 does not use the signal bit processing method of NLI50. Data port circuit 42, PRI circuit 40
And the NLI circuit 50 of the BRL circuit 38 is its master /
Slave pin 80 is set to a logic 0, along with synchronization information obtained from the receiving network link, NLI circuit phase synchronization circuit,
The internal timing is controlled by the 12.352 MHz clock obtained from FIG. 5, (PLL).

The NLI circuit 50 of the DAS circuit 37 operates in mode 2, designated by wiring mode pin A to logic 1 and pin B to logic 0. In Mode 2, the PCM data transmitted on the network link is provided to the NLI 50 as eight parallel PCM bits. Similarly, the data received from the network link is N parallel PCM bits, N
Output from LI50. The A port signal data is extracted from the PCM LSB of each channel of the receive link during the system defined A port signal frame, stored, and subsequently read by the circuit's microprocessor. The NLI circuit 50 of the DAS circuit 37 sets its master / slave pin 80 to a logic 0 and is provided by the phase synchronization circuit (PLL) of the card, FIG. 5, along with the synchronization information obtained from the receiving network link. The internal timing is controlled by the .352 MHz clock.

The NLI circuit 50 of the DSP circuit 37 operates in the mode 3 designated by wiring both mode selection pins A and B to logic 1. In mode 3, the PCM data to be transmitted is presented to the NLI 50 as a 1.536 MHz serial data stream consisting of 24 8-bit PCM samples. 2 PCM data received from network link
1.536 MHz consisting of 4 8-bit PCM samples
It is also output from NLI as a serial data stream. The A port signal data is extracted from the PCM LSB of each channel of the receive link during the system defined A signal frame, stored and later read by the circuit's microprocessor. The NLI 50 of the DSP circuit 37 sets its master / slave pin 80 to a logic 0, and the phase-locked circuit (P
LL), FIG. 5, 12.352 MHz given by
The clock controls the internal timing.

NLI 50 performs various functions.
It has 24 channels of PCM and signaling data 3.08
3.08 received after converting to 8MHz serial bit stream
Convert 8 MHz serial bit stream to PCM and signal data. It uses a packet protocol to embed the message information into each outgoing network link and extract the message information from each incoming link. It also performs link synchronization by embedding a clock in each transmission network link using the pulse width modulated line decoding and by embedding a "sync" bit 24 in the serial data stream, clocking and syncing from each receive link. To extract. PCM
And signal data insertion / extraction registers are provided for background testing, and signal storage with microprocessor access is provided for received A signal bits. There is also a microprocessor interface for message information processing and chip control.

Referring to FIG. 11, the NLI 50 has five interfaces, which are the outgoing data interface, the outgoing link interface 82, the incoming link interface 86, and the incoming data interface 8.
8 and a microprocessor interface 90. Outgoing data interface 82 provides a means for the card to pass PCM and signaling data over a network link.
This data is the microprocessor interface 90
Is combined with the information designated for transmission by the transmission link interface 84 and transmitted to the outgoing network link by the transmission link interface 84 in the pulse width modulation coded format. In the other direction, the data received from the network link 47 is received by the receive link interface 86.
Where the PCM and signal data is extracted and sent to the incoming data interface 88 for output from the NLI 50. The message information is also extracted from the receiving network link 47 and passed to the microprocessor interface 90. The connection between the microprocessor interface 90 and the transmission / reception interfaces 84 and 86 is a FIFO.
Via 91.

NLI input and output data interface 8
Although there are several formats for the data flowing through 8, 82, the format of the data on each network link 47 is
Whether it is generated by the transmission link interface 84 or received by the reception link interface 86,
It is always as shown in FIG.

Outgoing data interface 82 receives parallel or serial inputs for network link transmission. The operation of the outgoing data interface 82 depends on strapping the NLI mode select pins.

As mentioned above, each of the 32 NLI circuits 50 of the NSC circuit 36 receives parallel data for network link transmission on each of the 24 channels. This data is 7
It is derived from the 68 channel TDM bus. Referring to FIG. 12, each NLI 50 latches a set of 24 11-bit samples at approximately a 192 KHz rate. The timing of this latching is a 12.352 MHz control time base clock, FIG. 5, and an NL driven by a 333 Hz synchronization pulse provided to each element of the NSC circuit 36.
It is derived from the counter in I50. To identify which 24 channel set of the 768 channel bus is for a given circuit, each NLI 50 has 0-31
It has a position register to which the value of is loaded. NSC
Each NLI 50A in circuit 36 has a different value in its position register. The 11 bits passed to each NLI 50A are generated by the TSI circuit 34 and consist of 8 PCMs and 3 system bits. The three system bits include a parity bit, a frame bit and a super frame sync signal (SFSS) bit. All of these inputs, except SFSS, come from the exchange complex. S
The FSS bit is generated from the signal circuit of the TSI circuit 34,
It is passed to NLI 50 in parallel with the other 10 bits. NLI
The parity received by 50 is on the eight PCMs and one frame bit generated by the TSI 34, the parity check is on the outgoing data interface 82,
This is done within FIG. When a parity error is detected, the appropriate bit in the NLI interrupt status register, Figure 18, is set and the microprocessor of the DPC circuit is interrupted. The remaining 10 regardless of the result of the parity check.
Data bits are transferred to the transmit link interface 84.

In the DPC circuit 42, FIG. 4A, and the PRI circuit 40, FIG. 3 and FIG. 9, the serial PCM and parallel signal data are output from the data interface 82.
And is transmitted via the network link 47. The serial stream contains 24 channels of PCM data and frame bits are received at a rate of 1.544 MHz. NLI 50 pin 92, FIG. 8 is DP to generate this data stream.
Transmission 1.5 used in C circuit 42 and PRI circuit 40
It is provided to derive the 44 MHz clock.
8KHz transmission synchronous output pin 100, FIG. 8 is NLI5
It is provided on the NLI 50 so that the channel order can be extracted on the 0. The timing of each of these clock signals is 12.352M from the NLI PLL pin to the NLI 50.
It is derived from the received network link synchronization information with the Hz input.

The 8-bit PCM samples for each channel are extracted from the received serial stream and converted to parallel form. The serial stream frame bits are latched and passed to the transmit link interface 84 in parallel with the parallel PCM data for each channel. The 4 bits of signal information received by outgoing data interface 82 represent the A, B, C, D signal bits for each channel. Based on the system-defined superframe timing, the appropriate signal bit is selected from the four received and sent to the transmit link interface 82 in parallel with the PCM and frame bits. Under the control of the microprocessor, this signal data can also be specified to replace the LBS of the outgoing PCM sample. This kind of control is a transmission signal control register,
It is maintained on a channel-by-channel basis by processor designation for each channel in FIG.

The operation of output data interface 82 is BRL except that no signal bits are passed to NLI 50.
Compared to circuits 38 and 39.

In the DAS circuit 37, 24 8-bit parallel PCM samples are given to the output data interface 82 every 125 μS and transmitted to the network link. NL
The I50 provides the DAS 37 with an 8 KHz transmit sync output on pin 93, which can be used with the 12.352 MHz clock on the board to derive the timing and channel order that is passed to the output data interface 82. The DAS circuit 37 supplies data to the NLI 50 and transmits it at a 192 KHz rate. This data is then transferred to the send data interface 84.

On the DSP circuit 42, the serial PCM data is received by the output data interface 82 and transmitted to the network link 47. The serial stream contains 24 channels of PCM data and is received at the 1.536 MHz rate. N
The LI50 1.536Hz transmit clock pin 95 is a DS
It is provided to derive the clock used in P circuit 44 to generate this data stream. The 8 KHz transmit sync pin 93 is also used to determine the channel order.
The 8-bit PCM samples for each channel are extracted from the serial stream, converted to parallel format and passed to the transmit link interface 84.

The transmit link interface 84 receives data from the outgoing data interface 82 and the microprocessor interface 90. The 16-bit data transmitted on the link combines 10 bits (up to) from the output data interface 82 with 4 bits from the microprocessor interface 90 to generate odd parity on the set and add the fixed bit to a logical one. Formed. 24 such words are formed every 125 μS. Two link sync bits are added to these 24 16-bit words to serialize the entire block of information. The setting of the NLI master / slave pin 80 determines the coding used for the outgoing 3.088 MHz stream. The NLI circuit 50, which is seized to act as the master 50A, can derive the clock from the low-to-high transition that causes the NLI circuit 50, acting as the slave 50B at the end of the network link, to start each bit interval. To use pulse width modulation coding.
The NLI circuit 50 that is captured as the slave 50B has 1
3.08 as a simple NRZ, where is represented as a high voltage and 0 is represented as a low voltage for all bit intervals.
Output 8MHz.

The reception link interface 86 is 3.0
It receives the 88 MHz network link and immediately passes the stream to the decoder. The data transition of the received stream is detected by the pulse width modulation decoder, FIG. 5, at 3.088M.
The Hz clock is derived. This clock is divided into two to form a 1.544 signal which, from the NLI 50B to the phase locked loop circuit, FIG. 5, to the NLI circuit 50B which is designated for slave operation by its master / slave pin 80 setting. Sent there 12.352MHz
Are generated and returned to the NLI 50 to be used to derive all timing. The serial data output of the decoder is clocked into the shift register at the 3.088 MHz rate to convert the data to parallel form. A 16-bit word is thus formed, which is a 10-bit to incoming data interface 88, a microprocessor interface 9
It consists of 4 bits to 0, a parity bit for the whole word, and a fixed bit of logic 1. If the properly received data word is verified using the odd parity checker and a parity error is detected, then the appropriate bit in the NLI interrupt status register, FIG. Interrupted. 3.0
38 transmitted every 125 μS on 88 MHz link
There are 6 bits. Channel data (24 in 16 bit words
Since only 384 are used for the set), 2 more bits of link synchronization information are also received in the data stream. These bits are passed to the counter / timer circuit 92, FIG. 11, where they are used to obtain synchronization with the link transmitter.

The incoming data interface 88 receives 10 bits from the receive link interface 86 and sends this data in parallel or serial form.
The mode select pins on NLI 50 are used to select the output mode for each card.

In the NSC circuit 36, the data from each of the 32 input data interfaces 88 are merged into 76.
Form an 8-channel TDM bus. Each NLI master circuit 50A has a set of 11 11-bit samples of about 1
It occurs at a rate of 92 KHz. The timing of this latching is NSC according to the clock card 32, FIG.
12.352M provided to each NLI 50A of circuit 36
It is derived from a counter in the NLI circuit 50A driven by the Hz clock and the 333 Hz synchronization pulse. Each NLI circuit 50A has a position register that is loaded with a value from 0 to 31 to determine when to output to this 768 channel bus. Given NLI circuit 5
When 0A is not outputting data, its output pin remains in a high impedance state. Given NLI circuit 5
If 0A is outputting data, EX of that NLI50
The G pin 97 generates a low level pulse used for the special purpose of the NSC circuit 36.

11 bits of output are given from the input data interface 88 of each NLI circuit 50, and 8 PCs are provided.
It consists of M and 3 system bits. The three system bits include parity bits, frame bits and SFSS bits. All of these outputs are sent to the TSI circuit 34 except the SFSS bit, and the 9 non-S
Parity occurs in the FSS data bits. The SFSS bit is sent to the signal circuit of the TSI circuit 34 in parallel with the other 10 bits.

In the DPS circuit 42 and the PRI circuit 40, the serial PCM data is output by the input data interface 88. Serial flow is PCM data 2
Includes 4 channels and frame bits, 1.544MH
Sent at z-rate. Reception of NLI 1.544MHz
Clock pin 92, FIG. 8, is for DPC 42 and PRI 4
Zeros are provided for use in latching this data stream. A 333 Hz receive sync output pin 94 is also provided to allow these circuits to derive the channel and frame order. The timing of each of these clock signals is 12.352 MHz from the NLI phase locked loop circuit.
It is derived from the received network link synchronization information along with the z input.

Signal information obtained for each channel at the SFSS bit position of the receiving network link can be inserted into the LBS of each PCM word output by the input data interface 88 according to the system-defined superframe timing. This can be selected on a channel-by-channel basis by setting the bit corresponding to the channel in the receive link signal control register, Figures 33-35, under the control of the microprocessor. The operation of the incoming data interface 88 is comparable to the BRL circuit 38, except that no signal bit information is inserted into the PCM sample.

In the DAS circuit 37, 24 8-bit parallel PCM samples are output by the input data interface 88 every 125 μS. 4 N on the card
For each of the LI circuits 50B, an explicit value is defined in its position register, FIG. 19, to define when each should provide a parallel output to the common output bus. When a given device is not passing data from this incoming data interface 88 to this bus, its output pin remains in a high impedance state. The DAS circuit 37 is N
The OSYC pin 98 of LI circuit 50, FIG. 8, is used to determine when output data should be latched from a given NLI circuit 50B.

In the DSP circuit 42, the input data interface 88 outputs serial PCM data. The serial stream contains 24 channels of PCM data and is transmitted at the 1.536 MHz rate. 1.536 MHz receive clock pin 9 to generate the clock that DSP circuit 44 uses to generate this data stream.
Two are provided. It is clear that the 8 KHz receive sync pin 100, FIG. 8 and the 1.536 MHz and 8 KHz pins interact with the incoming data interface 88 and these with the outgoing data interface 82. Each set has a different phase than the others. The 8-bit PCM samples for each channel are extracted from the serial stream, converted to parallel format and passed to the transmit link interface 84.

Signal bits are provided on the LSB of the PCM sample during the system-defined signal frame for the channel that the DSP circuit 42 receives. Signal bit is NL
The I data circuit 50 captures the received data register, 36th
Figures 38-38 and are read by the card microprocessor.

Microprocessor interface 90
Provides various registers that allow the microprocessor to communicate with the NLI circuit 50 and control its functions. One major function controlled by the microprocessor interface 90 relates to passing messages between circuits. This circuit is transmitted 3.088
It performs the necessary functions associated with embedding message information in the MHz network link and extracting such information from the receiving link. The message and associated control information are allocated 4 bits out of each 16 bits over the network link. These information bits are sent at a 768 Kbit / sec rate using the packet protocol. Communication between the control unit and the network terminator is always done by the NSC circuit 36.
It starts from. When it is necessary to send message information to the network card, the NSC 36 microprocessor sends NLI up to 64 bytes, the first byte being the byte count, via means for writing to the send message data register, FIG. Buffer to FIFO. The microprocessor then sends the word containing a logical 1 in the outgoing message bit position to the NLI control register, the 17th.
Figure, write to. The NLI 50 "packets" the message bytes according to the protocol shown in Figure 13 and adds flags, status fields, and checksum bytes around this information field. During the period when no message is sent, the NLI circuit 50 outputs 768 Kbit /
Please understand that non-flag characters are output to the seconds field.

The NLI circuit 50 always searches for incoming message information by checking the release flag in the message field of its receive link. Once the open flag is recognized and the byte count is determined, the NLI circuit 50 buffers the message byte in the receive FIFO. The running checksum of the message byte is kept as received and compared to the checksum given to the incoming message. If the received checksum is different than that calculated, the appropriate bits in the interrupt status register, FIG. 18, are set and the microprocessor of the circuit is interrupted. Upon receipt of a valid message, the receive status register, FIG. 18, receive FIFO all bits are set and the received status field bits are interrupted and acted upon.
In the NSC circuit 36, the received message is detected by polling each interrupt status register of the NLI circuit 50, FIG. 18, and it is checked whether or not all the bits of this reception FIFO are set. The message is then read from the NLI circuit 50 via the Receive Message Data Register, FIG. The first byte read is the byte count and the microprocessor must loop that number of times to read the 63 (up to) other bytes.

NLI circuit 50 functions similarly in all other modes except as noted below. First, upon receipt of an incoming message, the circuit's microprocessor will
Interrupted with the receive FIFO full indication in the I Interrupt Status Register, FIG. Second, when a message is received, the receive FIFO is "locked" so that the message is not overwritten by a second message to the card. Obviously, any subsequent messages passed while the FIFO is locked will be lost. After extracting the current message from the receive FIFO, the processor changes the F bit by changing the appropriate bits in the control register, FIG.
It must act to unlock the IFO. No FIFO locking mechanism is available on the device, such as NSC card 36, where the master is designated as master / slave pin 80. Finally, the NLI 50 designated to operate in modes 1-3 should not send a message until it receives a message requesting a response. However, nothing binds the sending of unsolicited messages.

The NLI circuit 50 "packages" messages from the processor using a protocol consisting of an open flag, a status field and a checksum of all preceding bytes except the open flag. The release flag indicates the start of the message and is always 7EHex (01111110).
Has a binary value. The status field is an 8-bit field used to send control information from the NSC circuit 36 to the network card, and its content is NS.
It has no meaning to the link to C36. The status field bit is used to return the NSC circuit 36 to the processor, perform a non-maskable interrupt (NMI), or switch the bus that received the serial information.
64 (up to) bits of message information are transmitted after the status field, and the first byte of the information field is always the byte count for that field. A checksum is calculated during transmission of this data. This checksum byte is inserted into the link after completion of the info field,
Provide a means for the far end to check message integrity.

The bytes that start the information field are 0-6
Please understand that the range of 3 can be taken. To simplify the pass status field information between cards,
For example, a 0 byte count message can be sent. However, a 0 byte count message that is properly received by the slave device will be interpreted and acted on even if the receive FIFO is locked. A 63-byte count message has a 1-byte count digit and 6
A message with a complete full information field consisting of 3 actual data bytes.

The NLI circuit 50 is designed not only to generate the parity of outgoing data, but also to recognize the parity error of incoming data. Parity errors can be detected on outgoing parallel data from TSI mode 0, received 3.088 MHz serial data in all modes, or bytes transferred from either of the two FIFOs maintained in NLI circuit 50. Odd parity is used for 3.088 MHz serial link, even parity is used for two internal FIFOs, parity type is selected via control register for Mode 0 TSI data check and generation, The type of parity violation is NLI status register, 18th
Shown in Figure, always accompanied by a circuit microprocessor interrupt. If the microprocessor wishes to mask either of these parity error interrupts, it does so by setting the corresponding bit in the control register, FIG. In addition, if the microprocessor wishes to have any or all of these errors test its own diagnostic software, the bits in the control register, FIG. 14, are also designated for that purpose. Similar to the parity check, NLI circuit 50 always looks at the checksum byte associated with each received message. If the checksum value calculated during receipt of the message does not correspond exactly to that given to the message, the circuit's microprocessor receives an interrupt and its indication is provided to the interrupt status register. Such interrupts are masked by setting the appropriate bits in the control register, i.e., "triggered" to a diagnostic software check.

When NLI 50 loses transmission synchronization with its receive network link, its indication is provided in the interrupt status register and the circuit's microprocessor is interrupted. Master 5
For NLI circuits captured as 0A, the interrupt status register indication is at the receive link out-of-sync bit position,
NLI circuit 5 captured as slave unit 50B
For 0, an interrupt is indicated in the master clock out-of-sync bit. Further, in the NLI circuit 50 operating as the master unit 50A, the internal counter is
It is checked if stepped by a sync signal provided via sync input pin 97. When such synchronization is lost, the master clock out-of-sync bit in the interrupt status register, Figure 18, is set and the microprocessor of the circuit is interrupted. Consistent with the handling of other error interrupts, these types can be masked, or "triggered" by diagnostic software checks, by setting the appropriate bits in the control register.

NLI circuit 50 also provides a background test feature for some system functions. Each NLI circuit 50 has a register that allows a known PCM and signal pattern to be inserted in place of the data of one channel output via the transmission network link. The microprocessor includes an 8-bit PCM and / or 4-bit A, B, C, in the transmit insert data register, FIGS. 26 and 41.
The D signal value can be specified, and the channel number can be specified in the transmission insertion address register, FIG. 25. By setting the enable PCM insertion bit in the control register, FIG. 16, the microprocessor can replace the A, B, C, D signal values during the system-defined superframe timing of SFSS for that channel. In this way, the NSC 36 can send a known value over the link over the link to the switching complex and the signaling circuitry of the TSI 34 where it can take action to check its operation. Insertion of PCM can be done without signaling the insertion and vice versa. Similarly, the NLI 50 has an extract data register for latching the PCM and signaling data for a given channel when received from the network link 47.
39 and 40, and address register, 24th
There is also a figure. The insert and extract registers can be used individually or in pairs to monitor various system functions.

The NLI circuit 50 has a 10 mS output pin that provides each card with a real-time signal to interrupt its processor. This 10 mS signal is sent to the NLI circuit 5
It is derived from the 12.352 MHz clock input to 0. This interrupt is a clear timer / NM of the NLI circuit 50.
The I register must be read and acknowledged in FIG. 43, after which the output signal is deactivated until the next period elapses.

The NLI circuit 50 receives a DSP signal every time the A port signal bit is received on all channels via the network link.
The circuit 42 has an output pin which provides the interrupt signal of the microprocessor. This 1.5 mS signal is derived from the 12.352 MHz clock input to NLI circuit 50 according to the system-defined superframe structure. This interrupt must read and acknowledge the clear time / NMI register of the NLI circuit 50, FIG. 43, after which the output signal will pause until the next period elapses.

Four pins are provided in the NLI circuit 50 to handle a 56 or 64 Kbps data link. Two
Two pins represent clock signals generated by the NLI circuit 56 and used to transfer 56 or 64 Kbps data to the NLI circuit. The two clock signals are not in phase. The remaining two pins are 56 or 64 Kb
This is a path for ps data I / O. In the PRI circuit 40, these pins are used to transfer data between the NLI circuit 50 and the serial communication controller (SCC), which are connected to the circuit's microprocessor.
In this way, the processor can receive data from one channel in NLI circuit 50, and can similarly generate data for that channel. 56 or 64K that the processor can interact with
The bps channel is one that arrives / ships over a T1 line connected to the circuit. 56 or 64 Kbps by enabling the data link operation and setting the appropriate bits in the control register, FIG.
You must specify the action.

Each NLI circuit 50 is provided with a DTAK output pin 102, FIG. 8, for use in handshaking during data transfer by the terminal circuit microprocessor.

The registers that make up the microprocessor interface to the NLI are described below and in Section 14.
It is shown in the figure and next. The address of each register is given along with its name. These addresses contain 5 bits, the designation of which is from A5-A1. NLI circuit 50
In a 6800 microprocessor-based circuit that uses a .. In addition to the address given to each register, there is a read only (RO) designation given to the appropriate register. Any register without RO designation can be read / written.

Control MS register of NLI circuit 50, first
In FIG. 4, no receive link out-of-sync interrupt can occur for an NLI circuit that has a slave designation on its master / slave pin 80, and only an outgoing data parity error can capture NLI circuit 50 in mode 0. ,
It is the only mode of operation with parity flowing into the outgoing data interface 82.

Control SS register of NLI circuit 50, first
In Figure 5, even if a given interrupt is masked,
The status register, Figure 18, continues to give an indication that a given event has occurred. The set bits in this register only act as interrupt output pins.

In the control TS register, FIG. 16,
The IDE bit is cleared whenever the device goes out of sync, and the IDE bit must be set after the device has acquired sync regardless of the mode of operation. The 3 bits are always read as 0 and in any case one should not expect to read back exactly from this register what was written to it. If mode 0, SUFR
The M bit must be set to 333 Hz synchronous operation selection.

In the control LS register, FIG. 17,
The receive FIFO lock is never activated and is never set for a device that has a master designation through its master / slave pin 80. The 5 bits are always read as 0 and in any case one should not expect to read back exactly from this register what was written to it.

In the interrupt status register of FIG. 18, there is no receive link out-of-sync interrupt for a device having a slave designation through its master / slave pin 80. Also, an output data parity error interrupt does not occur for a device having a mode designation other than 0.

In the position register of FIG. 19, 5 to 7
The bits are always read as 0 and in any case one must expect to read back exactly from this register what was written to it.

NLI circuit 50 designated as master
In the transmission link MS counter load register shown in FIG. 20, the value to be given to this register is B5H. For the NLI circuit 50B designated as a slave, the value to be given to this register is 08H.

In the transmission link LS counter load register shown in FIG. 21 of the device designated as the master circuit 50A, the value to be given to the register is F6H. The value to be given to the register for the NLI circuit 50B designated as the slave is DAH.

NLI circuit 50 designated as master
In the reception link MS counter load register shown in FIG. 22, the value to be given to this register is 00H. Further, for the NLI circuit 50 device designated as the slave, the value to be given to this register is BDH.

NLI circuit 50 designated as master
In the reception link LS counter load register shown in FIG. 23, the value to be given to this register is 02H. For a device designated as a slave, the value to give to this register is C8H.

In the extract address register of FIG. 24, bits 5-7 are always read as 0 and in any case one should not expect to read back exactly from this register what was written to it. In the insert address register shown in FIG. 25, bits 5-7 are always read as 0 and in any case one should not expect to read back exactly what was written to it.

In the insert MS data register shown in FIG. 26, bits 4-7 are always read as 0 and in any case one should not expect to read back exactly from this register and what was written. .

In the 56/64 Kbps data link address register of FIG. 27, bits 5-7 are always read as 0 and in any case expect to read back exactly from this register what was written to it. Don't

The sequence of operations performed during device initialization is as follows. 1. All interrupts are masked by writing FFh to the control SS register. 2. Appropriate data (described above) is written to the transmit / receive link counter load register of FIGS. 20 and 23. 3. Reads the interrupt status register and NLI50 becomes "synchronous"
Guarantee that you are giving the display. Keep looping until the device produces these displays. 4. Write the appropriate value (specific card) to the SUFRM bit of the control TS register of FIG. 16 and the position register of FIG. 5. The IDE bit of the control TS register is enabled regardless of the PCM / system bit I / O used. 6. Write the specific card data to the appropriate registers (which can be control TS, control LS, transmit link signal control, receive link signal control, and / or 56/64 Kbps data link address registers). 7. Enable the desired interrupt in the control SS register of FIG. While the embodiments have been disclosed in detail, it will be appreciated that various modifications can be made within the spirit and scope of the invention as claimed.

[Brief description of drawings]

FIG. 1A is a comparative waveform table of different prior art encoding methods, including the known self-clocking encoding method described above in the Prior Art section. FIG. 1B is a binary code of the waveform of FIG. 1A represented using the binary encoding method of the present invention. FIG. 2 is a waveform table that more clearly illustrates the preferred ternary coding of the present invention.

FIG. 2 is a block diagram of a telephone network adopting the present invention. FIG. 4A is a block diagram of a digital port circuit of the network of FIG. 3 using the network link interface circuit of the present invention as a network terminator.

FIG. 4B is a block diagram of the NSC functional block of FIG. 3 using the network link interface circuit of the present invention as a control unit.

4 is a simplified version of the network link interface circuit operating as a control unit in the NSC circuit of FIG. 4B and the network link interface circuit functioning as a network terminator in the digital port circuit of FIG. 4A. It is a block diagram.

5A is a circuit diagram of a transmission link encoder section of the network terminating device of FIG.

6B is a circuit diagram of a reception link unit of the network terminating device of FIG.

FIG. 6C is a comparison waveform at different designated points of the receive link section of FIGS. 6A and 6B.

Figure 6D is a continuation of Figure 6C.

FIG. 9E is a continuation of FIG. 6D.

Figure 6F is a continuation of Figure 6E.

11A is a circuit portion of a transmission link encoder portion of the control unit of FIG.

12 is a circuit portion of a receiver link decoder portion of the control unit shown in FIG.

FIG. 13C is a comparison waveform at various designated points within the receiver decoder section of FIG. 7B. FIG. 7D is a comparison waveform at different designated points in the transmit link encoder section of FIG. 7A and the receive link decoder of FIG. 7B.

FIG. 8 is a block diagram of the network link interface integrated circuit of FIGS. 4A and 4B showing various inputs and outputs of FIGS. 4A and 4B.

15 is a block diagram of a system configuration in which the network link interface circuit of FIG. 8 is variously adopted. FIG. 10 is a signal to various mode pins and master / slave pins of the network link interface circuit of FIG. 8 necessary to achieve the different modes of operation required for the different applications shown in FIG.

FIG. 16 is another functional block diagram of a network link interface circuit showing various interfaces with other elements of the network. FIG. 12 is a preferred network link format employing the present invention. FIG. 13 shows a message format adopting the present invention.

FIGS. 14-16 are the contents of various registers of the network link interface circuit of FIG.

18 to 19 are the contents of various registers of the network link interface circuit of FIG.

20 to 22 are the contents of various registers of the network link interface circuit of FIG.

20. FIG. 20 shows the contents of various registers of the network link interface circuit of FIG.

21 to 28 are the contents of various registers of the network link interface circuit of FIG.

22 to 31 are the contents of various registers of the network link interface circuit of FIG.

FIGS. 23-35 are the contents of various registers of the network link interface circuit of FIG.

24. FIG. 24 is the contents of various registers of the network link interface circuit of FIG.

25. FIGS. 40-43 are the contents of various registers of the network link interface circuit of FIG.

[Explanation of symbols]

 20 logic 0 path 22 logic 1 path 24 sync pulse 26 full clock period 27 network termination subsystem 29 network subsystem 30 SBX bus 32 system clock (CLK) 34 time slot interchanger (TSI) 36 network self controller (NSC) 37 digital Audio source (DAS) 38 Basic rate line (BRL) 40 Primary rate interface (PRI) 42 DSI port 44 Digital signal processing circuit (DSP) 46 DS1 transmission link 47 Wire link 50 Network link interface (NLI) 50A Master unit 50B Slave Unit 51 Line Interface 52 DS1 Transceiver 53 Elastic Buffer 54 DPC Microprocessor 56 RAM 57 Serial Communication Controller 57A data link 57B data link 58 microprocessor 59 EPROM 60 DRAM 61 protection logic 62 multi-function peripheral device 63 fixed module counter 64 fixed module counter 65 XMT counter 66 XMT counter 67 multiplexer 68 line encoder 69 delay network 70 two-divided circuit 71 Phase synchronization circuit 72 Line decoder and demultiplexer 73 Phase synchronization acquisition circuit 74 Network link transmission multiplexer 75 NSC latch 76 Demultiplexer 77 Edge synchronization check circuit 80 NLI master / slave pin 81 NLI mode selection pin 82 Transmission link interface 84 〃 86 Receive link interface 88 Input data interface 90 Microprocessor interface 91 FIFO 92 Counter / Timer Circuit 93 8KHz Transmit Sync Pin 94 333KHz Receive Sync Output Pin 95 1.536Hz Transmit Clock Pin 97 Pin 100 8KHz Receive Sync Pin 101 Network Link 102 Network Link 104 Data Output 105 Toggle Flip Flop

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[Procedure amendment]

[Submission date] November 18, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (46)

[Claims] 1. A switching interface system for communication between information sources in a telecommunications network of transmitting and receiving information sources,
The exchange interface scheme is a control unit connected to some of the sources, means for encoding the information from the sources into a serial, pulse width binary format, and a pulse width for the encoded information. A network terminating device connected to the control unit and other information sources, including means for serially transmitting binary coded pulses at a predetermined transmission bit rate, wherein the serially transmitted pulse width binary code Means for extracting a clock signal therefrom in response to the clock pulse, and for synchronously decoding the pulse width binary coded pulse serially transmitted in response to the clock signal, and for connecting the other terminal connected to the network terminating device. A switching interface system comprising: the network terminating device including means for providing to an information source. 2. The switching interface system according to claim 1, wherein the network terminator encodes the data from the information source connected thereto into a pulse format, and the coded data in response to a clock signal. A switching interface method comprising means for transmitting to the control unit in frequency synchronization with the transmission bit rate. 3. The switching interface method according to claim 1, wherein the extracted clock signal has a frequency substantially equal to a transmission bit rate frequency. 4. The switching interface system according to claim 3, wherein the control unit has a primary clock having a frequency that is a binary power of a transmission bit rate, and the network terminator has a frequency of the primary clock. A switched interface scheme having means for generating clock signals having equal bit rates. 5. The switching interface system according to claim 1, wherein the control unit decodes data from the network terminating device, and a transmission bit rate of a pulse width binary coded pulse transmitted to the decoder. A switching interface system comprising means for maintaining frequency synchronization of the. 6. The switching interface method according to claim 5, wherein said control unit includes means for maintaining phase synchronization between said decoder and a pulse width binary coded pulse to be transmitted. 7. The switching interface system according to claim 6, wherein said phase synchronization means includes means for matching the time when a data bit enters the coding means with the time when the bit leaves the decoding means. 8. The switching interface system according to claim 1, wherein the control unit stores the information in a logical 1
A switching interface scheme including means for encoding a binary pulse width modulation format in which each state and logic zero state is represented by two pulses of different selected width. 9. The switching interface method according to claim 8, wherein leading edges of the two pulses having different selection widths simultaneously occur during a bit interval. 10. The switching interface method according to claim 9, wherein the leading edge transition is a positive transition. 11. The switching interface method according to claim 8, wherein the two pulses having different widths generate a pulse transition within each data bit interval. 12. The switching interface method according to claim 11, wherein the pulse transition is a positive transition. 13. A telecommunications network as a transmission / reception information source,
In the exchange interface method for communication between information sources, the exchange interface method is a control unit connected to some of the information sources and encodes information from the information sources into a serial, pulse width binary format. And a network unit connected to the other information source, the control unit including a pulse width binary coded pulse of the coded information and a means for serially transmitting the coded pulse at a predetermined transmission bit rate. Means for extracting a clock signal therefrom in response to the serially transmitted pulse width binary coded pulse; synchronously decoding the serially transmitted pulse width binary coded pulse in response to the clock signal; Said network terminator including means for providing to said other information source connected to the terminator. Switching interface method. 14. The switching interface method according to claim 13, wherein the multiple is 4. 15. The switching interface system according to claim 13, wherein said clock signal extraction means is a phase synchronization circuit having an input / output, and means for delaying the leading edge of the width modulation pulse to generate a delay pulse width modulation pulse. And a means for applying a corresponding delayed intermediate signal to the input of the phase-locked loop circuit in response to the delay-width modulated pulse and outputting the clock signal at a predetermined multiple of the transmission bit rate from the phase-locked loop circuit. Interface method. 16. A binary counter according to claim 15, wherein said delayed intermediate signal applying means generates an intermediate signal having a frequency which is a predetermined fraction of the transmission bit rate and interfaces with the input of the phase locked loop. Switched interface method, including. 17. A system according to claim 1, wherein said control unit periodically inserts a phase synchronization pulse into said serial transmission pulse width binary coded pulse to provide phase synchronization information to a network terminator. Switched interface method, including. 18. The switching interface system according to claim 17, wherein the control unit generates a phase reference signal in response to an external clock, and the serial transmission pulse width in response to the phase reference signal generation means. Means for inserting said phase-locked pulse into a binary coded pulse stream. 19. The switching interface scheme of claim 17, wherein the pulse width binary coded pulse has a leading edge transition of a selected transition sense and the synchronization pulse is the selected transition sense of a binary coded pulse. Switched interface method with the same transition sense as. 20. The switching interface method of claim 19, wherein the transition sense is a positive transition from a relatively low voltage to a relatively high voltage. 21. The switching interface system according to claim 17, wherein said network terminator is responsive to said phase synchronization pulse and phase-synchronized with said pulse width binary coded data pulse at said predetermined transmission bit rate. A switched interface method that includes means for sending data to the control unit. 22. In telecommunication of a transmission / reception information source, in the exchange interface method for communication between the information sources,
The exchange interface method is a control unit connected to some of the information sources, means for encoding information from the information sources into a serial, pulse width binary format, and a pulse width 2 of the encoded information. A means for serially transmitting a binary coded pulse at a predetermined transmission bit rate; and a phase synchronization pulse is periodically inserted into the serially transmitted pulse width binary coded pulse to transmit phase synchronization information to a network terminator. Means for providing, and a network terminator connected to the other information source, the means for extracting a clock signal therefrom in response to a serially transmitted pulse width binary coded pulse. , A pulse width binary coded pulse serially transmitted in response to the clock signal is synchronously decoded and connected to a network terminating device. Means for providing to said other information source followed, and means for transmitting data to said control unit at said predetermined transmission bit rate in phase synchronization with said pulse width binary coded data pulse in response to said phase pulse. And a phase synchronization acquisition circuit that generates a synchronization control signal, and a control unit that controls the synchronous transmission of data to the control unit in response to the synchronization control signal and synchronizes with the generated synchronization pulse. And a network terminating device including the data transmitting means including means for maintaining data transmission. 23. In a telecommunication network of a transmission / reception information source,
In the exchange interface method for communication between information sources, the interface method is a control unit connected to some of the information sources and encodes information from the information sources into a serial, pulse width binary format. Means for serially transmitting a pulse width binary coded pulse of the coded information at a predetermined transmission bit rate; and periodically inserting a phase synchronization pulse into the serially transmitted pulse width binary coded pulse. A network terminating device connected to said control unit, and means for providing thereto phase synchronization information, and in response to a serially transmitted pulse width binary coded pulse. Means for extracting a clock signal therefrom, and a pulse width binary serially transmitted in response to said clock signal Means for synchronously encoding the coded pulse and providing it to said other source connected to a network terminator; and in response to said phase synchronizing pulse in phase synchronization with said pulse width binary coded data pulse Means for transmitting data to the control unit at a predetermined transmission bit rate; and the control unit at the predetermined transmission bit rate in phase synchronization with the pulse width binary coded data pulse in response to the phase synchronization pulse. Means for transmitting data to the clock signal, means for identifying a time division multiplexed channel of a telecommunications network in response to the counter and the counter for triggering the clock signal, and the means for responding to the synchronization control signal The data including means for maintaining phase synchronization between the counter and the phase synchronization pulse of the control unit. A switching interface system comprising the network terminating device, including: 24. The switching interface system according to claim 23, wherein the control unit has one microprocessor, the network terminator has another microprocessor, and One is dedicated to sending messages from the one microprocessor of the control unit to the other microprocessor of the network terminator, a switched interface scheme. 25. In a telecommunication network as a transmission / reception information source,
In the exchange interface method for communication between the information sources, the exchange interface method is a control unit connected to some of the information sources, and outputs information from the information sources in a series of serial pulse width binary formats. Means for coding as a data pulse, means for generating a pulse width coded synchronization pulse, and transmitting the series of data pulses and pulse width coded synchronization pulse together at a predetermined bit rate on a time division multiplexed basis Means for deriving a clock signal in response to said pulse width coded synchronization pulse, said network unit being connected to said control unit and to said other information source, In response, the series of pulse width coded data pulses are synchronously coded and the network termination equipment is Means for connecting to the other information source connected to the network, and means for controlling the synchronization between the synchronous decoding means of the network terminator and the encoding means of the control means in response to the pulse width coded synchronization pulse. A switching interface system comprising: the network terminating device including; 26. The switching interface method according to claim 25, wherein the data pulse has a predetermined pulse width different from each other, and the synchronization pulse has a pulse width different from a predetermined pulse width of the data pulse. . 27. The switching interface system of claim 25, wherein the network terminator encodes information from the other sources as a series of uniform binary data pulses, and uniform binary data. Means for generating a uniform synchronization pulse having a pulse width substantially the same as the pulse in synchronization with the pulse width coded pulse; and the uniform synchronization pulse with the uniform binary data pulse in a series of uniform pulses. A switching interface method, including means for transmitting as pulses. 28. The switched interface system according to claim 27, wherein said control unit includes means for decoding said binary data pulse from a termination device in response to said uniform synchronization pulse. 29. The switching interface scheme of claim 28, wherein the control unit is responsive to the uniform synchronization pulse to determine if it is in phase synchronization with a pulse width coded synchronization pulse transmission of the control unit. A switching interface method, including means for doing so. 30. The switching interface scheme of claim 27, wherein at least some predetermined pulses of the uniform synchronization pulse received by the control unit are pulse width coded synchronization pulses transmitted from the control unit. A switched interface scheme having a binary logic state opposite to that of. 31. The switching interface scheme of claim 25, wherein the series of data pulses is binary in pulse width by the encoding means such that a logic 1 data pulse has a different pulse width than a logic 0 data pulse. A switching interface scheme, wherein the synchronizing pulse generating means is coded to generate the synchronizing pulse having a pulse width different from both the logic 0 data pulse and the logic 1 data pulse. 32. The switching interface system according to claim 25, wherein the predetermined bit rate at which the data pulses of the synchronization pulse are transmitted is a substantially uniform rate, and the clock signal in the network terminating device is uniform. A switched interface scheme that is generated at a given uniform frequency that is a given multiple of the desired bit rate. 33. The switching interface system according to claim 25, wherein said network terminator is transmitted from another source connected thereto to said control unit in response to said synchronizing pulse and said data. A switching interface scheme having means for transmitting data to a control unit, including means for maintaining phase synchronization with pulse width coded sync pulses from. 34. A telecommunications network for transmitting and receiving information sources,
In the exchange interface method for communication between information sources, the exchange interface method is a control unit connected to some of the information sources, and means for encoding information from the information sources as a series of data pulses. A control unit including means for generating a pulse width coded sync pulse; means for transmitting the series of data pulses and the pulse width coded sync pulse together at a predetermined bit rate on a time division multiplexed basis; A network terminating device connected to said information source of at least means for deriving a clock signal in response to said pulse width coded synchronization pulse, and for synchronously decoding a series of data pulses in response to said clock signal. , Means for connecting to said other source to which the network terminator is connected, and means for connecting to it. Data from another source to the control unit, including means for maintaining phase synchronization of the data transmitted to the control unit in response to the synchronization pulse and the pulse width coded synchronization pulse from the control unit. A phase synchronization acquisition circuit for transmitting a synchronization control signal for controlling the phase synchronization of the encoding means in response to the synchronization pulse received by the network terminating device; and the pulse width encoding synchronization A switching interface system comprising: the network terminator including: the data transmitting means, including means for controlling synchronization between the synchronous decoding means of the network terminating equipment and the encoding means of the control unit in response to the pulse. 35. The switching interface system according to claim 34, wherein the phase synchronization acquisition circuit is associated with the decoding means and generates a synchronization pulse reception signal in response to reception of the synchronization pulse from the control unit. Means, a counter of the encoding means for counting clock pulses in phase synchronization with a synchronization pulse in response to the synchronization control signal, and generating the synchronization control signal in response to the counter,
Means for indicating when the next synchronization pulse should be received when the counter is in phase synchronization with the synchronization pulse; and the synchronization pulse reception signal and the synchronization control signal which have not been generated within a predetermined time interval from each other. A switching interface method, including means for generating an out-of-sync signal in response to. 36. The switching interface system of claim 35, including means for resynchronizing the counter in response to the out-of-sync signal. 37. The switching interface system of claim 34, wherein said network terminator includes means for generating an out-of-sync indication in response to said out-of-sync signal. 38. In a switching interface method for communication between information sources in a telecommunications network of information sources, the switching interface method is a control unit connected to some of the information sources, the series of data pulses. Means for binary coding the information from the device, means for decoding the information received as a series of data pulses, means for generating a series of synchronization pulses having a predetermined width different from the data pulses, said coding A network terminating device connected to said control unit and to said other information source, comprising means for transmitting information and said synchronizing pulse together at a predetermined bit rate, said network terminating device being at least responsive to said synchronizing pulse. And a means for deriving a clock signal from the other information source in response to the clock signal. And means for controlling the phase synchronization between the encoding and transmitting means of the network terminator and the decoding means of the control unit in response to the synchronization pulse. A switching interface system comprising the network terminating device. 39. The switching interface system according to claim 38, wherein said clock signal extracting means includes means for extracting said clock pulse in response to a predetermined bit rate of a series of data pulses. 40. In a switching interface method for communication between information sources in a telecommunication network of information sources, said switching interface method is a control unit connected to some of said information sources, wherein a series of data pulses Means for encoding information from, a means for decoding information received as a series of data pulses, a means for generating a synchronization pulse of a predetermined width different from the data pulses, the coded information and the synchronization Means for transmitting pulses together at a predetermined bit rate, said control unit, and a network terminating device connected to said other source of information, said network terminating device providing a clock signal at least in response to said synchronizing pulse. Means for deriving and encoding information from one of the other sources in response to the clock signal. And a means for controlling the phase synchronization between the encoding and transmitting means of the network terminator and the decoding means of the control unit in response to the synchronization pulse, and a synchronization pulse from the control unit. Responsive to detecting phase desynchronization with the control unit, and responsive to the desynchronization detecting means to change the timing of the encoding and transmitting means to eliminate the desynchronized state,
A switching interface system comprising the network terminating device. 41. A switching interface method for communication between information sources in a telecommunication network of an information source, wherein the switching interface method is a control unit connected to some of the information sources, and a series of data pulses. Means for encoding the information from, a means for decoding the information received as a series of data pulses, a means for generating a synchronization pulse of a predetermined width different from the data pulses, the coded information and the synchronization Means for transmitting pulses together at a predetermined bit rate, said network unit connected to said control unit and to said other information source, said clock terminating means being at least responsive to said synchronizing pulse. And means for synchronously encoding information from one of the other sources in response to the clock signal. Means for transmitting to the control unit, means for controlling the phase synchronization between the coding and transmitting means of the network terminator and the decoding means of the control unit in response to the synchronization pulse, and the synchronization pulse from the control unit A switching interface system comprising a network terminating device, including means for transmitting a phase desynchronization indication to the control unit in response to. 42. A method of communication in a synchronous digital data communication network, the method comprising the following steps: in a controller circuit, a binary data pulse in a non-self clocking format in which the clock signal is not carried by a stream of binary data pulses. 2 receives a stream, converts a non-self clocking data stream into a corresponding self-clocking pulse-width-modulated binary data stream, sends the pulse-width binary-modulated data stream to an end device of the network, and the end device receives 2 Extracting a clock signal from the progressive pulse width modulated data stream and using the extracted clock signal to decode the transmitted pulse width modulated data stream into a binary data pulse stream in a non-self clocking format, Communication Law. 43. The method of claim 42, comprising transmitting the data stream from the terminating device to the controller circuit synchronously with transmitting the pulse width modulated data stream to the terminating device using the extracted clock signal. Communication law, including. 44. The method of claim 42, wherein the step of inserting a pulse width modulated synchronization pulse into the self-clocking pulse width modulated binary data stream and using the pulse width modulation synchronized pulse in the controller. Maintaining a phase synchronization of the communication between the circuit and the termination circuit. 45. The method of claim 42, wherein the transmitting step comprises the step of transmitting each pulse width modulated pulse at the beginning of each clock cycle. 46. A communication method in a synchronous digital data communication network, the communication method comprising the following steps: a binary data pulse in a non-self clocking format in which the clock signal is not carried by the binary data pulse stream in the controller circuit. Receive a stream, convert a non-self clocking data stream into a corresponding self-clocking pulse width modulated binary data stream, and convert the pulse width modulated data stream with a predetermined transition at a predetermined time during each clock cycle to the network. A clock signal is extracted from the pulse width modulated data stream transmitted to the terminating device (pulse transmission step) and received by the terminating device, and the pulse width modulated data stream transmitted using the extracted clock signal is converted into a non-self clocking format. Decoding to binary data pulse stream of, communication method consisting of: