JPH0769820B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for performing pipeline processing, and more particularly to a data processing device for performing memory indirect addressing and register indirect addressing at an address calculation stage. .

[Conventional technology]

As a method to increase the processing speed of the data processing device,
There is a pipeline processing method.

The pipeline processing method divides the instruction processing and executes a plurality of instructions simultaneously in the data processing device to increase the throughput and the apparent execution speed of one instruction. For example, in a data processing device configured such that one instruction is executed in a four-stage pipeline of instruction decoding, operand address calculation, operand fetch, and operation execution, a maximum of four instructions are simultaneously executed in each processing stage. . On the other hand, in a data processing device which processes one instruction at a time, it is not possible to proceed to the next instruction processing until all the processing of instruction decoding, operand address calculation, operand fetch, and operation execution are completed. So in this case,
A data processing device that performs pipeline processing can apparently have an instruction processing speed four times as high.

In order to increase the processing speed of the data processing device, it is necessary to improve the pipeline processing efficiency. In order to increase the efficiency of pipeline processing, it is necessary that the load on each stage of the pipeline is equal, that each stage process data in the same number of clock cycles, and the pipeline processing progresses one after another.

Factors that disturb the progress of continuous data processing in the pipeline include jump instructions, exceptions, interrupts, and conflicts between instructions in the pipeline. Here, one of the main conflicts in the pipeline is that the operand address calculation stage refers to a general-purpose register or memory written by the operation execution stage before the writing.

In order for the instruction to be executed correctly as programmed, the operand address calculation stage must refer to the general-purpose register or memory after the operation execution stage has finished writing to the general-purpose register or memory.

FIG. 4 is a circuit block diagram for explaining a conventional pipeline control mechanism. Reference numeral 41 is an instruction decoder which decodes an instruction and outputs a register write reservation signal for register write processing.
It outputs to the set input of the SR flip-flop 42, and outputs the memory write reservation signal to the set input of the SR flip-flop 43 for memory write processing. SR flip-flop 42,
The SR flip-flops 43 for the memory writing process are reset by the reset signal from the arithmetic processing unit 44.

FIG. 5 is a state diagram for explaining the transition of pipeline processing. 51 is an instruction decode stage, 52 is an address calculation stage, 53 is an operand fetch stage, 54 is an operation execution stage, and T1 ... T8 indicates a processing cycle, and I1 to I3 indicate instructions flowing in the pipeline.

Next, referring to FIG. 4, a conventional pipeline control method associated with writing to a register or memory will be described.

The instruction decoder 41 checks whether the input instruction writes data in a register or a memory in the arithmetic processing unit 44. Then, when writing to the memory, the memory write reservation signal is sent to the SR flip-flop 43 and set to "1".
Set to. The value of the SR flip-flop 43 is reset to "0" when the processing unit 44 finishes processing the instruction in which "1" is set, and then the instruction processing is started again.

Similar to memory writing, register writing is also reset when the register write reservation signal sets the SR flip-flop 42 and the arithmetic processing unit 44 completes the processing. The stage delay due to the pipeline control will be described with reference to FIG.

For example, if the instruction I1 makes a memory write reservation, the instruction I2 stops processing in the processing cycle T3, and the instruction I2 stops processing in the processing cycle T4.
Decoding cannot be executed until I1 writes data to memory. The stop signal is reset in processing cycle T4,
In the processing cycle T5, the instruction I2 starts processing again. As a result, instruction I2 is delayed by two cycles. The same delay occurs in the case of register write reservation.

Therefore, a proposal has already been made to improve this problem associated with the register conflict as described above, for example, as shown in Japanese Patent Application No. 62-144394.

[Problems to be Solved by the Invention]

However, in the conventional method, when the previous instruction writes the value to the memory, the operand address calculation processing is stopped until the instruction after the previous instruction finishes the memory writing of the previous instruction, and the pipeline processing speed is significantly reduced. There was a problem of inviting.

The present invention has been made to solve the above problems, and by checking the memory write state of an instruction and sequentially transferring the memory write reservation information to each stage, the subsequent instruction accompanying the memory write of the preceding instruction An object of the present invention is to obtain a data processing device capable of efficiently executing pipeline processing by greatly reducing the frequency of processing suspension caused by operand address calculation processing.

[Means for Solving the Problems]

A data processing apparatus according to the present invention includes a pipeline processing mechanism including a first pipeline stage for calculating an address of an operand and a second pipeline stage for writing an operand of an operation result, and an operation to a memory space. An operand write reservation unit that reserves the writing of an operand in the memory space and an output of the operand write reservation unit are held when the process related to the first instruction that writes the resulting operand is executed in the first pipeline stage. One or a plurality of reservation latch means, a reservation latch clear means for clearing the contents of the one or a plurality of reservation latch means when processing the first instruction in the second pipeline stage; Access memory space for operand address calculation in 1 pipeline stage That when executing the processing for the second instruction, which is constituted from an operand address calculation inhibition means for inhibiting the address calculation of an operand in the first pipeline stage based on the contents of the reservation latch.

In addition, a 1-bit register circuit having an input data signal, an input enable signal, a clear signal, and an output signal
Flag information holding unit, a second flag information holding unit which is a 1-bit register circuit having an input data signal, an input enable signal, a clear signal, and an output signal, a third pipeline stage, and a fourth pipeline. A flag information holding unit in which a first flag information holding unit and a second flag information holding unit are connected in series corresponding to a stage, and logic of each output of the first flag information holding unit and the second flag information holding unit. Flag information holding state detecting means for detecting the flag information holding state in the flag information holding means while taking a sum;
The first flag information holding unit is set when the first instruction is processed in the pipeline stage, and the processing of the first instruction is performed from the processing in the third pipeline stage to the processing in the fourth pipeline stage. When moving to, the contents of the first flag information holding unit is transferred to the second flag information holding unit,
Further, by clearing the first flag information holding unit, the information is sequentially moved in the flag information holding unit, and the memory space is accessed for operand address calculation according to the output of the flag information holding state detecting unit. Pipeline control means for controlling the processing relating to the second instruction.

[Action]

According to the present invention, when the first instruction for writing the operand of the operation result to the memory space, for example, the processing related to the memory write instruction is performed in the first pipeline stage, the operand write reservation means is to write the operand in the memory space. A second instruction that reserves and when the processing related to the first instruction is performed in the second pipeline stage, the content of the reserved latch means is cleared by the reserved latch clear means, and the memory space is accessed for operand address calculation. For example, when processing relating to an instruction for memory access by address calculation is performed in the first pipeline stage, the operand address calculation suppression mechanism delays and executes the address calculation of the operand.

Further, the pipeline control means sets the first flag information holding unit when processing the first instruction in the third pipeline stage, for example, an instruction for writing a memory and another instruction, and processes the first instruction. Transfers from the processing in the third pipeline stage to the processing in the fourth pipeline stage, the contents of the first flag information holding unit are transferred to the second flag information holding unit, and the first flag By clearing the information holding unit, the information is sequentially moved in the flag information holding unit. Further, the pipeline control means controls the processing execution relating to the second instruction, for example, the instruction for memory access by address calculation, according to the output of the flag information holding state detection means.

〔Example〕

FIG. 1 is a block diagram for explaining the configuration of a data processing device showing an embodiment of the present invention, and shows a case of a five-stage pipeline configuration, for example.

In this figure, reference numeral 1 denotes an instruction fetch stage (IF stage) which performs instruction prefetch processing. A decode stage (D stage) 2 decodes an instruction. Three
In the operand address calculation stage (A stage), which is the first pipeline stage, performs operand address calculation. An operand fetch stage (F stage) 4 is a third pipeline stage, which performs micro ROM access and operand fetch. An execution stage (E stage) 5 is the second or fourth pipeline stage, which executes instructions.

The IF stage 1 passes the instruction code to the D stage 2, the D stage 2 to the A stage 3 receives information about the operation and the address calculation of the operand, and the A stage 3 to the F stage 4 enters the microprogram routine. Addresses, parameter information to the microprogram, operand addresses, and access method information are passed, and operation control information and operand and operand address information are passed from the F stage 4 to the E stage 5.

An instruction decoder 6 decodes the instruction output from the IF stage 1 into information related to operation and information related to operand address calculation. Reference numeral 7 is an instruction decoder, and 8 is a decoder. The instruction decoder 7 further decodes the information related to the operation, judges whether or not to write the register or the memory in the E stage 5, and judges the decoding result by the register writing reservation circuit 9 or the memory writing. Make a reservation in the reservation circuit 10. The decoder 8 further decodes the information on the operand and outputs the decoding result to the register write reservation circuit 9.

Reference numeral 11 is a register write reservation flag circuit (provided in the F stage 4), which is reserved in the register write reservation circuit 9 and is based on a control signal output from the pipeline control circuit 15 (details will be described later). Holds register write reservation information transferred from.

Reference numeral 12 is a memory write reservation flag circuit (provided in the F stage 4), which is reserved in the memory write reservation circuit 10 and is based on a control signal (details will be described later) output from the pipeline control circuit 15. Holds memory write reservation information transferred from.

Reference numeral 13 is a register write reservation flag circuit (provided in the E stage 5), which is held in the register write reservation flag circuit 11 and is based on a control signal (details will be described later) output from the pipeline control circuit 15 It holds the register write reservation information transferred from the circuit 11.

Reference numeral 14 is a memory write reservation flag circuit (provided in the E stage 5), which is held in the memory write reservation flag circuit 12 and which is based on a control signal (details will be described later) output from the pipeline control circuit 15 It holds the register write reservation information transferred from the circuit 12.

It should be noted that, when performing the processing related to the first instruction for writing the operand of the operation result in the memory space in the first pipeline stage (A stage 3), writing the operand in the memory space is performed by the operand write reservation means (memory write reservation). Circuit 10) and when the processing related to the first instruction is completed in the second pipeline stage (E stage 5), the reservation latch clear means (pipeline control circuit)
(15 also serves as) to clear the contents of the reservation latch means (memory write reservation flag circuit 14) and perform the processing related to the second instruction for accessing the memory space for the operand address calculation in the first pipeline stage. ,
The operand address calculation suppression mechanism (also used by the pipeline control circuit 15) delays and executes the operand address calculation.

The pipeline control operation associated with a conflict between instructions in the pipeline will be described below.

The instruction processed in the data processor is passed from the IF stage 1 to the D stage 2, decoded by the instruction decoder 6 and the information about the operation and the information about the operand address calculation are passed to the A stage 3. In the A stage 3, the operand address is calculated based on the information related to the operand address calculation, and the information related to the operation is further decoded by the instruction decoder 7 and it is determined in the E stage 5 whether to write it in the register or the memory. The decoding result related to the writing is set in the register writing reservation circuit 9 and the memory writing reservation circuit 10. The register write reservation circuit 9 has as many reservation circuits as the number of registers and is reserved by the output of the instruction decoder 7 and the output of the decoder 8 for register designation. The memory write reservation flag is only one regardless of the address and is reserved by the output of the instruction decoder 7.

When one instruction has a plurality of operands, one instruction is divided into a plurality of processing units and decoded, and the write reservation information is accumulated by repeated write reservations.

It is described in detail in Japanese Patent Application No. 61-236456 that such one instruction is divided into a plurality of processing units and processed.

When the A stage processing of one instruction is completed, the write reservation information is transferred to the F stage 4 and held in the register write reservation flag circuit 11 or the memory write reservation flag circuit 12. E stage 5 upon completion of F stage processing of instruction
The write reservation information is transferred to. The write reservation information is held by the flag circuit of the stage where the write-reserved instruction is processed, and the flag circuit that has transferred the write reservation information clears the held write reservation information.
When the processing of the instruction reserved for writing in the E stage 5 is completed, the register write reservation flag circuit 13 or the memory write reservation flag circuit 14 is cleared. The instruction that refers to the memory for the memory indirect addressing in the operand address calculation stops the processing if at least one of the memory write reservation flag circuits 12 and 14 is set in the A stage 3, and the memory write reservation flag circuit 12 and 14 Wait until all 14 are reset.

Similarly, an instruction that refers to a register in operand address calculation in the A stage 3 stops the processing if at least one of the register write reservation flag circuits 11 and 13 corresponding to the referred register is set, and the register write reservation is performed. Wait for the flag circuits 11 and 13 to be reset.

In this control method, since the write reservation is made in the A stage 3, the operand write reservation of the register and the memory used for the operand address calculation is made first and the conflict does not occur by itself. All of the transfer of the write reservation information is generally performed by the pipeline control circuit 15
(Details will be described later).

Next, the write reservation information transfer process in the data processing device shown in FIG. 1 will be further described with reference to FIGS. 2 and 3.

FIG. 2 is a configuration diagram for explaining an example of the write reservation information transfer circuit shown in FIG. 1. Reference numeral 21 is a memory write reservation latch, which is AND gates 21a, 21b, NOR gate 21c, and inverter.
The AND gate 21a is supplied with the non-overlapping two-phase clock φ2 and the memory write reservation signal 22 from the instruction decoder 7 and is output to the R register 23 of the F stage 4. The R register 23 has a master-slave configuration and includes transmission gates 23a and 23b and an inverter 23.
c, NOR gate 23d, etc.
The write reservation information is transferred to the register 24. Reference numeral 25 is an E register, which receives write reservation information via the EI register 24. 26 is an OR gate, which is the output of the NOR gate 23d on the slave and master sides of the R register 23, the output of the EI register 24, and E
The OR (logical sum) of the outputs of the register 25 is taken (processing for detecting the setting state of the memory write reservation flag), and the write reservation signal is output to the AND gate 27 of the A stage 3. One of the AND gates 27 has a memory indirect reference signal 28
Is input and the AND output with the write reservation signal is output as the memory conflict signal 29. While the memory conflict signal 29 is "1", the operand address calculation in the A stage 3 is stopped. In this way, a 1-bit write reservation information transfer line is provided in each stage,
The memory or register write reservation information output from the instruction decoder 7 and the decoder 8 is sequentially transferred to the subsequent stage, and the E stage 5 is notified of the write reservation information. Then, the state of the write reservation information for each stage is detected by the OR logic, and the E stage 5 is set after the write reservation information for the instruction is being transferred to any stage.
Until the memory or register write by is completed.
Delay the start of operand address calculation in stage 3.

The memory write reservation latch 21 of the A stage 3 is an A stage end signal output from the pipeline control circuit 15.
The write reservation signal latched by the R register write signal 31 while being reset by the F register 4 is reset by the F stage 4
Transferred to.

Further, the R register 23 of the F stage 4 transfers the write reservation signal transferred to the master side to the slave side by the R register read signal 36 output from the pipeline control circuit 15, and the R register clear signal. Cleared by 32.

Further, the EI register 24 of the E stage 5 receives the write reservation signal from the R register 23 by the EI register write signal 33 output from the pipeline control circuit 15, and receives the write reservation signal from the EI register 24 by the E stage start signal 34. , E stage end signal 35 clears. In the figure, ~ indicates the output of each node.

FIG. 3 is a timing chart for explaining the transmission timing of each signal shown in FIG.

The memory write reservation signal 22 is output from the instruction decoder 7 and sets the memory write reservation latch 21. When one instruction performs a memory write for a plurality of operands, the memory write reservation signal 22 sets the memory write reservation latch 21 that number of times. Finally, when the address calculation processing of one instruction is completed, the memory write reservation information is sent to the E stage 4 by the A stage end signal 30 and the R register write signal 31, and the memory write reservation latch 21 is reset. Then, when the write reservation information is transferred to the F stage 4, the R register 23 which is the memory write reservation flag of the F stage 4 has a master-slave configuration, and the memory write reservation information of the next instruction is taken in and E
The memory write reservation information is transferred to the stage 5 at the same time. The memory write information is transferred to the slave by the R register read signal 36, and the master of the R register 23 is cleared when the memory write reservation information of the next instruction is not input.

When the processing of the instruction is completed in the F stage 4, the memory write reservation information is transferred to the E stage 5 by the EI register write signal 33 to the EI register 24, and the slave side of the R register 23 receives the input information from the master side of the R register 23. Will be overwritten.

When the EI register 24 receives the memory write reservation information from the F stage 4, the memory write reservation information input from the EI register 24 which is an input register is transferred to the E register 25 by the E stage start signal 34, and the next instruction If no reservation information is input, the EI register 24 is cleared. The memory write reservation information input to the E register 25 is cleared by the E stage end signal 35 at the end of the E stage processing.

As described above, the memory write reservation information is transferred in the pipeline in synchronization with the instruction transferred in the pipeline.
The memory is written in stage 5 and cleared when the instruction is completed.

The pipeline control circuit 15 serving as pipeline control means is the F stage 4 serving as the third pipeline stage.
The first flag information holding unit (memory write reservation flag circuit 12) is set when the first instruction is processed by, and the processing of the first instruction changes from the processing in the third pipeline stage to the fourth pipeline. When the process proceeds to the stage (E stage 5), the contents of the memory write reservation flag circuit 12 are changed to the second flag information holding unit (memory write reservation flag circuit).
14) and clear the memory write reservation flag circuit 12 to sequentially move the information in the flag information holding means. Further, the pipeline control circuit 15 controls the processing execution relating to the second instruction in the third pipeline stage according to the output of the flag information holding state detecting means (which is constituted by the OR gate 26 and the AND gate 27 etc.). .

The operation of FIG. 2 will be described below.

The output of the memory write reservation flag of each stage is ORed by the OR gate 26 and input to the AND gate 27. The memory indirect reference signal 28 is set to "1" in the instruction for memory reference in the A stage 3. Therefore, when even one instruction preceding the pipeline is reserved for memory writing, the memory conflict signal 29 becomes "1", and the A stage 3
Stops processing. Then, when all the instructions reserved for memory writing are processed in the E stage 5 and the memory conflict signal 29 becomes "0", the A stage 3 restarts the processing.

In the above embodiment, the transfer of the memory write reservation information has been described, but the register reservation information can be transferred by the same hardware. In particular, there are as many register reservation information as there are registers, and register reservation and register conflict signal generation are performed independently for each register. An instruction that refers to a register in the A stage 3 sets the register indirect reference signal 28 to "1", and if even one preceding instruction in the pipeline has reserved the corresponding register for writing, the register conflict signal is "1".
Then, the A stage 3 stops processing. Then, all the instructions reserved for register writing are processed in the E stage 5, and when the register conflict signal becomes "0", the A stage 3 restarts the processing.

When the E stage 5 executes a jump instruction or an interrupt, when a jump occurs, the instruction in the pipeline is canceled, and the IF stage 1 newly starts fetching the instruction at the jump destination. At this time, the register write reservation information and the memory write reservation information are cleared as in the case of the instruction in the pipeline. The register write reservation flag and the memory write reservation flag have reset inputs and are cleared when a jump occurs in the E stage 5.

At this time, the memory write reservation latch 21 uses the A stage end signal 30, the R register 23 uses the R register read signal 36 and the R register clear signal 32, the EI register 24 uses the E stage start signal 34, and the E register 25 uses the E register 25. It is cleared by the E stage end signal 35.

Further, in the above-described embodiment, a case has been described in which one system of memory write reservation and conflict check are performed for the entire memory space, but the memory reservation is divided into a plurality of spaces and the write reservation and conflict check are performed for each space. You may do it.

Furthermore, in the above-described embodiment, the memory write instruction performs the write reservation and the conflict check is performed. However, the conflict check may be performed depending on whether or not the instruction exists in the pipeline. In that case, the flag information holding circuit corresponding to the pipeline stage has the instruction presence information of that stage. If there is an instruction in the pipeline stage, the flag is 1, and if there is no instruction, the flag is "0". When an instruction is transferred in the pipeline, a flag indicating the existence of the instruction is transferred in the flag information holding circuit correspondingly. When the processing of that stage is completed, the flag information holding circuit sends a flag indicating the presence of an instruction to the next pipeline stage to clear the flag information. The outputs of the flag information holding circuits of the stages subsequent to the stage for calculating the address of the operand are ORed to detect whether or not there is an instruction in the stage subsequent to the address calculation stage. If there is even one instruction in the subsequent stage, the logical sum signal becomes "1", and if all the instructions in the subsequent stage disappear, the logical sum signal becomes "0". When an instruction processed in the address calculation stage performs address calculation that refers to memory, the address calculation is performed after checking the logical sum signal of the flag information holding circuit output and confirming that there is no instruction in the subsequent stage. . If the OR signal is "1", the instruction of the subsequent stage may write to the memory, so execution of the address calculation is stopped, all the instructions of the subsequent stage are completed, and the OR signal is "0". Then the address calculation is executed. It is also possible to perform the memory conflict check in this way.

〔The invention's effect〕

As described above, according to the present invention, the pipeline processing mechanism including the first pipeline stage for calculating the address of the operand and the second pipeline stage for writing the operand of the operation result, and the operation to the memory space An operand write reservation unit that reserves the writing of an operand in the memory space and an output of the operand write reservation unit are held when the process related to the first instruction that writes the resulting operand is executed in the first pipeline stage. One or more reservation latch means for
Reserved latch clearing means for clearing the contents of one or more reserved latching means when the processing related to the instruction is processed in the second pipeline stage, and the address calculation of the operand in the first pipeline stage. And an operand address calculation suppressing means for suppressing the address calculation of the operand in the first pipeline stage based on the contents of the reserved latch when executing the processing related to the second instruction for accessing the memory space. In the operand calculation stage, only the instruction that refers to the memory is placed in the waiting state due to the memory conflict, so that the disturbance of the pipeline processing can be significantly reduced and the pipeline processing efficiency can be improved. Further, since there is a memory write reservation flag for each stage constituting the pipeline, it is possible to hold memory write reservation information by a plurality of instructions in the pipeline.

In addition, a 1-bit register circuit having an input data signal, an input enable signal, a clear signal, and an output signal
Flag information holding unit, a second flag information holding unit which is a 1-bit register circuit having an input data signal, an input enable signal, a clear signal, and an output signal, a third pipeline stage, and a fourth pipeline. A flag information holding unit in which a first flag information holding unit and a second flag information holding unit are connected in series corresponding to a stage, and logic of each output of the first flag information holding unit and the second flag information holding unit. Flag information holding state detecting means for detecting the flag information holding state in the flag information holding means while taking a sum;
The first flag information holding unit is set when the first instruction is processed in the pipeline stage, and the processing of the first instruction is performed from the processing in the third pipeline stage to the processing in the fourth pipeline stage. When moving to, the contents of the first flag information holding unit is transferred to the second flag information holding unit,
Further, by clearing the first flag information holding unit, the information is sequentially moved in the flag information holding unit, and the memory space is accessed for operand address calculation according to the output of the flag information holding state detecting unit. Since the pipeline control means for controlling the processing relating to the instruction 2 is provided, the memory write reservation information held in each stage when the memory write reservation information / register write reservation information is transferred to each stage in the pipeline / Transfer to the subsequent stage while clearing the register write reservation information, and can automatically clear all the memory write reservation information / register write reservation information in the pipeline at the end of the instruction in the instruction execution stage, and the efficiency of pipeline processing It has an excellent effect that it can be remarkably improved.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the configuration of a data processing device according to an embodiment of the present invention, FIG. 2 is a configuration diagram illustrating an example of the write reservation information transfer circuit shown in FIG. 1, and FIG. FIG. 4 is a timing chart for explaining the transmission timing of each signal shown in FIG. 2, FIG. 4 is a circuit block diagram for explaining a conventional pipeline control mechanism, and FIG. 5 is a state diagram for explaining transition of pipeline processing. is there. In the figure, 1 is an IF stage, 2 is a D stage, and 3 is A.
Stage 4, F stage, 5 E stage, 6 and 7 instruction decoder, 8 decoder, 9 register write reservation circuit, 10 memory write reservation circuit, 11 and 13 register write reservation flag circuit, 12 and 14 Is a memory write reservation flag circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A pipeline processing mechanism including a first pipeline stage for calculating an address of an operand and a second pipeline stage for writing an operand of an operation result, and writing an operand of the operation result to a memory space. An operand write reservation unit that reserves the writing of an operand in the memory space when executing the process related to the first instruction for executing the operation 1 in the first pipeline stage; One or more reservation latch means, and a reservation latch clear means for clearing the contents of the one or more reservation latch means when processing the first instruction in the second pipeline stage; In the first pipeline stage, a memory space is allocated for address calculation of the operand. And an operand address calculation inhibiting means for inhibiting the address calculation of the operand in the first pipeline stage based on the contents of the reservation latch means when executing the processing relating to the second instruction to be accessed. Characteristic data processing device. 2. A third pipeline stage for sequentially processing a second instruction accessing a memory space for address calculation of a first instruction and an operand following the first instruction, and the third pipe. 4th after the line stage
A data processing device having a pipeline processing mechanism including a pipeline stage, and a first flag information holding unit which is a 1-bit register circuit having an input data signal, an input enable signal, a clear signal, and an output signal; A second flag information holding unit, which is a 1-bit register circuit having a data signal, an input enable signal, a clear signal, and an output signal, and the third pipeline stage and the fourth pipeline stage corresponding to the above. The logical sum of the outputs of the first flag information holding unit and the second flag information holding unit and the flag information holding unit in which the second flag information holding unit is connected in series, and the outputs of the first flag information holding unit and the second flag information holding unit are calculated. Flag information holding state detecting means for detecting the flag information holding state in the flag information holding means,
When processing the first instruction in the third pipeline stage, the first flag information holding unit is set, and the processing of the first instruction proceeds from the processing in the third pipeline stage to the fourth. Of the pipeline stage, the contents of the first flag information holding unit are changed to those of the second flag information holding unit.
Information is transferred to the flag information holding unit and the first flag information holding unit is cleared to sequentially move the information in the flag information holding unit, and according to the output of the flag information holding state detecting unit, And a pipeline control means for controlling a process relating to a second instruction for accessing a memory space for address calculation.