JPH077096A - Completely enclosed self-aligned separation process - Google Patents

Abstract

(57) Summary A method is provided for fabricating a bipolar transistor on a semiconductor wafer. The method includes implanting a p-type dopant into the diffusion compensation region (23) where the intrinsic base region (18) intersects the isolation oxide film (31). This implantation step is performed before the formation of the isolation oxide film (31). The diffusion compensation region (23) is connected to the emitter contact (27
Located under a). A diffused emitter (27b) is then formed by diffusing the dopant from the emitter contact (27a) into the lower active region. [Effect] By selectively incorporating the dopant in the diffusion compensation region, the segregation of the intrinsic base is compensated during the field oxidation, and the charge of the oxide in the field oxide film is also compensated. As a result, the desired base state is maintained at the edge of the emitter-isolation oxide film, and I _CEO
Can be reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to the field of semiconductor devices and their manufacture. More particularly, the present invention, in one embodiment, provides a bipolar device on a substrate and a manufacturing process thereof.

[0002]

2. Description of the Related Art Bipolar semiconductor devices and methods of making the same are well known. Such devices are described, for example, in commonly assigned US Pat. No. 4,609,568 (Koh et al.) And US Pat. No. 4,764,480 (Vora), the contents of which patents are hereby incorporated by reference. Incorporated herein by reference.

Recently, both bipolar and CMOS type devices have been implemented on a single substrate, and the advantages of both these devices have been effectively incorporated into the circuit. Circuits incorporating both bipolar and CMOS devices are known as "BiCMOS". BiCMOS devices offer the advantages of CMOS devices such as high recording density and low power consumption, and the high speed of bipolar devices. BiCMOS devices and one of their manufacturing processes are described in US Pat. No. 4,764,480.

Isolation of bipolar junction transistors (BJTs) is an important step in bipolar and BiCMOS fabrication. One known separation method is the so-called interface mask separation (SWAMI) process. BJTs manufactured by this process and some related processes have "walled emitters", where the transistor emitters intersect the isolation oxide. The wall emitter device makes efficient use of the active area of the device and minimizes collector-base parasitic capacitance for a given emitter area. Moreover, the layout area per transistor required for a transistor with a wall-shaped emitter is generally small.
In contrast, in a non-walled emitter BJT, the emitter is separated from the isolation oxide, and the resulting structure is such that the emitter-base edge contour is nearly uniform at all edge portions. This type of transistor typically requires a larger layout area than the wall emitter BJT for a given lithographic technique.

[0005]

Wall-shaped emitters can have certain problems, some of which are collector-type.
The emitter leakage current (I _CEO ) is excessive and the collector-
The emitter breakdown voltage BV _CEO may be low. I _CEO is
The current that flows between the collector and the emitter when a voltage is applied between the collector and the emitter while the base terminal remains open. A significant leakage current will result in poor yield and / or improper circuit operation.

There are many factors that can cause I _CEO to become excessive. Some of these are mitigated by eroding the corners of the BJT active area with excess isolation oxide. For example, the intrinsic base dopant can segregate into the field oxide adjacent to the base, resulting in a locally lower concentration of base dopant. This may also allow the subsequently formed emitter region to penetrate further into the intrinsic base region, resulting in a reduced base width. Both effects (reduced base width and reduced base dopant concentration) can lead to excessive leakage current between the emitter and collector at the intersection of the intrinsic base and isolation oxide. In addition, the charge present in the field oxide as a result of dopant segregation can cause inversion of the P-type intrinsic base region at the edge of the wall-shaped emitter, which causes leakage between the collector and the emitter. A route is created.

One method recently developed to overcome the above problems involves forming the diffusion compensation region in the region where the narrow base width occurs. This diffusion compensation region contains an increased concentration of base dopant so that segregation or inversion of the intrinsic base region is avoided. The diffusion compensation region is typically formed by implanting and diffusing a base dopant into the isolation oxide region prior to growing the isolation oxide. Devices formed according to this process are described in US patent application Ser. No. 07 / 821,256, the contents of which application is incorporated herein by reference in all respects.

Other methods for reducing or controlling I _CEO leakage in wall emitters generally tend to reduce BJT performance. For example, increasing the base width or increasing the dopant concentration across the base region can increase the transit time of charge in the base region and / or increase the parasitic capacitance of the BJT, thereby increasing the BJT's parasitic capacitance. Reduce performance.

In view of the above, in order to provide a device with improved performance, I _CEO in a BJT with a wall-shaped emitter (particularly for BiCMOS devices).
It will be appreciated that an improved method for controlling the current is desired.

[0010]

SUMMARY OF THE INVENTION Described herein are methods for improving the performance of a wall-emitter BJT.
The method involves selectively incorporating boron or other P-type dopant (in an NPN device) at the intersection of the isolation oxide and the emitter-base region (or "active region"). The incorporated region is referred to herein as a "diffusion compensation region".

This selective incorporation of boron has several advantages. Boron compensates for intrinsic-based boron segregation during field oxidation and reduces the tendency to flip in regions near the field oxide. Boron also compensates for the oxide charge in the field oxide,
This causes or contributes to the inversion of the P-type base region if not addressed.

By compensating for both the boron segregation of the intrinsic base and the charge of the oxide, the desired base state can be maintained at the edge of the emitter-isolator, I _CE
O can be reduced. Reducing excess I _CEO prevents yield degradation, prevents loss of functionality, and / or prevents abnormal circuit operation.

This technique has several advantages over known techniques. The additional incorporation of boron results in only a slight increase in the parasitic capacitance of the device, thus maintaining the desired BJT performance, in particular the BJT base transit time. Boron implantation also requires minimal increase in manufacturing process complexity and is standardized as described in Peltzer U.S. Pat.No. 3,648,125, the contents of which are hereby incorporated by reference in all respects. Can be easily combined into various separation steps.

The present invention incorporates the self-aligned implant and anneal steps into the well known oxidative separation step. Preferably, the method of the invention is SWAM
It is adopted in the I separation process. As a result of the present invention, boron is controllably placed near the "bird's beak" between the emitter contact and the intrinsic base, which does not affect the majority of the active intrinsic base, but the I at the emitter edge. _This will reduce the _CEO leakage current.

In one aspect, the invention provides a method of forming a portion of a base region in a bipolar transistor. This method comprises: (a) forming a mask which covers the active region and has an edge at the intersection of the isolation oxide region and the active region, and (b) a first conductivity type dopant in the region exposed by the mask. Inject and
(C) The dopant is laterally diffused from a portion where the dopant is injected below a part of the mask to form a diffusion compensation region adjacent to the base region, and (d) the region exposed by the mask is dry-etched. ) Forming a field oxide region in the etched region.

In the preferred embodiment, the mask used in the implant process includes a nitride film sandwiched between two thin oxide films. This thin oxide-nitride-oxide layer defines well-defined vertical planes at the edges of the active and field oxide regions. Thus, the subsequent dry etching also becomes vertical and self-aligned with the active region. Other masks, such as photoresists, often have beveled edges, which results in less well defined edge contours.

In another aspect, the invention provides a bipolar transistor manufactured on a semiconductor wafer. The transistor has an isolation oxide with an active region having an intrinsic base region, a collector region, an emitter region, and a diffusion compensation region. The diffusion compensation area is
It abuts the isolation oxide along an interface having an angle between about 85 and about 90 degrees to the vertical, and the diffusion compensation region is below the base into the active region by a small, predetermined area. Extend. More specifically, the diffusion compensation region is formed at the intersection of the intrinsic base region, the collector region, and the isolation oxide film region.

A further understanding of the nature and advantages of the present invention may be gained by
This can be achieved by referring to the rest of the specification and the accompanying drawings.

[0019]

EXAMPLES The following description of the examples is made in accordance with the following contents. I. General Matters II. Manufacturing process of BiCMOS device III. Conclusion I. General Matters FIG. 1 illustrates in cross-section a BiCMOS device according to one embodiment of the present invention. This illustrated device is a CM
Although including an OS device, the bipolar device of the present invention can be manufactured independently, and
It is not necessary to form part of the CMOS structure. In addition, although the embodiments described herein are silicon-based structures,
Other semiconductors (eg germanium or gallium arsenide) can also be used. The cross section shown in FIG. 2 is obtained by cutting the emitter contact 27a shown in FIG. 1 in a direction perpendicular to the emitter contact 27a. FIG. 3 is a plan view of the NPN bipolar transistor viewed from the level of the bottom of the emitter contact 27a.

This device is a bipolar transistor 2
(NPN transistor in the embodiment shown in FIG. 1), N-channel MOSFET (NMOS transistor) 4, P
A channel MOSFET (PMOS transistor) 6 is included on the same substrate. NMOS transistor 4 and P
The MOS transistors 6 are appropriately connected to form a CMOS structure 8.

The device is manufactured on a substrate 10. In the embodiment shown in FIG. 1, the substrate is a P-type substrate and is between about 1 × 10 ¹³ and 1 × 10 ¹⁶ / cm ³ , preferably 2 × 10 ^16.
It has a dopant concentration in the range of × 10 ¹⁴ to 3 × 10 ¹⁵ / cm ³ . Low pressure doped N-type epitaxial silicon is grown on the top surface of the substrate and the device is built therein.

In most embodiments, the NMOS transistor 4 is formed with a p ⁺ tub or P-well 12,
An n ⁺ tub, that is, an N well 14 is formed in the OS transistor 6. In the preferred embodiment, N-well 14 has a concentration gradient and is doped to a concentration of about 1 × 10 ¹⁶ to 2 × 10 ¹⁹ / cm ³ , preferably about 2 × 10 ¹⁶ to 5 × 10 ¹⁶ / cm ^3. Has been done. The P-well 12 has a concentration gradient and is between about 1 × 10 ¹⁶ and 1 × 10 ¹⁸ / cm ³ , preferably about 5 × 10 ¹⁶ to 7 × 1.
Doped to a general concentration in the range of 0 ¹⁷ / cm ³ . However, a wide range of dopant concentrations can be used without departing from the scope of the invention. Wells 12 and 14 allow forming complementary conductive devices on a single substrate.

The NPN transistor 2 is provided with a heavily doped buried layer 16 and a collector sink 17, which together provide a low resistance connection region between the collector contact 20 and the base 18. In the preferred embodiment, buried layer 16 and sink 17 are about 1 × 10 ¹⁷ to 1 × 10 ^20.
/ Cm ³ , preferably a concentration in the range of about 5 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ .

A p ⁺ channel stop 19 is provided between the NPN transistor and the adjacent device, and the buried layer 16
It prevents surface inversion of the lightly doped substrate connecting the adjacent device to the device. NMOS transistor 4
1 and the PMOS transistor 6, between the sink 17 and the base 18, between the NPN transistor 2 and the NMOS transistor 4, and between the transistor shown in FIG. And 22d respectively, which are typically SiO ₂ for device isolation, for example.

Along the surface of the device is a resistor 24, a base contact 26, an emitter contact 27a, a collector contact 20, an NMOS drain contact 28, an NMOS.
Gate 30, NMOS source / well tap 32a, PMO
S-drain 32b, PMOS gate 34, and PMOS source / well tap contact 36 are formed from one or more layers of deposited polycrystalline silicon (polysilicon). The emitter region 27b is the emitter contact 27a.
To the microcrystalline epitaxial layer. Region 27a, referred to herein as the emitter contact,
It will be appreciated by those skilled in the art that this region is sometimes referred to as the emitter. No semantic difference is intended.

Thin gate oxide layers are NMOS and PMO
An interface or side wall oxide 42 is provided under the gate of the S-transistor and over the gates of the NMOS and PMOS. In some embodiments, the NMOS gate is formed of heavily doped n ⁺ implanted polysilicon, while the PMOS gate is formed of n ⁺ or p ⁺ implanted polysilicon. N-type dopants are preferred for the PMOS gate because n ⁺ results in a buried carrier device with high carrier mobility, whereas p ⁺ results in a surface channel device. Sidewall oxide film 44 also provides bipolar emitter contact 27a.
Is also provided on the side wall of.

A metal contact (ie, a metal-containing contact), such as a silicide contact 46, is formed on the p ⁺ base contact 26 of the bipolar transistor. The silicide contact covers the top of the base contact, the sidewall of the base contact, and the upper horizontal surface of the base region from the sidewall of the base contact to the sidewall oxide of the emitter. Separate silicide contacts 48 are provided along the upper surface of the emitter contact 27a between the sidewall oxide films 44 spaced apart. The refractory metal contacts shown here reduce the contact resistance, thereby increasing the speed of the device.

Similarly, the silicide contacts are polysilicon collector contacts 20, NMOS gates 30, P.
Provided for MOS gate 34 and p ⁺ / n ⁺ source and drain polycrystalline contacts 28, 32 and 36. Similar to the silicide contact for emitter contact 27a, the silicide contacts 50 and 52 for the NMOS and PMOS gates, respectively, extend only from the sidewall oxide to the sidewall oxide. Conversely, the silicide contacts 54a, 54b, 54c, and 54d for the NMOS and PMOS source and drain contacts cover the sidewalls of the polysilicon contacts and extend to the horizontal portion of the source / drain down to the sidewall oxide of gates 30 and 34. Extend along. The silicide 55 for the collector contact is used in the field oxide regions 22b and 22c.
Covering the side wall of the collector contact down to
It also covers the upper surface of the collector contact.

This structure is further thick (0 ..) to insulate the device from the metal layer 58 used for interconnection purposes.
8 to 1.3, preferably about 1.3 micrometers) oxide film 5
Including 6 A plug 80 of tungsten may optionally be provided to fill the openings in oxide 56 between the first metal layer and the various silicide regions. An additional metal / oxide interconnect layer 82 can also be optionally provided, with a passivation film 84 on top.

At the intersection of the isolation oxide region and the intrinsic base region 18, as shown in FIG.
23 are arranged. The boron implant region 23 does not substantially change the dopant concentration of the intrinsic base region. However, at the edge of the intrinsic base region adjacent field oxide region 31, the boron implant region substantially compensates for outdiffusion of boron into the field oxide. In some embodiments, below the emitter contact, in the region directly adjacent to the field oxide, the boron implant region slightly increases the base width, as shown in FIG. Make sure to compensate.

Referring to FIG. 3, there is shown a plan view of the bipolar device described above. This figure exaggerates the relative position of the outdiffusion compensation region, or boron implant region 23, with respect to other device components. Metallization layers, passivation layers, and contact layers are not shown. This figure also depicts the diffusion before the emitter 27b is formed in the active region of the bipolar device. An isolation oxide film 22 surrounds the bipolar device region 101 on the semiconductor substrate. The intrinsic base region 109 intersects with the isolation oxide film 22 in the intersection regions 111 and 113. Near the center of the intrinsic base region 109, an emitter region (not shown) is subsequently formed from the conductivity type dopant opposite to the base region. The collector sink regions 121 and 122 are from the base region,
It is separated by the separation oxide film 22. Beyond the collector sink regions 121 and 122 is a CMO as shown in FIG.
There is an S device (beyond 122). As shown in FIG. 3, the diffusion compensation region 23 is formed at the edge of the intrinsic base 109 adjacent to the intersection regions 111 and 113. In the completed bipolar structure, the intrinsic base region
Emitter contacts (not shown) are present above 109 and diffusion compensation region 23.

II. BiCMOS Device Manufacturing Process FIGS. 4 to 26 illustrate a manufacturing process of the device shown in FIGS. 1 to 3. 4 to 26 are the same as FIG.
Taken along line 2 through diffusion compensation region 23 (and beyond collector sink region 121 and into the CMOS device). This allows a visual inspection of the process used to form the diffusion compensation region 23 in FIGS.

Although the method is fully described herein in the context of BiCMOS fabrication, other structures without MOS devices are also possible. Therefore, some of the steps described below that relate only to the fabrication of MOS devices can be omitted if the structure to be obtained includes only bipolar devices. FIG. 4 shows a cross section of the device at the first stage of manufacture. To reach this stage, de-nude the substrate.
nude) and form a screen oxide film. The device then has an n ⁺ tub or well 14 and a buried layer 16 of NPN.
With arsenic, antimony, etc. for simultaneous ion implantation. The implant energy used to form regions 14 and 16 is preferably about 50 to 200 keV, with a more preferred range of about 60 to 80 keV.
The dopant concentration in 4 and 16 is about 5 × 10 ¹⁷ to 2
× 10 ²⁰ / between cm ^3, and preferably about 1 × 10 ^{1 9} from 1 × 10 ²⁰
/ Cm ³ range. The buried layer is then annealed and further oxidized. As shown, the oxide film is n ⁺
It grows slightly thicker on the area.

[0034] After formation of the n ⁺ regions 14 and 16, the device is masked in as in FIG. 5, p ⁺ channel stop 19
And an NMOS tab or well 12 are formed simultaneously. The implant energy used to form regions 19 and 12 is preferably about 50 to 200 keV, with a more preferred range of about 14
0 to 200 keV, with dopant concentrations in these p ⁺ buried layers in the range of about 1 × 10 ¹⁷ to about 1 × 10 ¹⁸ / cm ³ . The p ⁺ region is preferably doped with boron.

As shown in FIG. 6, the channel stop mask and oxide are then removed, eg, about 1.
Doped N with a thickness of 1 micrometer
A shaped epitaxial silicon layer 21 is grown over the entire surface of the substrate. A thin (eg, about 250 Å) screen oxide film is then formed thereon and a nitride film is deposited to a thickness of, eg, about 1500 Å. However, for some applications thinner films, eg 750 Å, are preferred. In the preferred embodiment, an oxide or other suitable mask for silicon etching is then deposited over the nitride. The thickness of the nitride film and the oxide film is
It can be optimized depending on factors such as the selectivity of the oxide film with respect to silicon etching and the stress generated in the isolation oxidation step. After depositing the sandwich layer of thermal nitride and oxide, a photoresist mask is formed on the surface, and field oxide regions 22a, 22b, 22 are formed.
c and 22d are defined. The deposited nitride and oxide layers are then etched away from the unmasked areas, care being taken in this case not to over-etch the silicon. In some embodiments not shown, a thin screen oxide is left on the epitaxial silicon layer in the areas where the nitride was stripped. In another alternative embodiment, the screen oxide is stripped and a new oxide is subsequently grown.

The edge of the oxide film-nitride film-oxide film layer is
It may have various forms without departing from the scope of the present invention. For example, in some embodiments,
The nitride film is slightly undercut (beyond the oxide film) at one or more edge portions of this sandwich. Alternatively, spacer oxide can be formed at the edge of the sandwich structure.

Following the nitride etch, a boron implant is included in the process step shown in FIG. This is to form a more heavily doped region at the intersection of the isolation oxide film and the intrinsic base region after further processing steps. Boron is first implanted into the region where the intrinsic base intersects the isolation oxide.
In the preferred embodiment, some areas of the exposed field oxide are masked prior to the boron implant. In an alternative embodiment, boron is implanted into all areas where the nitride and oxide are etched away (ie where the isolation oxide is grown). This implant is preferably set at 0 ° to eliminate the shadowing effect of the implant caused by the stack of films. In some embodiments, rotating the wafer may use a larger angle implant.

The implant has an energy of about 20 to 60 keV,
It is performed with a dose of about 10 ¹⁰ to 10 ¹⁵ , the preferred implantation energy is about 35 keV, and the preferred dose is about 5 × 10 ¹⁴
Is. Subsequently, the boron implant is preferably annealed for about 60 minutes at about 950 degrees Celsius. Of course,
Other annealing condition ranges can also be selected. As shown in FIG. 7, boron is allowed to diffuse such that the p ⁺ region extends below the masked nitride region. Thus, the scattering by implantation and / or annealing driven steps must result in sufficient lateral migration of the doped boron, which is obtained by
The P plug shown at 23 has a sufficient doping level. Preferably, the annealing is p
The n-junction is performed a few micrometers from the edge of the mask of material on top.

The isolation oxide regions are formed using the well known "SWAMI" process, according to one embodiment. This process can be modified by varying the silicon etch procedure and depth, and selecting different oxide / nitride / oxide sidewall layers. In particular,
According to one embodiment, the silicon is masked and preferably etched using a dry etch (eg plasma) as shown in FIG. 8 to a depth of about 3000 Å, for example. Preferably, the edge portion of the etch mask is defined by the oxide-nitride-oxide structure defined prior to the boron implant. This thin, hard mask provides a near vertical surface and dry etching produces near vertical sidewalls. On the other hand, the contour of the resist mask is often more inclined,
It varies from wafer to wafer, and even on a single wafer. This thin and hard oxide mask provides excellent etching because the sidewall angle is sensitive to the resist profile.

After etching, the implanted boron is 23
It occupies only a small area shown by. The resist is then removed and a third thermal oxide film (approximately 400 Å) is removed.
The second nitride film (about 600 angstroms) and the fourth
And a deposited oxide film of about 1800 Å is formed on the device. A second plasma etch is used to remove approximately 750 angstroms of additional silicon, leaving the device substantially as shown in FIG. Subsequent removal of the remaining sidewall oxide and subsequent oxidation of the substrate in a high pressure (eg 10 atmospheres) oxidizing environment to grow the required isolation oxide leaves a device as shown in FIG. The interface between the resulting isolation oxide film and the active region is preferably between about 85 and 90 degrees to the horizontal. This sharp slope is the result of the well-defined etching characteristics of the dry etching used and the thin and hard oxide-nitride-oxide mask. Wet etching and / or photoresist masks tend to produce more sloping interfaces, which in turn reduces device storage density. Of course, some of the oxide will erode into the active area near the top of the interface, as shown in FIG.

After the isolation oxide film is formed, the nitride is stripped off and a screen oxide film having a thickness of about 250 Å is formed on the substrate surface as shown in FIG. A mask is then formed and only the sink area 17 is exposed. As shown in FIG. 12, a sink implant is then performed using phosphorus as a dopant with an implant energy of about 100 to 190 keV and a dose of about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ . The resulting dopant concentration in sink region 17 is between about 1 × 10 ¹⁸ and 1 × 10 ²⁰ / cm ³ . The sync mask is then removed and another masking /
Ion implantation is performed and the well and channel regions of the PMOS transistor are doped with phosphorus as a dopant at a concentration of between about 1 × 10 ¹⁶ and 5 × 10 ¹⁶ / cm ³ as shown in FIG. . In a preferred embodiment, the implant energy used for the well region of the PMOS is between about 50 and 200 keV, and about 100 to 200 keV.
V is preferred. The total dopant concentration obtained in the N-well epitaxial channel region is about 1 × 10 5.
It is between ¹⁶ and 5 × 10 ¹⁶ / cm ³ . The sink and N-well are then annealed and driven in by heating with a conventional nitrogen thermal cycle.

After that, a mask is formed on the surface of the substrate to expose only the NMOS and PMOS transistor regions. This mask is used for threshold voltage injection as shown in FIG. This injection is typically about
Between 0.6 | and | 1.0 | volts, NMOS and PMO
It is used to adjust the threshold voltage of the S-transistor as needed. In a preferred embodiment, the threshold voltage implant is implanting boron between about 1 × 10 ¹³ and 5 × 10 ¹³ , preferably 30 to 60 keV.
This boron and p ⁺ that diffuses upward from the P well are NM
Set the threshold voltage of the OS transistor. This threshold voltage injection, in combination with the N-well injection, sets the threshold voltage of the PMOS transistor. In the preferred embodiment, the threshold voltage injection ultimately results in a transistor having a threshold voltage of 0.75 ± 0.1 for NMOS transistors and −0.85 ± 0.1 for PMOS transistors.

Referring to FIG. 14, the screen oxide is then stripped and a thin (on the order of 135 to 165 Angstroms) gate oxide 86 is grown using means well known to those skilled in the art. Then a thin (400 to 600 Angstroms) polysilicon layer 88 is deposited on the thin gate oxide and a mask 62 is formed on the polysilicon layer to define the NMOS and PMOS gates. The plasma etch removes the undesired polysilicon layer from all areas on the substrate except those on the NMOS and PMOS gate oxide areas. Next, the lower oxide film is removed using wet etching. Protection of the gate oxide with a thin polysilicon layer results in MOS gates with very few defects because they are not directly exposed to photoresist.

FIG. 15 shows the next step in the process steps. The gate oxide mask 62 is removed and about 1000
To 4000, preferably about 3200 angstroms, another layer 64 of intrinsic polysilicon is deposited over the entire surface of the substrate by thermal oxidation of the polysilicon layer 64.
A cap oxide film 66 is formed. The device is then masked with photoresist to expose at least the base region of the bipolar transistor and the lightly doped region of the resistor. In some embodiments,
Only the NMOS and PMOS transistor regions are protected by the mask. Base implant is performed as shown in FIG. This implant is subsequently annealed to produce P
Topographical dopants are diffused from the BJT polysilicon layer 64 to form an intrinsic base region. In a preferred embodiment, this base implant uses energy between about 30 and 100 keV, with a preferred base implant energy of about 30 to 50.
It is keV. The dose for this implant is preferably about 3 × 10 ¹³
To 8 × 10 ¹⁵ . In a preferred embodiment, annealing the structure for 900-900 minutes.
Performed by heating to 950 ° C., resulting in a thickness of between about 1000 and 2000 Angstroms,
A p-type base region is obtained having a dopant concentration of about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ , preferably about 5 × 10 ¹⁸ / cm ³ .

In an alternative embodiment, the intrinsic-based ion implantation is performed before the polysilicon layer 64 is formed.
Performed directly on the epitaxial silicon layer. Regardless of how the intrinsic base is formed, the diffusion compensation region 23 preferably has a boron concentration that is equal to or higher than the boron concentration of the intrinsic base region (a portion beyond the diffusion compensation region).

As shown in FIG. 17, a region 70a that will eventually become part of the resistor and contact 32 (shown in FIG. 1).
And a mask is formed to expose 70d. In addition, the mask exposes the area where the base contact (see FIG. 1) will be formed. These regions are preferably p ⁺ doped with boron to a concentration of between about 1 × 10 ¹⁹ and 1 × 10 ²⁰ / cm ³ , preferably about 6 × 10 ¹⁹ / cm ^3. It This p ⁺ mask is removed and another mask is formed on the device surface to eventually be used as the emitter contact, collector contact, source / drain contact of the bipolar transistor and the gate of the MOS transistor 68a. , 68b and 68c are exposed. These regions 68a, 68b and 68c are about 100 keV with arsenic implant.
With the energy of about 5 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³
N ⁺ to a concentration of. As mentioned above, PM
The OS gate is n ⁺ or p ⁺ and is therefore included in either the n ⁺ or p ⁺ mask. Then, a nitride film 67 having a thickness of between about 1000 and 1200 angstroms prevents undercutting due to the etching of the underlying polysilicon and prevents link-like ion implantation into the gate and emitter. It is deposited for the purpose. Polysilicon layer 64
Is then annealed at 900 ° C. for 15 minutes.

Next, a mask is formed on the surface of the nitride film to protect the base, emitter and collector contacts of the bipolar transistor and the sources, gates and drains of the NMOS and PMOS transistors. As a result of chemical dry etching with chlorine, the structure shown in FIG. 18 is obtained. This etching begins at the base of the bipolar and the epitaxial region adjacent to the gate of the MOSFET starting at about 1000 times less than the original epitaxial surface.
It is done as if it were etched down by 2000 Angstroms.

The next step in the process is shown in FIG.
The etching mask is removed. Ion implantation of a lightly doped drain (LDD) is performed, in this case NMO
The source and drain of the S-transistor are about 20 to 50 ke
Lightly ion-implanted with an n-type dopant such as phosphorus with an implant energy of V, preferably about 20-40 keV. This implant results in source and drain regions 72 having a dopant concentration of approximately 5 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ and self-aligned with the NMOS gate.
Is obtained. After the oxidation process to grow the cap oxide film, p-type LDD using a dopant such as BF ₂ is performed.
Over the entire surface of the bipolar and PMOS transistors, the source and drain of the PMOS transistor and the base region of the bipolar transistor are exposed by the mask. A more highly doped p-type region (not shown) self-aligned with the emitter contact is formed at the base of the bipolar transistor, and a more heavily doped p-type region 76 self-aligned with the gate is formed. It is formed around the gate of the PMOS transistor. The resulting total dopant concentration in region 76 (and the p-type region in the more heavily doped bipolar base) is about 5 × 10 ¹⁷
To 1 × 10 ¹⁹ / cm ³ . The implantation energy is preferably about 40 to 60 keV. As shown, more heavily doped well connections are also diffused from the NMOS contact to the PMOS contact. Further, the emitter region 27b is diffused from the upper emitter contact 27a and the heavily doped intrinsic base region is diffused from the base contact.

Referring now to FIG. 20, the nitride film is stripped from the device surface and low temperature oxide (LTO) deposition is performed. A silicide exclusion mask, not shown, is formed on the device over the polysilicon regions where silicide formation is not desired (eg, over the center of the resistor). The oxide is then etched back and the source contact, drain contact, gate,
Spacer oxide is left on the exposed sides of the emitter, base and collector contacts. The mask shown in Figure 20 is then formed over the device to protect the bipolar emitters, the gates of the NMOS and PMOS transistors, and at least the sidewall oxide over the resistors. The device is BOE etched for about 1 minute and the oxide is removed from the sidewalls of the resistor / base contact, the collector contact, and the source and drain contacts of the NMOS and PMOS transistors, as shown in FIG. In an alternative embodiment, sidewall oxide is selectively formed on the sidewalls of polysilicon according to the process disclosed in US patent application Ser. No. 07 / 503,491. The disclosure of this application in all respects is incorporated herein by reference to the numbers herein.

Referring to FIG. 22, a mask is formed and a strong p ⁺ (BF ₂ ) ion implantation is performed in the regions shown, namely the source / drain regions of the PMOS transistor and the intrinsic base region of the bipolar transistor. . The purpose of this ion implantation is to further reduce the resistance of the source / drain regions and the intrinsic base region.
This ion implantation uses energy between about 40 and 60 keV. Similarly, as shown in FIG. 23, n ⁺ (arsenic) ion implantation is performed in the source / drain regions of the NMOS transistors with the purpose of forming the source / drain regions and reducing their resistance.
This arsenic implant uses energy between about 50 and 100 keV. The device is then optionally about 10 to 30 at a temperature of about 900 to 950 ° C. for about 10 to 30 minutes, or using a short time annealing process.
Annealed at a temperature of 1000 to 1100 ° C. for seconds.

Next, a refractory metal layer of titanium, molybdenum, tantalum, tungsten or the like is deposited over the device surface. In the area where the deposited metal contacts polysilicon using means well known to those skilled in the art,
This layer is heated to form a metal silicide.
Unreacted residual metal is then etched away from the device, leaving the structure as shown in FIG. As shown in this figure, the silicide contact of the emitter
48 is from the side wall oxide film on one side to the side wall oxide film on the other side,
It extends over the entire horizontal upper surface of the emitter contact. Bipolar polysilicon-based contacts (not shown) are covered with silicide along their entire horizontal top surface and along their vertical sidewalls. In addition, the silicide contacts extend from the vertical sidewalls along the horizontal top surface of the single crystal base, all the way to the sidewall oxides of the emitter. The silicide 80 on the collector contact 20 extends along both vertical sidewalls of the collector contact and over the entire horizontal top surface of the contact, terminating on field oxide regions 22b and 22c. The silicide 54a on the NMOS polysilicon contact 28 rises from the field oxide region 22c to the vertical sidewalls of this contact, extends to the top surface thereof, and descends the vertical portion of the contact to the single crystal source region of the NMOS transistor. . Further, the silicide extends from this contact to the horizontal upper surface of the source / drain region and reaches the sidewall oxide film of the gate. Similar to a bipolar emitter, the polysilicon gate of an NMOS transistor includes a silicide 50 that extends from one sidewall oxide to the other sidewall oxide over the entire top surface.

The polysilicon well tap 32 is also covered with a silicide 54b, which covers both the vertical sidewalls and the horizontal top surface of the contact. Further, this silicide extends over the upper surface of the transistor to the sidewall oxide film of the gate of the transistor. PM
The OS gate includes a silicide 52c that extends over its horizontal top surface, whereas the PMOS source contact includes a silicide 54c that extends over its horizontal top surface, vertical sidewalls, and the horizontal top surface of the drain to the sidewall oxide of the gate.

The contact morphology disclosed herein results in reduced source / drain resistance through silicidation of the sidewall polysilicon contact strips, thereby increasing the current drive performance of the CMOS transistor and the polysilicon-silicon contact. Eliminate resistance. Since the current is carried through the silicide on the sidewall and not through the epitaxial silicon-polysilicon interface, the spacer oxide film on the sidewall is removed and the sidewall is silicidized, so that the polysilicon source / drain is formed. And reduced epitaxial silicon source / drain overlap. This reduces the active area of the CMOS transistor, resulting in high storage density.

By removing the spacer sidewall oxide and siliciding the polysilicon sidewalls of the intrinsic base, the resistance of the intrinsic base is reduced, thus eliminating the problem of high polysilicon-silicon contact resistance. The electrical characteristics of the transistor are increased. Through siliciding the sidewall polysilicon of the intrinsic base and reducing the overlap of the base polysilicon and the epitaxial silicon base, the bipolar transistor geometry is reduced. Thus, in combination with the low resistance of the intrinsic base, a lower intrinsic base junction capacitance is obtained.
Also, reducing the active area of the bipolar transistor due to sidewall silicidation also reduces the collector-substrate junction capacitance, thereby improving the transistor's electrical characteristics. Furthermore, silicidation of the collector sidewall polysilicon to contact the silicided polysilicon to the silicided silicon collector reduces collector resistance by eliminating polysilicon to silicon contact resistance. . This reduced resistance allows the collector region to be scaled, thus reducing collector-substrate capacitance and increasing storage density.

It is believed that local interconnect sidewall silicidation improves the interconnect resistance by a factor of 2, thereby improving circuit performance. The silicided polysilicon according to the present invention, when applied to the ground tap, conducts current through the sidewalls of the silicided polysilicon tap to the substrate rather than from the doped polysilicon to the substrate. , Reduce the ground tap resistance.

FIG. 25 shows the next procedure in the manufacturing process, in which an oxide film 56 is deposited and masked to form contact holes. Metal is deposited on the surface of the device, masked and etched from selected areas to provide the device as shown in FIG.
In an alternative embodiment, the contact holes are filled with tungsten and etched back to form a planar surface prior to depositing the metal interconnect layer. Thereafter, an additional metallization layer is formed and the device is passivated.

III. Conclusion It will be understood that the above description is intended to be illustrative and not limiting. Many modifications and variations of the present invention will be apparent to those of skill in the art upon reviewing the disclosure herein. Although the invention has been illustrated with reference to specific dopant concentrations in some cases, it will be apparent that a wide range of dopant concentrations can be used for many features of the devices of the invention without departing from the scope of the invention. further,
Although the invention has been illustrated with respect to BiCMOS devices, other structures, including bipolar devices, can be similarly manufactured. Therefore, the scope of the invention should be determined not by the above description, but by the claims and their equivalents in their full scope.

[0058]

As described above, according to the present invention, boron is sequestered selectively in the diffusion compensation region to compensate for intrinsic base boron segregation during field oxidation, and to prevent the tendency to invert in a region close to the field oxide film. Can be reduced. The diffusion compensation region also compensates for the oxide charge in the field oxide, preventing inversion or contribution to the P-type base region. In this way, by compensating both the boron segregation of the intrinsic base and the charge of the oxide, the desired base state can be maintained at the edge of the emitter-isolation oxide film, and I _CEO can be reduced. Prevent deterioration of the yield by reducing the excess I _CEO, to prevent loss of functionality, and /
Alternatively, it is possible to prevent abnormal circuit operation. Also, the inclusion of the diffusion compensation region only slightly increases the parasitic capacitance of the device and minimally increases the complexity of the manufacturing process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a BiCMOS structure according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a bipolar structure according to one embodiment of the present invention.

FIG. 3 is a plan view of a bipolar structure according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 10 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 11 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 12 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 13 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 14 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 15 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 16 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 17 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 18 is a cross-sectional view showing a manufacturing step of a BiCMOS device incorporating the present invention.

FIG. 19 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 20 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 21 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 23 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 24 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 25 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

FIG. 26 is a cross-sectional view showing the manufacturing steps of a BiCMOS device incorporating the present invention.

[Explanation of symbols]

 2 NPN transistor 4 NMOS transistor 6 PMOS transistor 10 substrate 12 P well 14 N well 16 buried layer 17 collector sink 18 base 19 channel stop 20 collector contact 22a, 22b, 22c, 22d isolation oxide region 23 diffusion compensation region 24 resistance 26 Base contact 27a Emitter contact 27b Emitter region 28 NMOS drain contact 30 NMOS gate 31 Field oxide film region 32a NMOS source / well tap 32b PMOS drain 34 PMOS gate 36 PMOS source / well tap contact 54a, 54b, 54c, 54d Silicide contact

[Procedure amendment]

[Submission date] March 18, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

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─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 29/73 (72) Inventor Michael Gravisic 9595 San San Jose, Menker Avenue, California, USA 692

Claims (21)

[Claims] 1. A method for forming a diffusion compensation region at an intersection of an intrinsic base region and an isolation oxide film region of a BJT, wherein the intrinsic base region is disposed in an active region, and a first conductivity type is formed. A) covering the active region and forming a mask having an edge at the intersection of the isolation oxide and the active region; and b) adding a dopant of the first conductivity type to the region exposed by the mask. Implanting, c) laterally diffusing the dopant from the implant site underneath a portion of the mask to form a diffusion compensation region, and d) dry etching the region exposed by the mask. And e) forming a field oxide film in the etched region. 2. The mask used in the implantation step is
The method of claim 1 including a nitride film sandwiched between two oxide films. 3. The method according to claim 2, wherein the nitride film in the mask is undercut between the two oxide films in the region of the edge portion of the mask. 4. The method of claim 2 wherein the mask used in the implant step further comprises spacer oxide adjacent the edge of the nitride sandwiched between the two oxides. 5. The method of claim 2 wherein one oxide defines a top surface of the mask at an edge of the mask at the intersection of the isolation oxide and the active area. 6. The method of claim 1, wherein the first conductivity type dopant is a P-type dopant. 7. The method of claim 6, wherein the P-type dopant is boron. 8. A method for forming a diffusion compensation region at an intersection of an intrinsic base region and an isolation oxide film region of a BJT, wherein the intrinsic base region is disposed in an active region and a first conductivity type is formed. A) a) forming a first oxide film, a nitride film, and a second oxide film on the surface of the epitaxial silicon; and b) forming a nitride film and a second oxide film in the selected region. Removing to form a mask covering the active region and having an edge at the intersection of the isolation oxide and the active region; and c) implanting a dopant of the first conductivity type in the region exposed by the mask. D) diffusing the dopant laterally from the implant site down the portion of the mask to form a diffusion compensation region, and e) dry etching the region exposed by the mask. The method comprises the step and, and f) a step of forming a field oxide film on the etched region. 9. The method of claim 8, wherein the second oxide defines a top surface of the mask at an edge portion of the mask at the intersection of the isolation oxide and the active area. 10. The method of claim 8, wherein the first conductivity type dopant is a P-type dopant. 11. The method of claim 10, wherein the P-type dopant is boron. 12. A method for manufacturing a BJT, comprising: a) defining an active region and an isolation oxide region on an epitaxial silicon surface; and b) coating the active region and an isolation oxide region. Forming a mask having an edge at the intersection with the active region; and c) implanting a dopant of the first conductivity type into the region exposed by the mask at the intersection of the isolation oxide region and the active region. D) diffusing the dopant laterally from the implant site underneath a portion of the mask to form a diffusion compensation region, e) dry etching the region exposed by the mask, f) Forming a field oxide in the etched region, g) forming an emitter contact on the active region, and h) a second conductive layer. The method comprising the step of forming an emitter in the form of a dopant to diffuse into the active region from the emitter contact. 13. The method of claim 12, wherein the mask used in the implanting step comprises a nitride film sandwiched between two oxide films. 14. The method of claim 12, wherein the first conductivity type dopant is a p-type dopant and the second conductivity type dopant is an n-type dopant. 15. The method of claim 14, wherein the P-type dopant is boron. 16. A bipolar transistor having a diffusion compensation region at an intersection of an intrinsic base region of a BJT and an isolation oxide film region, wherein the intrinsic base region is arranged in an active region and has a first conductivity type. A) a diffusion compensation region comprises: a) forming a mask which covers the active region and has an edge at the intersection of the isolation oxide film and the active region; and b) a first conductivity type in the region exposed by the mask. The step of: d) implanting the dopant of step c); d) diffusing the dopant laterally from the point of implantation down the portion of the mask to form a diffusion compensation region; and d) drying the area exposed by the mask. A bipolar transistor formed by etching, and e) forming a field oxide film in the etched region. Register. 17. The bipolar transistor of claim 16, wherein the first conductivity type dopant is a P type dopant. 18. The bipolar transistor of claim 17, wherein the P-type dopant is boron. 19. A bipolar transistor manufactured on a semiconductor wafer, comprising an isolation oxide film and an active region having an intrinsic base region, an emitter region and a diffusion compensation region, the intrinsic base region and the diffusion compensation region. And are of the first conductivity type and the emitter region is of the opposite second type.
Of the conductivity type, the diffusion compensation region abuts the isolation oxide film along an interface having an angle of about 85 to about 90 degrees with respect to the horizontal, and the diffusion compensation region separates from the intrinsic base region and the isolation oxidation region. A bipolar transistor formed at the intersection of the film regions. 20. A first charge carrier is introduced into the intrinsic base region to form a first conductivity type and an opposite second charge carrier is injected into the collector and emitter regions. 20. The bipolar transistor of claim 19, forming two conductivity types. 21. The bipolar transistor of claim 19, wherein the first conductivity type is p-type and the second conductivity type is n-type.