JPH0772178A - Logic analyzer - Google Patents

Abstract

(57) [Summary] [Object] The present invention detects the value of each bit of data of serial data and displays the value of the data in close proximity to the corresponding part of the data displayed on the screen so that the observer can display the value of the data. The aim is to be able to easily and definitely recognize. [Structure] The reading position calculation circuit 79 includes a change point detection circuit 78.
The reading position is calculated from the change point of the display data detected by. The data reading circuit 80 reads the calculated level of the display data at the reading position and causes the character generation circuit 81 to generate "1" if the level is high, and generates a character "0" if the level is low. The generated characters are displayed in the circuit 81 and displayed near the corresponding portion of the data displayed on the display device 77. This allows the observer to easily and definitely recognize the value of the display data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic analyzer for recording and displaying a data pattern of a digital signal,
The present invention relates to a configuration for displaying data by sampling data of a serial signal.

[0002]

2. Description of the Related Art A conventional logic analyzer has a structure in which an input signal is detected as a high level or a low level by an internal sampling clock and is written in a recording memory. FIG. 16 shows an example of a conventional logic analyzer of this type. The plurality of input signals 701 are converted into high level or low level binary data by the sampling circuit 71, and then input to the data recording memory 75. on the other hand,
The trigger detection circuit 72 detects a trigger condition (pattern) from the plurality of input signals 701, and when the trigger condition is detected, notifies the sampling counter 73 of this. When the sampling counter 73 is informed of the detection of the trigger condition, the sampling clock oscillator (OSC) 7
The recording position designation address is generated by receiving the clock signal 704 from No. 4 and counting the number of recording data, and outputs this to the data recording memory 75. This allows
The binarized data is written in the data recording memory 75. The sampling counter 73 stops the data writing to the data recording memory 75 after recording the data a predetermined number of times after the trigger detection circuit 72 detects the trigger point. The data recorded in the data recording memory 75 is converted into a display format by the data conversion circuit 76 and then displayed on the screen of the display device 77.

Here, the input signal 701 shown in FIG.
When serial data of NRZ type 2400 bps as shown in 7 is input, the length of 1 bit of this serial data is 416.7 μsec, and this signal is recorded in the data recording memory 75 at the sampling period of 10 μsec. By doing so, the time difference can be observed by simultaneously displaying this serial signal with another signal on the display device 77 with a resolution of 10 μsec. Here, the 1-bit signal length corresponds to about 41 sampling numbers. Whether the data of each bit is at the high level or the low level can be seen at approximately the midpoint of each bit, and the number of samplings is 2
It will be about 0. However, in the conventional logic analyzer, the observer must visually find out where the intermediate point is, which imposes a burden on the observer and may cause an observation error.

Further, the above-mentioned conventional logic analyzer is configured so that the trigger detection circuit 72 detects the pattern by the combination of the high level or the low level of one or a plurality of input signals, and triggers to record the signal. It had been.

FIG. 18 shows an example of the trigger detection circuit 72 described above. 181 is an exclusive OR circuit for selecting whether to pass the signal as it is or inverting the high level and the low level, and 182 is a pattern of the signal. An OR circuit that selects valid or invalid as a detection condition, 1
Reference numeral 83 is an AND circuit for synthesizing signal conditions, and 184 is a data holding circuit including a data latch for holding pattern detection conditions. In this figure, the number of input conditions 701 (corresponding to the input signal) is two, but a larger number may be used, and normally 8 to 16 are used.

According to this conventional apparatus, since the condition is set by the birds according to the combination pattern of the input signals, the time change of the signals, that is, the data is sent by dividing the data into time intervals used for serial communication. When observing a signal, after recording the serial data in the data recording memory 75 with specific serial data as a trigger condition, displaying on the display device 77, and observing a signal change under such condition is desired. In this case, the observer has to visually select a specific pattern from a large number of displayed patterns, which is disadvantageous in that the observer is burdened and an observation error is likely to occur.

[0007]

In the conventional logic analyzer as described above, the binarized input signal is sampled at the sampling cycle and written in the recording memory.
Since the written data is only displayed as a pattern on the display device 77, if the input signal is serial data,
The value of each bit of the data must be checked by the observer by looking for the approximate middle point of each bit, which is erroneous if the observer is burdened and the serial data is long or the waveform is distorted due to noise or the like. I was afraid. In addition, since the trigger condition is set by the combination pattern of the input signals, the time change of the signals, that is, the case of observing a signal that is sent by dividing the data into time intervals that are used for serial communication, that is, a specific When you want to observe the signal change under such conditions by recording the serial data of the above as a trigger condition in the memory and then displaying it, the observer can visually select a specific pattern from among the many displayed patterns. It had to be selected, which had a drawback that the observer was burdened and that an observation error was likely to occur.

Therefore, the present invention eliminates the above-mentioned drawbacks, calculates the data length of serial data, detects the value of each bit, and displays the data in close proximity to the corresponding part of the data displayed on the screen, To provide a logic analyzer capable of easily and erroneously recognizing the value of the data, and generating a trigger only when a serial signal of a specific pattern is input, and recording and displaying the input signal. It is an object.

[0009]

SUMMARY OF THE INVENTION According to the present invention, in a logic analyzer for sampling an input signal at a predetermined sampling period and storing it in a memory, and displaying the data stored in the memory, the level of the data stored in the memory is displayed. A change point detecting means for detecting a change point, and an operation for calculating a position for reading the level of the data based on the change point detected by the change point detecting means and the length per bit of the data designated in advance. Means, data reading means for reading the level of the display data at the reading position calculated by the computing means, character generating means for generating a character indicating the level of the data read by the data reading means, and this character generation Display means for displaying the characters generated by the means in proximity to the corresponding portion of the display data It has a configuration which is provided.

As another configuration, in a logic analyzer which samples an input signal at a predetermined sampling period and stores it in a memory and then displays the data stored in the memory, a sampling clock for sampling the input signal is divided. The input signal is converted into parallel data by frequency dividing means for performing frequency division, initialization means for detecting a change point of the input signal to initialize the frequency dividing means, and a frequency dividing clock output from the frequency dividing means. After that, it comprises a comparison means for comparing this with reference data, and a storage control means for storing the sampled input signal in the memory from the time when the comparison means determines that the two data match. .

[0011]

In the logic analyzer of the present invention, the change point detecting means detects the level change point of the data stored in the memory. The calculating means calculates a position at which the level of the data is read based on the change point detected by the change point detecting means and the length per bit of the data designated in advance. The data reading means reads the level of the display data at the reading position calculated by the calculating means. The character generating means generates a character indicating the level of the data read by the data reading means. The display means displays the character generated by the character generation means in proximity to the corresponding portion of the display data. This allows
Since the value is displayed numerically together with the display data, the observer can easily and accurately read the display data.

In the operation of the logic analyzer having another structure, the frequency dividing means divides the frequency of the sampling clock for sampling the input signal. The initialization means detects a change point of the input signal and initializes the frequency division means. The comparing means converts the input signal into parallel data by the divided clock output from the dividing means, and then compares the input signal with reference data. The storage control means stores the sampled input signal in the memory from the time when the comparison means determines that the two data match. Thereby, since the serial data of the specific pattern indicated by the reference data is automatically selected and displayed, the observer does not need to search for the specific pattern as in the conventional case, and the serial data of the target pattern The observation can be performed easily and accurately.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the logic analyzer of the present invention. 71 is the input signal 701
A sampling circuit for digitizing, 72 a trigger detection circuit for detecting a trigger condition from the input signal 701, 73 a sampling counter for generating a data recording address, 74 an oscillator for generating a reference clock for address generation, 75
Is a data recording memory for recording the binary data, 76 is a data conversion circuit for converting the binary data into display format data, 77 is a display device for displaying the data recorded in the memory 75, and 78 is a memory 75. A conversion point detection circuit for detecting low (“0”) level and high (“1”) level conversion points of the recorded display data, and 79 is a read position calculation for calculating the read position of each data bit from the reference change point. circuit,
Reference numeral 80 is a data reading circuit that reads out whether the data at the reading position is low level or high level and generates a character "0" or "1" by the character generation circuit 81. Reference numeral 81 is "0" or " This is a character generation circuit for generating the character "1" and outputting these characters to the display device 77.

Next, the operation of this embodiment will be described.
The input signal 701 is 2400 bp as shown in FIG.
If the data is an 8-bit start / stop synchronization signal in s, the portions without data (including stop bits) 201 and 21
1 is present at a high (“1”) level for a certain length or longer, and is composed of a start bit (S) having a 1-bit length and an 8-bit data bit from a transition point Po from a high level to a low level. Therefore, in order to know the data content, the change point detection circuit 78 first detects the first change point Po. Next, the read position calculation circuit 79 calculates the midpoint position of each bit in order to read the value of that bit at the substantially midpoint of each data bit. The length of 1 bit is 416.7 μs, and when the sampling speed of data recording is 10 μsec, 416.7 / 10 = 41.67, which is not an integral multiple. However, since the data recording memory 75 stores only data for every 10 μsec of the sampling speed, it is converted into an integer (rounded off) in the calculation of the middle point position.

That is, assuming that the number of data recording samples per bit length of 41.67 is l _o , the arithmetic expression is P _o + l _o / 2
+ L _o × n. However, (n = 0.1, ..., 8) In the above equation, when n = 0, P _o +20.83
Integer ratio P _o +21 When n = 1 P _o +62.50 Integer ratio P _o
+63 When n = 8 P _o +354.17 Integer ratio P _o
+354 At the midpoint obtained by the above calculation, when n = 0, it is a start bit, so the data reading circuit 80 causes the character generating circuit 81 to generate “S”, and the display device 77 displays it.
It is displayed as shown in (A), and since the others are data bits, the value at that point is high (“1”) or low (“0”).
And read "1" or "0" as shown in Fig. 2 (A).
As shown in FIG. FIG. 2B shows the above-mentioned integerized reading position. Data reading circuit 8
In the case of 0, the data value is similarly displayed at the change point P ₁ after the next data-less portion 211. In the above description, the input signal 701 has a data length of 8 bits, but
The data length may be 7 bits to 6 bits, and of course, a parity bit may be added. However, FIG. 2B shows the bit length of the data shown in FIG.

FIG. 3 is a flowchart showing the operation of detecting and displaying the start point when the input signal 701 is a start-stop synchronization type signal. The conversion point detection circuit 78 sets the pointer (P) to the left end of the display data in step 301, and then increments the pointer (P) in step 302 while incrementing the pointer (P) from the data recording memory 75 to display the display data (binarized data). ) Is read. Next, the change point detection circuit 78 determines in step 303 whether or not the data has changed from a high level to a low level. If it does not change, the process jumps to step 305, and if it changes, step 3
Go to 04. Reading position calculation circuit 79 in step 304
Calculates the midpoint position and displays the character at the midpoint position of the data displayed on the display device 77 via the data reading circuit 80 and the character generating circuit 81. Thereafter, the change point detection circuit 78 determines in step 305 whether or not the display position is the right end portion of the data displayed on the screen. If it is not the right end portion, the process returns to step 302, and if it is the right end portion, The process ends.

FIG. 4 is a flow chart showing a detailed example of the character display processing at the midpoint position shown in FIG. In step 401, the reading position calculation circuit 79 sets the number of data storage samples per bit length to l _0, and in step 402 sets 0 to n, and then proceeds to step 403. In step 403, the reading position calculation circuit 79 calculates the midpoint position P and converts it into an integer. In step 404, the data reading circuit 80 reads the display data of the position of the pointer (P) designating the calculated midpoint position P from the data recording memory 75, and then in step 405, is n = 0? It is determined whether or not, and if it is 0, step 407.
Then, the character generation circuit 81 generates a start bit S, displays it at the midpoint position of the data displayed on the screen of the display device 77, and proceeds to step 410. If it is determined in step 405 that n = 0, the process proceeds to step 406, in which the data reading circuit 80 determines whether or not the read data is 1, and if it is 1, the process proceeds to step 408. If it is not 1, proceed to step 409. The data reading circuit 80 is step 408.
At "1" is generated by the character generation circuit 81 and is displayed at the midpoint position of the data displayed on the screen of the display device 77, and the process proceeds to step 410. The data reading circuit 80 causes the character generation circuit 81 to generate "0" at step 409, and displays it at the midpoint position of the data displayed on the screen of the display device 77, and at step 4
Go to 10. Next, the reading position calculation circuit 79 proceeds to step 41.
At 0, n is incremented by +1 and set to a new n. Then, the process proceeds to step 411, and it is determined whether n = 9. If it is not 9, the process returns to step 403 and n = 9.
If so, the process ends.

FIG. 5 shows an example in which the input signal 701 is continuous data as in the synchronous system. In such a case, the data is first received after the synchronization with the synchronization character or the like, but when the signal is observed by the logic analyzer, only the middle of the long data is observed. Therefore, since character synchronization cannot be performed, the bit change point is used as the starting point to display the value of each bit, and the data break point specified by the observer moving the cursor is used as the second starting point (P5). ,
The observation is facilitated by dividing the data by a data length such as 8 bits or 7 bits and performing hexadecimal display for each data length.

FIG. 6 is a flowchart showing the operation of displaying the value of each data bit when the input signal 701 is a synchronous signal. The value of each bit of data is set to a high ("1") level or a low level. It is displayed at the (“0”) level, the change point from “0” to “1” or “1” to “0” is searched, and the position of the approximate middle point of each data bit is set with this point as the starting point (p5). The value of the midpoint is read out by calculation, and "0" or "1" is displayed. Since the data is continuous, it ends on the right side of the display screen of the display device 77.

That is, the change point detection circuit 78 is step 60.
After the pointer (P) is set to the left end of the display data at 1, the data of the portion where the pointer (P) is incremented by 1 is read from the data recording memory 75 at step 602,
In step 603, it is determined whether the read data has changed. If this does not change, step 6
02, and if changed, the process proceeds to step 604. In step 604, the reading position calculation circuit 79 sets the pointer (P) position as a starting point, then in step 605, sets the number of data recording samples per bit length to l _0, and then proceeds to step 606. In step 606, the reading position calculation circuit 79 sets 0 to n, and then proceeds to step 607 to calculate the midpoint position and convert it to an integer to obtain the midpoint position P. Next, the data reading circuit 80 reads the data of the position of the pointer (P) designating the calculated midpoint position P in step 608, and determines in step 609 whether this data d is 1 or not. If it is 1, the process proceeds to step 610, and if it is not 1, the process proceeds to step 611.

In step 610, the data reading circuit 80 causes the character generation circuit 81 to generate "1" and displays it at the midpoint position of the data on the screen of the display device 77 as shown in FIG. , Go to step 612. Data reading circuit 8
For 0, in step 611, the character generation circuit 81 generates "0", which is displayed at the midpoint position of the data on the screen of the display device 77 as shown in FIG. 5, and the process proceeds to step 612. In step 612, the reading position calculation circuit 79 increments n by +1 and sets it as new n, and then proceeds to step 613, where the displayed position is the display device 77.
It is determined whether or not the data displayed on the screen is the right end, and if it is not the right end, the process returns to step 607, and if it is the right end, the process ends.

FIG. 7 is a flow chart for hexadecimal display starting from the cursor position (Pc) when the input signal 701 is a synchronous signal. The observer operates external input means such as key operation (not shown). ) To move the cursor on the screen of the display device 77 to specify the cursor point PC, the data read by the cursor point (PC) is shifted by 1 bit and 8 bits are put together, and this is converted into a hexadecimal number. Then, the screen display is performed, and the process ends when the right end of the display screen of the display device 77 is reached.

That is, the reading position calculation circuit 79 executes step 7
01 to set the number of data recording samples per bit length to l
₀ and then, after setting n to 0 in step 702,
Go to step 703. The reading position calculation circuit 79 calculates the middle point position in step 703 and converts it into an integer to be P. The data reading circuit 80 reads the data from the memory 75 at the position of the pointer (P) designating the midpoint position P, creates the data synthesized by the shift operation at step 705, and then at step 706. n
Is incremented by +1 to make it a new n, and the process proceeds to step 707. In step 707, the data reading circuit 80 determines whether or not n is a multiple of 8, and if not, the process returns to step 703, and if it is a multiple of 8, the process proceeds to step 708. The data reading circuit 80 converts the combined data into a hexadecimal number, and the obtained hexadecimal number is generated by the character generating circuit 81 and is shown at the midpoint position of the data displayed on the display device 77 as shown in FIG. Is displayed, the process proceeds to step 709. In step 709, it is determined whether or not the display position is the right end of the data on the screen. If it is not the right end, the process returns to step 703, and if it is the right end, the process ends.

FIG. 8 shows an example in which the input signal 701 is a biphase signal. With this biphase signal,
The change point from "0" to "1" or "1" to "0" is at the midpoint of the 1-bit data, and may or may not change at the delimiter portion for each bit. "0" and "1"
Or when the combination of "1" and "0", 6 in the middle part
As shown in Nos. 1 and 62, there is a portion where the 1-bit length does not change. Therefore, as shown in the flow chart of FIG. 9, the length between the change points is measured from the left end of the display data, and when a long change point portion having a 1-bit length is detected, the start point (P
C). Paying attention to the fact that the latter half of the 1-bit length from this starting point (PC) becomes the value of the data of "0" or "1", by reading each 3/4 part of the 1-bit length, "0" or A value of "1" is displayed. Therefore, the calculation formula used in the reading position calculation circuit 79 is P _O + 3/4 ×
L _O + L _O × n → becomes an integer (rounded off). still,
The hexadecimal display for every 8 bits is the same as the example shown in FIG. 7.

FIG. 9 is a flowchart showing the display operation of the bit value of the biphase signal. Change point detection circuit 7
In step 901, after the pointer (P) is set to the left end of the display data in step 901, the data is read from the memory 75 while moving the pointer (P), and the first change point X1 is detected in step 902. After that, the second change point X
2 is detected in step 903. Then step 904
At the change point detection circuit 78, the change point is detected between the change points (X1 to X2).
Is calculated to determine whether this length is approximately 1 bit. If the length is approximately 1 bit, go to step 907; otherwise, go to step 906.
Go to. The change point detection circuit 78 sets X2 at step 906.
As the first change point and X1 as the first change point, and then step 9
Return to 03.

In step 907, the reading position calculation circuit 79
Is a starting point P6 which is an intermediate point between the change points X1 and X2. The reading position calculation circuit 79 sets the number of data recording samples per bit length to l _{0 in} step 908, and then proceeds to step 909. In step 909, the reading position calculation circuit 7
After setting 0 to n, 9 advances to step 910 to calculate the midpoint position and convert it to an integer to obtain the midpoint position P. Next, the data reading circuit 80 reads the data of the position of the pointer (P) designating the midpoint position P from the data recording memory 75 in step 911, and determines in step 912 whether this data is 1 or not. After that, if it is 1, the process proceeds to step 913. If it is not 1, the process proceeds to step 914. In step 913, the data reading circuit 80 causes the character generating circuit 81 to generate "1", which is then displayed on the display device 7.
8C is displayed at the midpoint position of the data on the screen of FIG. 7, and the process proceeds to step 915. Data reading circuit 8
0 is "0" by the character generation circuit 81 in step 914.
Is generated and displayed at the midpoint position of the data on the screen of the display device 77, and the process proceeds to step 915. Step 9
At 15, the reading position calculation circuit 79 increments n by +1 and then sets this as a new n before proceeding to step 916 to determine whether the displayed position is the right end of the data displayed on the screen of the display device 77. If it is not the right end, the process returns to step 910, and if it is the right end, the process ends.

Here, the serial communication speed is 240
In some cases, such as 0 bps or 4800 bps, the sampling speed of the logic analyzer cannot be converted into an integer. However, after calculating the reading position with high precision up to the decimal point as described above, it is possible to perform positioning without cumulative error by determining the actual reading position by performing integerization and determining the actual reading position. Observation is facilitated by the display of values and hexadecimal display according to the data length such as 8 bits.

According to the present embodiment, the data recording memory 7
When the serial data recorded in No. 5 is displayed on the display device 77, whether the display data is high level or low level is indicated by a high level "1" which is close to the corresponding portion of the display data. Since it is possible to simultaneously display a logical value of "0" indicating that the display data is converted into a hexadecimal number and displayed on the display device 77 at the same time, the observer can determine whether the display data is high level or low level. It is no longer necessary to look for it visually, and it is possible to observe data without burdening the observer and making mistakes in observation. Moreover, the fraction is adjusted even if the ratio between the first cycle for sampling when recording data in the memory 75 and the second cycle for sampling communication data measured from the signal speed is not an integer. As a result, it is possible to display the correct and easy-to-observe data even if the data is long.

FIG. 10 is a block diagram showing another embodiment of the logic analyzer of the present invention. 71 is the input signal 7
A sampling circuit for binarizing 01, 73 for a sampling counter for generating a data recording address, 74 for an oscillator for generating a sampling clock for address generation, 75 for a data recording memory for recording binarized data, and 76 for A data conversion circuit for converting the binarized data into display format data, 77 a display device for displaying the data recorded in the data recording memory 75, and 82 an input signal 701.
Input signal change point detection circuit that detects a change from “low level” to “high level” or “high level” to “low level”, 83 is a frequency dividing circuit that divides the sampling clock 704, and 84 is an input signal 701. It is a serial signal pattern detection circuit that outputs a trigger signal 303 when a serial signal pattern is compared with a specific reference pattern and becomes the same as the reference pattern.

Here, the input signal change point detection circuit 82 comprises a delay circuit 11 and an exclusive OR circuit 12. The frequency dividing circuit 83 includes a frequency dividing register 21, a down counter 22,
It is composed of an OR circuit 23 and a 1/2 divider circuit 24. The signal pattern detection circuit 84 includes a shift register 31, a reference data generation circuit 32, and a comparison circuit 33.

Next, referring to FIG. 1 using the signal waveforms of FIGS.
The operation of the logic analyzer shown in 0 will be described. Figure 2
FIG. 6 is a diagram showing operations of the input signal change point detection circuit 82 and the frequency dividing circuit 83. When the input signal change point detection circuit 82 receives one of the plurality of input signals 701 and detects the change point of the input signal 710 by the delay circuit 11 and the exclusive OR circuit (EX-OR) 12. , Divider circuit 8
At 3, the reset pulse signal 101 is generated. Frequency divider 83
Is composed of a frequency dividing register 21, which holds the frequency dividing number, a down counter 22, an OR circuit 23 and a 1/2 frequency dividing circuit 24, and a sampling clock 7 output from an oscillator 74.
The down counter 22 counts the pulse signal of 04, and when the count value reaches zero, the down counter 22 generates a borrow pulse 202. The borrow pulse 202 passes through the OR circuit 23 and the load input 203 of the down counter 22.
Is supplied to the down counter 22 at this point, and the value of the frequency dividing register 21 is loaded into the down counter 22, and the down counter 22 performs counting operation again from the new value. In addition, borrow pulse 202
Is also supplied to the 1/2 frequency dividing circuit 24 and divided into 1/2, and the signal pattern detection circuit 84 and the sampling circuit 71 are
However, the phase of the frequency-divided output 204 is inverted. The frequency-divided output 204 is sampled by the sampling circuit 71 in the same manner as the other signal input 701 and recorded in the data recording memory 75. On the other hand, the initialization pulse signal 1 which is the output from the input signal conversion point detection circuit 82.
01 is supplied to the load input 203 of the down counter 22 through the OR circuit 23. At this time as well, the value of the frequency dividing register 21 is loaded to the down counter 22 and
The frequency dividing circuit 24 is also reset by the initialization pulse signal 101, and the frequency dividing output 204 becomes "low level".

FIG. 11 is a time chart for explaining the counting operation of the frequency dividing circuit 83. At the transition points n1, n2, and n3 of the input signal 710 shown in FIG. 11A, the input signal conversion point detection circuit 82 generates initialization pulses S1, S2, and S3, respectively, as shown in FIG. 11B. ing. The input signal 710 is a 4800 bps serial signal,
The 1-bit data length is 20 as shown in FIG.
It is 8.33 μsec, and the cycle of the sampling clock 704 output from the oscillator 74 is 10 μsec. A value obtained by dividing the data length by twice the sampling clock cycle is rounded to an integer and set in the frequency dividing register 21. In this case, it is 10, and the down counter 22
When a count value becomes zero, a borrow pulse is generated and a new value is loaded, so that a borrow pulse is generated every 10 times counting. The frequency division output 204 is shown in FIG.
After S1 of the first initialization pulse 101 shown in (B),
As shown in FIG. 11C, at the point t1 of the 10th sampling pulse, the signal rises to “high level” and pulse 2
It drops at the 0th pulse, rises again at the 30th pulse, and falls at t2 at the 40th pulse.

Thereafter, the frequency dividing circuit 83 is initialized at S2 of the initialization pulse 101 shown in FIG. 11 (B). Figure 11
As shown in (C), it takes 400 μs from S1 to t2, and if the input signal 710 has no change point, the frequency division output 2
Although 04 is a positive multiple of 200 μsec, the change point n2 shown in FIG. 11A, that is, the first change point n1 to 416.6.
At a point of 7 μs, an initialization pulse S2 is generated as shown in FIG. 11B to initialize the frequency dividing circuit 83. Therefore, the deviation of the synchronization with the input signal 710 due to the numerical value set in the frequency dividing register 21 being limited to an integer can be corrected. Similarly, the next rising t3 of the divided output 204 shown in FIG. 11C is 10 counts from the S2 point of the initialization pulse 101 shown in FIG. 11A, and the rising point t4 is 20 counts from the S2 point, that is, It is after 200 μs. However, the frequency-dividing circuit 20 is re-initialized at 208.33 μsec from S2 by the initialization pulse S3 generated next. In the serial signal pattern detection circuit 84, the shift register 31 operates at the rising point of the frequency-divided output 204, fetches the value of the input signal 710, and sequentially performs the shift operation. The comparison circuit 3 compares the parallel output of the shift register 31 and the data of the reference data register 32, which is a reference for comparison.
3, and when both data match, the comparison circuit 3
3 outputs the trigger signal 303 to the sampling counter 73. Accordingly, the sampling counter 33 outputs the write address to the memory 75 and records the serial data binarized by the sampling circuit 71.

FIG. 12 shows an example of comparison of data when the input signal is the start / stop synchronization signal. When the data is 8-bit start / stop synchronization as shown in FIG. 12 (A), 1 is added before the data.
A bit start bit (ST) is followed by one or two stop bits (not shown in the figure). Therefore, the comparison circuit 33 makes a mistake in the comparison of only 8 bits of the data portion, and the coincidence point K1 shown in FIG.
However, the trigger signal 303 is generated. But,
If a match is detected with 9 bits including the start bit (ST), then under this condition, there is a mismatch as in K2 shown in FIG. 12B, and errors are reduced.

Of course, it is best to operate after synchronizing by detecting the start bit correctly like an ordinary receiving circuit, but having a large number of receiving circuits depending on communication conditions is expensive as a measuring device. There is a drawback that Further, when there is a synchronization word only in a specific location of long communication data such as word synchronization, it may not take a period as a measuring device that wants to observe only a part of the long communication data. Rather, it is normal for the observer to easily judge that an incorrect coincidence point is incorrect,
If the frequency of error occurrence is low, there will be no obstacle. Although an inexpensive and general-purpose method has been described here, there is no problem even if a plurality of receiving circuits are used according to communication conditions.

In FIG. 13, after the serial communication data as described above is recorded in the recording memory 75, the data conversion device 7
In the example shown in FIG. Here, the communication data 7 shown in FIG.
In addition to 10, the frequency division output 204 shown in FIG. 13A is also sampled and displayed at the same time, and the sampling circuit 71 outputs the input data 7 at the rising time of the frequency division output 204.
Read the value of 10. This data reading is also performed by the serial signal pattern detection circuit 84 to detect a specific data pattern. In the example of the display screen of FIG. 13, when converting the data for display by the data conversion circuit 76, the value of the data is read and the value of each bit of “0” or “1” is displayed. Here, the data length is 8 bits. , 8 bits are collectively converted into hexadecimal numbers and displayed.

FIG. 14 is a flow chart showing the operation of performing such display. In step 141, the sampling circuit 71 causes the trigger point (tg) shown in FIG.
The rising point of the frequency-divided output 204 is detected from the point of 167 points before, and the first rising point a1 is detected. Since the value of the input data 710 at this point is “0”, which is the start bit, the data conversion circuit 76 causes the step 14
In step 2, "S" is displayed on the screen of the display device 77 as shown in FIG. Sampling circuit 71 is step 1
When the next rising point a2 is detected at 43 and the data is read, it is "0". Therefore, at step 144, it is judged that there is no change from 1 to 0, the process jumps to step 146, and the display position is not the right end of the screen. If so, the process returns to step 143 to continue the same operation. In this example, since the data length is 8 bits, 8 bits excluding the start bit are collectively converted into a hexadecimal number and displayed on the display device 77. Next is Fig. 13
As shown in (B), there is a stop bit and a section with no data of indefinite length. In this section, all are "high level", that is, "1". Therefore, the sampling circuit 71 determines that there is a change of 10 in step 144, displays “S” on the display device 77 in the same manner as above in step 145, and proceeds to step 146 to display position. If is not the right end, the process returns to step 143, and the bit data display is continued from here as in the above. If the display position is the right end, the process ends.

FIG. 15 is a flow chart showing details of the character display shown in FIG. In step 151, the data conversion circuit 76 sets the number of data storage samples per bit length to l _0, and in step 152, sets a numerical value 0 to initialize the variable n, and then proceeds to step 153.
In step 153, the pointer (P) is incremented by 1 and the data of the frequency division output 204 is read from the memory 75. Then, in step 154, it is determined whether or not the data is on the rising edge. If it is a rising edge, the process proceeds to step 155.
The data conversion circuit 76 reads the data of the input signal 710 at the rising point from the memory 75 in step 155 and sets it as d0, and then proceeds to step 156. In step 156, it is determined whether or not n = 0. If it is 0, in step 159 the start bit S is displayed on the screen of the display device 77 as shown in FIG.
Go to step 162. When it is determined in step 156 that n = 0, the process proceeds to step 157, where the data is combined by the shift operation to be d1 and then the process proceeds to step 158. In step 158, it is determined whether or not the read data is 1, and if it is 1, the process proceeds to step 160, and if it is not 1, the process proceeds to step 161.
In step 160, “1” is displayed on the screen of the display device 77 as shown in FIG. 13B, and the process proceeds to step 162. In step 161, “0” is displayed on the screen of the display device 77 as shown in FIG.
Proceed to. Next, in step 162, n is incremented by +1 and set to a new n. Then, the process proceeds to step 163 to determine whether or not n = 9. If it is not 9, the process returns to step 154 and n = 9. If so, step 164
Go to. In step 164, the value of the data d1 is displayed in hexadecimal on the display device 77, and the process ends.

According to this embodiment, the divided signal 20
By reading the serial data which is the input signal 710 at 4, it is possible to easily detect the communication data under various conditions without providing a dedicated receiving circuit adapted to the communication conditions. 710
Is the same as the pattern generated by the reference data generating circuit 32, the comparator circuit 33 outputs the trigger signal 303 to the sampling counter 73 to start recording the binarized data of the input signal 710. Since this is displayed on the display device 77 through the data conversion circuit 76, it is not necessary for the observer to visually select a specific pattern of the serial signal, and it is possible to perform the serial operation without burdening the observer and without causing an observation error. You can observe specific patterns in the data. Further, the sampling clock 704 is divided by the frequency dividing circuit 83, and the difference from the communication speed is determined by the frequency dividing circuit 83 at the change point of the communication data.
Since the error is prevented from increasing by initializing, the signal change before and after the trigger point can be observed in detail. Further, observation can be further facilitated by displaying the value of each bit of the communication data or the value of the data in which 8 bits are collected as a hexadecimal number.

In the above description, the start bit is an asynchronous method, the data length is 8 bits, and the communication speed is 4800.
This was done for bps. Therefore, the 1-bit signal length is 208.33 μsec, and the 8-bit length is 1666.67.
Since it is .mu.sec and the sampling cycle is 10 .mu.sec, 166.667 is rounded up, and the rising point of the frequency-divided output 204 is checked from before the trigger point by 167 points. However, the method is not limited to this method, and it is possible to start from the left end of the screen, or start from an arbitrary point and the input signal 710 continues to be at “1” level for a certain length of time and then to “0”.
The point changed to may be used as the start bit. The purpose of this data display is to facilitate observation, and even if there is some display error, it can be easily recognized by the observer, so there is little concern. Also, even if there is a start bit like the start / stop synchronization signal, but it is quite difficult to recognize the data delimiter in the middle of a long continuous data like the character synchronization signal, bit data of "0" or "1" It is possible to facilitate the observation by displaying only, or by displaying the hexadecimal number by recognizing the group for each data length based on the trigger point which is the data pattern matching point.

[0041]

As described above, according to the logic analyzer of the present invention, it is possible to calculate the data length of serial data, detect the value of each bit, and display close to the relevant portion of the data displayed on the screen. Thus, the observer can easily and surely recognize the value of the data, and the input signal can be recorded and displayed by generating the trigger only when the serial signal of the specific pattern is input.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a logic analyzer of the present invention.

FIG. 2 is a diagram showing an example of a case where the input signal shown in FIG. 1 is a start / stop synchronization signal.

3 is a flowchart showing the operation of detecting the start point of the start / stop synchronization signal by the apparatus of FIG.

FIG. 4 is a flowchart showing a detailed example of step 304 shown in FIG.

FIG. 5 is a diagram showing an example of a case where the input signal shown in FIG. 1 is continuous data as in a synchronous system.

FIG. 6 is a flowchart showing an operation of displaying each data bit value when the input signal shown in FIG. 1 is a synchronous signal.

FIG. 7 is a flowchart for displaying hexadecimal from the cursor position (Pc) when the input signal shown in FIG. 1 is a synchronous signal.

FIG. 8 is a diagram showing an example when the input signal shown in FIG. 1 is a biphase signal.

FIG. 9 is a flowchart showing a display operation of a bit value of a biphase signal.

FIG. 10 is a block diagram showing another embodiment of the present invention.

11 is a time chart explaining the counting operation of the frequency dividing circuit shown in FIG.

12 is a diagram illustrating a pattern detection operation of the signal pattern detection circuit shown in FIG.

13 is a diagram showing a display example in which an input signal, a divided signal, bit data and the like are displayed on the display device 77 shown in FIG.

14 is a flowchart showing an operation of displaying an input signal pattern and the like in the device shown in FIG.

15 is a flowchart showing a detailed example of the character display step shown in FIG.

FIG. 16 is a block diagram showing an example of a conventional logic analyzer.

FIG. 17 is a waveform chart showing an example when the input signal shown in FIG. 16 is NRZ type serial data.

FIG. 18 is a circuit diagram showing a detailed example of the trigger detection circuit shown in FIG.

[Explanation of symbols]

11 ... Delay circuit 12 ... Exclusive OR circuit 21 ... Dividing register 22 ... Down counter 23 ... OR circuit 24 ... 1/2 divider circuit 31 ... Shift register 32 ... Reference data generating circuit 33 ... Comparison circuit 71 ... Sampling circuit 72 ... Trigger point detection circuit 73 ... Sampling counter 74 ... Oscillator 75 ... Data recording memory 76 ... Data conversion circuit 77 ... Display device 78 ... Change point detection circuit 79 ... Reading position calculation circuit 80 ... Data reading circuit 81 ... Character generating circuit 82 ... Input signal change point detection circuit 83 ... Frequency divider circuit 84 ... Signal pattern detection circuit

Claims (2)

[Claims] 1. A logic analyzer for sampling an input signal at a predetermined sampling period and storing it in a memory, and then displaying the data stored in the memory, in a change inspection for detecting a level change point of the data stored in the memory. Output means, calculating means for calculating the position for reading the level of the data based on the change point detected by the change point detecting means and the length per bit of the data designated in advance, and the calculating means. The data reading means for reading the level of the display data at the calculated reading position, the character generating means for generating a character indicating the level of the data read by the data reading means, and the character generated by the character generating means are described above. Display means for displaying in close proximity to a corresponding portion of the display data. Logic analyzer. 2. A logic analyzer for sampling an input signal at a predetermined sampling period and storing it in a memory, and then displaying the data stored in the memory, by dividing a sampling clock for sampling the input signal. Frequency dividing means, initialization means for detecting a change point of the input signal to initialize the frequency dividing means, and after dividing the input signal into parallel data by a frequency dividing clock output from the frequency dividing means, Comparing means for comparing with the reference data and, after a predetermined time from the time point when the comparing means determines that the two data match, stop the informed operation of storing the sampled input signal in the memory. A logic analyzer comprising a control means.