JPH0772892B2 - Memory address allocation management method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory address allocation management system, and in particular, a processor unit including a processor and a main memory and other device modules are respectively connected via a common bus. The present invention relates to a memory address allocation management system for a main memory in each processor unit when viewed from the common bus side in a multiprocessor system capable of connecting a plurality of units.

[Conventional technology]

In the multiprocessor system as described above, the processor in each processor unit can, of course, access the main memory in its own unit, but other processor units or other device modules connected to the common bus Can be accessed in exactly the same procedure as accessing the main memory in its own unit, that is, by one machine language instruction of the processor, and the main memory in the processor unit In some cases, not only can it be accessed by the processor to which it belongs, but it must also be accessible by some other processor unit or other device module connected to the common bus.

As a method capable of responding to such a request, in the conventional technology, a certain common address space range among the address spaces of the processors in each processor unit is fixedly allocated for the main memory in each processor unit. , The remaining part of the address space of the processor is commonly assigned to each processor for the common bus address space, and the address area occupied by various device modules on the common bus address space and each processor unit The main memory address area is allocated so that it does not overlap depending on the memory capacity of the mounted memory.

FIG. 4 shows an address allocation method for a system including three processor units as an example. In this figure, of the address spaces (addresses 0 to C) of the processor of each processor unit, the space (addresses 0 to (A
-1) address), and addresses A through C are assigned as a common bus address space (addresses A to C).

An area corresponding to the capacity of the main memory mounted in the processor unit a (M ₁ byte) is allocated to the area (a ′ _M ) of addresses A to (A + M ₁ −1) of the common bus address space, and to the processor unit b. The area of the installed main memory capacity (M ₂ bytes) is allocated to the area (b ' _M ) of addresses (A + M ¹ ) to (A + M ₁ + M ₂ -1) of the common bus address space, and to the processor unit C. The amount of installed main memory (M ₃
The byte area is (A + M ₁ +) of the common bus address space.
M ₂₎ Address _{~ (A + M 1 + M} 2 + M 3 -1) are assigned respectively to the address of the area (C _'M). The occupancy of various device modules other than the processor unit is allocated to the area (n) of addresses B to C of the common bus address space.

From the viewpoint of the processor in each processor unit, the address allocation as described above is not limited to the main memory in its own unit, and the area for all main memories mounted in other processor units and other device modules. It means that the processor is placed in the address space that can be directly accessed. As a result, the processor of each processor unit can access the main memory mounted in another processor unit in exactly the same way as it accesses the main memory in its own unit. Other device modules having a bus master function can also access the main memory in each processor unit by accessing the area allocated in the common bus address space.

FIG. 5 is a configuration example of a system for realizing the above method. The processor units 1a to 1c are respectively connected to the common bus 2 and the processors in the respective processor units are connected.
4a to 4c are connected to the main memories 6a to 6c and the common bus 2 via bus switches 5a to 5c, and any one of a pair of couplings is selected by the bus switches 5a to 5c. The internal address comparison circuits 7a to 7c are the processors 4a to
If the address value output from 4c is smaller than a predetermined value (value "A" in FIG. 4) determined by hardware in advance, the processors 4a to 4c and the main memories 6a to 6c.
Is a circuit that controls the bus switches 5a to 5c so as to connect with each other, and otherwise controls the bus switches 5a to 5c so as to connect between the processors 4a to 4c and the common bus 2.

The registers 9a to 9c are the start addresses (of the areas allocated in the address space where the main memories 6a to 6c of the processor units 1a to 1c are treated as the common bus address space among the address spaces of the processors ( Fourth
As shown in the figure, "A" is assigned to register 9a, "A + M ₁ " is assigned to register 9b, and "A + M ₁ + M ₂ " is assigned to register 9c). 8a~8c, as shown in the last address (Fig. 4 of the area, the register _{8a "a + M 1 +1"} , "a + M 1 + M 2 -1" in the register 8b, the register _{8c "a + M 1 + M} 2 ＋ M ₃ −
1 "is assigned to each of them). Here, the registers 9a to 9c and 8a to 8c may both be switches.

The common bus address comparison circuits 10a to 10c are provided with the address value given from the common bus 2 and the registers 9a to 9c and the registers.
8a to 8c are compared, and if the address value given from the common bus 2 is within the area specified by the contents of registers 9a to 9c and the contents of registers 8a to 8c, the common bus and main memory It has a function of controlling the bus switches 5a to 5c so as to be coupled with 6a to 6c, and not performing the above control unless it is within the range of this area. (Concerning the common bus address comparison circuit 10a based on FIG. 4, if the common bus address value is within the range of "A to (A + M ₁ -1)", the bus switch 5a includes the common bus 2 and the main memory. The address subtraction circuits 11a to 11c subtract the contents of the registers 9a to 9c from the address value given from the common bus 2 and 0 to be given to the main memories 6a to 6c. It is a circuit that converts to a relative address that starts. The converted values are the bus switches 5a to 5c.
When the common bus 2 and the main memories 6a to 6c are coupled by the above, the common bus address is replaced and the data is given to the main memories 6a to 6c.

Now, the processor 4a in the processor unit 1a is
When an address is output while trying to access something, the address value is compared with the fixed value of hardware (the value "A" shown in FIG. 4) in the internal address comparison circuit 7a, and the address value is determined from this fixed value. If it is small, the bus switch 5a connects the processor 4a and the main memory 6a based on the instruction of the comparison circuit 7a, and gives the address output by the processor 4a to the main memory 6a.
Can access a predetermined address in the main memory 6a.

On the other hand, as a result of the comparison in the comparison circuit 7a, when the address value is equal to or larger than this fixed value, the comparison circuit 7a instructs the bus switch 5a to connect the processor 4a and the common bus 2 and the processor 4a The output address is output to the common bus 2. Processor units 1b and 1c
Receives the address of the common bus, and in the common bus address comparison circuits 10b and 10c, the value is registered in the register 9 respectively.
Whether or not it is within the range specified by the contents of b and 9c and the contents of registers 8b and 8c is determined.

Now, assuming that the common bus address comparison circuit 10b determines that the common bus address value is within the range determined by the registers 9b and 8b, the bus switch of the processor unit 1b.
5b couples the common bus 2 and the main memory 6b based on the command from the common bus address comparison circuit 10b, and the address converted by the address subtraction circuit 11b by this is stored in the main memory 6b as the main memory address. Therefore, the processor 4a of the processor unit 1a is connected to the bus switch 5
main memory 6b via a, common bus 2, and bus switch 5b
Can be accessed to a predetermined address.

On the other hand, in the common bus address comparison circuit 10c of the processor unit 1c, naturally, the common bus address value is set in the registers 9c and 8c.
Therefore, the bus switch 5c does not receive the bus switching command, and no accessed operation is performed. The various device modules 3a and 3b other than the processor units 1a to 1c also receive the common bus address, and the ones selected thereby are accessed by the processors 4a to 4c. Here, each processor unit 1a
The area on the common bus address space defined by the contents of the registers 9a to 9c and the registers 8a to 8c of ~ 1c, and the area occupied by other device modules on the common bus address space must not overlap. It should be noted that this is a prerequisite.

In the address allocation method described above, the area for the capacity of the main memory mounted in each processor unit is allocated to the common common bus address space among the address spaces of the processors in each processor unit. As a result, the total capacity of the main memory that can be mounted on each processor unit is limited by the size of the common bus address space.

For example, in FIG. 4, the total capacity of the main memory of each processor unit is limited by the following equation.

M ₁ + M ₂ + M ₃ ≦ B−A This means the size of the internal address space for the main memory for the processor to directly access the main memory in its own unit without passing through the common bus, and the main memory installed in each processor unit. This imposes great restrictions on the capacity of the system and the number of processor units that make up the multiprocessor system, which is a problem in constructing the system.

[Problems to be Solved by the Invention]

An object of the present invention is to set the size of the internal address space for the main memory (the size common to each processor unit) for the processor of each processor unit to directly access the main memory in its own unit when constructing a multiprocessor system. ) Or a common bus address space that is a part of the address space of the processor of each processor unit such that the restrictions on the capacity of main memory that can be mounted on each processor unit and the number of connected processor units are extremely small. It is to provide a memory address allocation management system for the main memory of the processor unit.

[Means for Solving the Problems]

A plurality of processor units having a processor and a main memory are connected to a common bus together with other device modules, and the common bus side is connected in the same procedure as the processor in each processor unit accesses the main memory in its own processor unit. In a multiprocessor system configured to be accessible, an address translation memory is provided between a main memory of each processor unit and a common bus interface unit, and common bus address information can be designated for each processor unit without duplication. Of the address translation memory, a second bit area for address translation memory access, and a third bit area for designating an in-page address of the main memory.
It has a bit width that can cover the size of the main memory address space in its own processor unit, and consists of a memory area in which information can be set and changed by the own processor. The information of the second area of the address information is stored as an address, and the information of the second area of the common bus address information is accessed and the information of the second area is stored in a predetermined area of the main memory in the own processor unit. The processor unit is configured to output the page address information of the area and output it to the main memory. Each processor unit outputs the information of the first area output on the common bus to the address set on the common bus for its own processor unit. If it is included in the range, the address translation memory is accessed by the information of the second area output on the common bus to access the page address. By giving information to the main memory as information and the information of the third area output on the common bus as the in-page address to the main memory, the main memory in the processor unit outputs the common bus address information to the processor unit or It is also accessible from other device modules via the common bus.

[Work]

According to the present invention, by providing an address translation memory in each processor unit, it is possible to translate a given common bus address into an arbitrary main memory address in the unit, so the capacity of the main memory of each processor unit Need not be allocated in the common bus address space for accessing the main memory in the processor unit from the common bus, and only a smaller area needs to be allocated regardless of the capacity of each main memory. .
Therefore, it is possible to construct a multiprocessor system having a large degree of freedom, because restrictions on the capacity of the main memory mounted on the processor unit and the number of processor units connected to the common bus are extremely loose.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and illustrates an address allocation method of a main memory of each processor unit according to the present invention when applied to a multiprocessor system including four processor units. This figure shows the address space of the processor of each processor unit is 16
8 megabytes of addresses 0 to (D-1) are allocated as the internal address space for the main memory as megabytes (addresses 0 to J), and the remaining 8 megabytes (addresses D to J) are shared bus address space. The example is assigned as.

The processor unit a has a capacity M of ₁₁ bytes in the area a _M , the processor unit b has a capacity of M ₁₂ bytes in the area b _M , the processor unit c has a capacity M of ₁₃ bytes in the area c _M , and the processor unit d has a capacity of M d in the area d _M. The main memory with a capacity of M ₁₄ bytes is mounted, and the processor of each processor unit can directly access the main memory in its own unit by accessing the internal address space for main memory below address D. it can. When each processor accesses at address D or higher, it becomes an access to the common bus address space.

On the common bus address space, a certain area is allocated for each processor unit without duplication, and this area is used as an area for accessing the main memory in each processor unit from the common bus side. Hereinafter, this will be referred to as a window area, the window area for the processor unit a is a _M ″, and the window area for the processor unit b is
Let b _M ″, the window area for processor unit c be c _M ″, and the window area for processor unit d be d _M ″.
In the figure, the window area provided for each processor unit occupies an area of 1 megabyte in the common bus address space. The occupancy of various device modules other than the processor unit is allocated to addresses I to J of the area n of the common bus address space.

Now, when a processor of a processor unit tries to access the main memory in another processor unit, it is supposed to access a window area for a desired processor unit in the common bus address space. Similarly, the main memory in the desired processor unit can be accessed by accessing the window area from other device modules as well.

FIG. 2 shows an embodiment of the system configuration according to the present invention which enables the address allocation described above, and particularly shows mainly the address bus system in the processor unit. In FIG. 2, the processor unit 1b
Illustrations of 1 and 1c are omitted.

The processor units 1a to 1d are respectively connected to the common bus 2, the processors 4a to 4d in the processor unit are connected to the main memories 6a to 6b via the buffer gates 21a to 21c, and the common buses via the buffer gates 22a to 22d. Connected with 2. Further, the main memories 6a to 6d are the address translation memories 27
It is also connected to the common bus 2 via a to 27d and buffer gates 23a to 23d. The gates of the buffer gates 21a to 21d, the buffer gates 22a to 22d, and the buffer gates 23a to 23d are enabled / disabled by the bus switching control circuits 20a to 2
Controlled by 0d.

The internal address comparison circuits 7a to 7d compare the value of the address output from the processors 4a to 4d with a fixed value (a value "D" in FIG. 1) determined in advance by hardware, and The result is given to the bus switching control circuits 20a to 20d. When the address value of the processor output is smaller than this fixed value, the bus switching control circuits 20a to 20d have the buffer gate 21
By enabling a to 21d, the processors 4a to 4d and the main memories 6a to 6d are coupled. Also, if not,
The bus switching control circuits 20a-20d enable the buffer gates 22a-22d to couple the processors 4a-4d with the common bus 2. (Note that the access from the processors 4a to 4d to the main memories 6a to 6d and the common bus 2 in the own unit is basically the same as the conventional technique.) The registers 25a to 25d are common buses for each processor unit. Of the window area provided in the address space,
This is a register that stores the values of several high-order bits of the common bus address information indicating the window area for its own processor unit (the number of bits differs depending on the size of the window area). (Note that the registers 25a to 25d may be switches.) The common bus address comparison circuits 24a to 24d compare the address value given from the common bus 2 with the contents of the registers 25a to 25d, and both match. In case of bus switching control circuit 20a-2
Command 0d to enable buffer gates 23a-23d to couple main memories 6a-6d and address translation memories 27a-27d. The address translation memories 27a to 27d are
Common bus 2 and processor via selectors 26a-26d
Connected with 4a-4d. The address translation memories 27a to 27d are
It is allocated to a predetermined area in the main memory internal address space of the address space of the processor, and the processors 4a to 4d are assigned to the address translation memories 27a to 27d.
When this area is accessed to set or change the contents within, the selectors 26a-26d cause the processor 4
The addresses a to 4d and the address translation memories 27a to 27d are switched so as to be coupled, and the address of the processor output is given to the address translation memory side. This allows processors 4a-4d
Can access the address translation memories 27a to 27d.

The signal SEL is invalid except when the processors 4a to 4d access the address translation memories 27a to 27d, and the selector 26a
.About.26d operate to connect the common bus 2 and the address translation memories 27a to 27d, and supply the common bus address to the address translation memory. Address translation memory 27a-27d
Has a predetermined capacity in accordance with the size of the main memory internal address space.
~ 4d stores the conversion address value, and the output value from the memory cell corresponding to the address given to the address conversion memory is supplied to the main memories 6a to 6d via the buffer gates 23a to 23d. There is.

FIG. 3 explains the process of address translation.
This figure corresponds to the address allocation shown in FIG. First, it is assumed that the main memory internal address space (8 megabytes) in the processor unit is subjected to paging management in units of 4 kilobytes per page. The upper 4 bits (bit 23
~ Bit 20) is used to determine whether or not the window area for accessing the main memory in the own unit is selected, and all 8 bits of bit 19 to bit 12 are addresses given to the address translation memory, that is, address translation. It becomes the index pointer of the table, and all 12 from bit 11 to bit 0
The bits are directly provided to the main memory as an in-page offset. The address translation table (memory) stores up to 256 pieces of 11-bit page information (page number). Then, the page information stored in the table designated by the index pointer is given to the main memory as bits 22 to 12 of the main memory address. Most significant bit of main memory address (bit 23)
Is given to the main memory as "0". In this way, the main memory address to be given to the main memory is formed from the given common bus address.

It is now assumed that the processor 4a of the processor unit 1a tries to access the main memory in the processor unit 1d. Processor 4a is a buffer gate
22a is coupled to the common bus 2 by being enabled, and the address pointing to the window area d _M ″ (FIG. 1) for the main memory access of the processor unit 1 d is set to the common bus 2
Print on top. The processor units 1b-1d receive the common bus address and receive the common bus address comparison circuits 24b-2.
In 4d, the upper 4 bits (bit
23 to bit 20) and contents of registers 25b to 25d (4 bits)
However, it is only the common bus address comparison circuit 24d of the processor 1d that determines that they coincide with each other, and the others do not react. At the same time, all 8 bits from bit 19 to bit 12 of the common bus address received by the processor unit 1d are given to the address translation memory 27d via the selector 26d, and the address translation memory 27d receives all the bits from the memory selected by it. Outputs 11-bit page information.
Then, in response to the notification of the match determination from the common bus address comparison circuit 24d, the bus switching control circuit 20d causes the buffer gate 2
3d is enabled, and this page information and all 12 bits from bit 11 to bit 0 of the common bus address as an in-page offset are given to the main memory 6d. At this time, the address bit 23 is also given a value "0" to the main memory 6d via the buffer gate 23d. (Not shown in FIG. 2).

In this way, the processor 4a of the processor unit 1a
Can access a predetermined address of the main memory in the processor unit 1d. Access to the main memory in the processor unit from various device modules 3a, 3b other than the processor unit is processed in exactly the same manner.

Here, in principle, the contents of the conversion between the common bus address and the internal main memory address are managed by the processor in the processor unit on the side of access. Therefore,
Normally, the processor and other device modules in the processor unit try to access the main memory in a processor unit, and output a common bus address pointing to the corresponding window area. It is not directly known where in the main memory it is converted and accessing. However, in this type of multiprocessor system, when the processor unit exchanges data with various device modules (input / output control device, communication control device),
Generally, the processor unit gives the device module, together with the command, address information about the main memory in its own unit to which data is transferred,
As long as the processor unit that issues the command manages all of them, the device module only needs to access based on the address information given by the processor unit, and does not need to particularly know where to access in the main memory. In addition, it is common for one processor unit to access the main memory of another processor unit as so-called inter-processor communication. In that case, the area of the main memory to be accessed is the inter-processor communication. It can be limited according to the role of. Therefore, there is no problem if a fixed conversion value is stored in a fixed memory of the address conversion memory so that it is known to all processor units only for inter-processor communication.

〔The invention's effect〕

As described above, according to the present invention, a plurality of processors having a processor and a main memory are connected to a common bus together with other device modules, and the address space of the common bus is within the address space of the processor of each processor unit. Is allocated in common, and the processor uses the same procedure as the main memory access in its own processor unit.
That is, in a multiprocessor system that can access the common bus side with one machine language instruction of the processor,
An address translation memory is provided between the main memory of each processor unit and the common bus interface section, and a common bit address information can be designated for each processor unit without overlapping a first bit area and a second address translation memory access second area. The address translation memory has a bit width capable of covering the size of the main memory address space in its own processor unit. Then
It consists of a memory area where information can be set and changed by its own processor, and the page address information of each area of the main memory is stored using the information of the second area of the common bus address information as an address. The processor unit is configured to be accessed by the information of the second area, convert the information of the second area into page address information of a predetermined area of the main memory in the own processor unit, and output the page address information to the main memory. When the information of the first area output on the common bus is included in the range of the address set on the common bus for its own processor unit, the information of the second area output on the common bus is used. The address translation memory is accessed and given to the main memory as page address information, and the information of the third area output on the common bus is paged. Since the internal address is given to the main memory, each processor unit can convert the given common bus address into an arbitrary main memory address within the unit. Therefore, each processor unit provided in the common bus address space For the main memory access area of, regardless of the capacity of the main memory of each processor unit, only a very small area needs to be allocated.
Due to the limited size of the common bus address space, the restrictions on the amount of main memory that can be installed in the processor unit and the number of processor units that can be connected to the common bus are extremely relaxed, and a large amount of main memory can be saved. The effect that it becomes possible to construct a multiprocessor system composed of a large number of processor units is provided.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of memory address allocation according to the present invention, FIG. 2 is a configuration diagram of an embodiment of a multiprocessor system according to the present invention, and FIG. 3 is based on the memory address allocation and system embodiment according to the present invention. FIG. 4 is an explanatory diagram of an address conversion process, FIG. 4 is a diagram showing a concept of memory address allocation according to the conventional method, and FIG. 5 is a diagram showing an example of a configuration of a conventional multiprocessor system. 1a to 1d ... Processor unit 2 ... Common bus 3a, 3b ... Various device modules 4a to 4d ... Processor 6a to 6d ... Main memory 7a to 7d ... Internal address comparison circuit 20a to 20d ... Bus switching control Circuits 21a to 21d, 22a to 22d, 23a to 23d ...... Buffer gates 24a to 24d ...... Common bus address comparison circuits 25a to 25d ...... Registers 26a to 26d ...... Selectors 27a to 27d ...... Address translation memory

Claims (1)

[Claims] 1. A procedure similar to that in which a plurality of processor units having a processor and a main memory are connected to a common bus together with other device modules, and the processor in each processor unit accesses the main memory in its own processor unit. In a multiprocessor system configured to access the common bus side with, an address translation memory is provided between the main memory of each processor unit and the common bus interface section, and common bus address information is shared between the processor units without duplication. The address translation memory is composed of a first bit area that can be designated, a second bit area for accessing the address translation memory, and a third bit area that designates an in-page address of the main memory. The size of the main memory address space in It has a bit width that can be set and can be set and changed by the processor itself, and the page address information of each area of the main memory stores the information of the second area of the common bus address information as an address. The information of the second area of the common bus address information is accessed, the information of the second area is converted into page address information of a predetermined area of the main memory in the own processor unit, and output to the main memory. And each processor unit has a first output on the common bus.
When the information of the area of is included in the range of the address set on the common bus for its own processor unit, the address translation memory is accessed by the information of the second area output on the common bus to access the page address. The third information output to the common bus while being given to the main memory as information
A memory address allocation management method characterized in that the information in the area is mainly given to the memory as in-page addresses.