JPH0773162A - Performance monitor of information processor - Google Patents

Abstract

PURPOSE:To facilitate the tuning up of a program by quantitatively grasping a memory access load which owes much to the intuition of a program preparing person in a super computer, etc. CONSTITUTION:Memory units 3-0 to 3-3 can simultaneously be accessed through a memory control part 2 from CPU 1. The memory access control part 2 decodes memory access requirement from CPU 1 so as to judge to which one of the memory units 3-0 to 3-3 a request to be sent in accordance with the kind and the address of the request to be accessed. Counters 6-0 to 6-3 counting access to the memory units 3-0 to 3-3 and a counter 5 counting a signal obtained by ORing request signals to the memory units 3-0 to 3-3 are provided and all these counters can be referred to from CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a performance monitor for performance evaluation and performance measurement of an information processing device.

[0002]

2. Description of the Related Art In recent years, so-called vector computers, which mainly deal with array calculations, have begun to be used.
In order to effectively use the vector computer, it is necessary to be familiar with its characteristics and rewrite the program so that the vector computer can maximize its performance.
One of the characteristics to be familiar with is the load on the program memory.

Particularly, as a recent tendency, for speeding up,
In many cases, a multiprocessor configuration in which a memory is shared is adopted, but it is known that in such a system of a memory sharing type multiprocessor configuration, a serious processing performance fixed price may be caused due to memory competition. One way to avoid this performance fixed price is to secure sufficient memory throughput, but this requires enormous cost in both development and manufacturing, and it does not always lead to a superior price-performance ratio. .

Therefore, it is advantageous in terms of realization to avoid the fixed price of the performance by changing the program so that the memory competition does not easily occur. However, in order to do so, it is necessary to let the program creator know in which part of the program the memory contention is likely to occur, but heretofore, there has been no means for knowing such information.

[0005]

As described above, conventionally, there is no means for notifying the program creator of information in which part of the program the memory contention is likely to occur, and the program creator often relies on the intuition of the program creator. Therefore, there is a problem that the fixed price of the processing performance cannot be avoided with the corresponding cost.

[0006]

The performance monitor of the present invention comprises:
A performance monitor of an information processing apparatus including a memory device including a plurality of memory units that can operate independently at the same time, and an information processing device including one or more arithmetic processing devices, the access request to the memory device from the arithmetic processing device. To a corresponding memory unit, and a counting unit corresponding to the arithmetic processing unit that advances when a request signal is sent to any of the memory units. Characterize.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 showing a first embodiment of the present invention, the present embodiment has a CPU 1 and a memory access control unit 2.
, Four memory units 3-0, 3-1, 3-2 and 3-3, an OR circuit 4, and five counters 5, 6-
It is composed of 0, 6-1, 6-2 and 6-3.

The CPU 1 is an arithmetic processing unit that interprets and executes instructions, and issues a memory access request to the memory access control unit 2 via a connection 101 when executing an instruction that refers to a memory and when fetching an instruction from the memory. Send out.

When the memory access control unit 2 receives a memory access request from the CPU 1, the memory access control unit 2 requests the memory units 3-0 to 3-3 corresponding to the request address from the CPU 1 via connection lines 102-0 to 102-3, respectively. Is sent.

Memory access requests from the CPU 1 include scalar data access requests and vector data access requests. In the case of a scalar data access request, the address sent from the CPU 1 is used as it is, the memory unit to be accessed is selected, and the request signal and address are sent to the corresponding memory unit.

On the other hand, in the case of a vector data access request, the memory access control unit 2 generates the address of each element forming the vector data based on the start address and the inter-element spacing supplied from the CPU 1. Then, the request signal and the address are sent to the memory unit corresponding to the generated address. However, regardless of whether it is scalar data or vector data, the write data is also sent when writing to the memory. The request signal is sent for each element, and up to four elements are sent at the same time depending on the inter-element spacing.

The memory units 3-0 to 3-3 are connected to the memory access control unit 2 by 102-0 to 102-3, respectively.
It operates based on the instructions sent via. CPU1
The addressing as seen is as shown in Fig. 3,
The memory access control device 2 determines the memory unit to be accessed on the premise of this addressing. Also,
As is clear from FIG. 3, when vector data arranged at consecutive addresses on the memory are accessed, four elements can be simultaneously accessed.

The request signal sent to the memory units 3-0 to 3-3 via the wirings 102-1 to 102-3 is also supplied to the OR circuit 4, and the OR circuit 4 connects to the wiring 103.
Is input to the counter 5 and the connection 103 becomes logic "1", the counter 5 is incremented. That is, the connection 102
Memory unit 3 via any one of −0 to 102-3
The counter 5 is incremented at the timing when the request signal is sent to -0 to 3-3. The value of the counter 5 is supplied to the CPU 1 via the connection 104, and the CPU 1 can refer to the value of the counter 5.

The connections 102-0 to 102-4 are also supplied to the counters 6-0 to 6-3, respectively.
-0 to 6-3 are stepped when the connections 102-0 to 102-3 become logic "1". Counter 6-0 to 6
-3 is C via connection 105-0 to 105-3, respectively
It is supplied to PU1, and CPU1 causes counters 6-0 to 6-3.
You can refer to the value of.

The CPU 1 has a timer (not shown) that is incremented in every clock cycle, and the counters 5 and 6-0 at fixed time intervals defined by this timer.
The memory load of the program can be calculated by referring to the value of 6-3. The program creator can consider the program so as to reduce the memory load based on the memory load thus obtained.

Next, FIG. 2 is a block diagram showing a second embodiment of the present invention. This embodiment has two CPUs 11-0.
And 11-1, a memory access control unit 12, four memory units 13-0, 13-1, 13-2 and 13-3, an OR circuit 14, and two AND circuits 15-.
0 and 15-1 and two counters 16-0 and 1
6-1 and 6-1.

The CPUs 11-0 and 11-1 are arithmetic processing units having the same functions as the CPU 1 in the first embodiment, and access the memory access controller 12 via the connections 201-0 and 201-1 respectively. Send the request.

The memory access control unit 2 includes a CPU 11-
0 and the memory access request sent from the CPU 11-1 are arbitrated and a request signal is sent to each of the memory units 13-0 to 13-3 via the connections 202-0 to 202-3. The memory units 13-0 to 13-3 are assigned addresses as shown in FIG. 3 similarly to the memory units 3-0 to 3-3 in the first embodiment. Address is CPU11
The memory unit to be accessed is determined on the assumption that the memory unit is common to 0 and 11-1.

The memory access control unit 12 has a CPU 11
Either one of the requests from 0 or 1 is processed, and no request signal is sent to the memory units 13-0 to 13-3 at the same time. The request signal transmission source CPU number is the connection 203-
It is output via 0 to 1 and supplied to AND circuits 15-0 and 15-1, respectively. When the request signal for the access request of the CPU 11-0 is sent, 203-0 becomes the logic "1", and when the request signal for the access request of the CPU 11-1 is sent, the logic 203-1 becomes the logic "1". , AND circuits 15-0 and 15-1 are activated, respectively.

The request signal supplied to the memory units 13-0 to 13-3 via the connections 202-0 to 202-3 is also supplied to the OR circuit 14 in the same manner as in the first embodiment, and four request signals are supplied. The signals are ORed and supplied to the AND circuits 15-0 and 15-1 via the connection 204. AND circuits 15-0 and 15-1 indicate the request source CPU numbers of the request signals to the memory units 203-0 and 20-3.
3-1 and the logical product of 204 indicating that there is an access request to any of the memory units 13-0 to 13-3 are taken and connected to the counters 16-0 and 16-1, respectively, by connecting wires 205-0 and 205. -1 is supplied. Counters 16-0 and 16-1 are each 205
-0 and 205-1 are counters that are incremented when they become logic "1".
-1 by the memory access request by the memory unit 1
It shows the number of times the request signal is sent to 3-0 to 13-3.

The counters 16-0 and 16-1 are connected to the CPU 11 via connections 206-0 and 206-1, respectively.
The values of the CPUs 11-0 and 11-1 to 16-0 and 16-1 can be referred to. The CPUs 11-0 and 11-1 have built-in timers (not shown) and counters 16-0 and 16-1.
It is possible to calculate the memory load of the programs executed by each.

Needless to say, the two embodiments described above are preferable examples of the present invention, and the present invention is not limited to these embodiments.

[0023]

As described above, according to the present invention, the memory load state of the program can be notified by having the counting means for counting each time an access request is sent to the memory, so that the program can be corrected. It is possible to obtain the performance of the vector computer as a result.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a diagram showing an example of addressing of a memory according to the present invention.

[Explanation of symbols]

1, 11-0, 11-1 CPU 2, 12 Memory access control unit 3-1 to 3-3, 13-0 to 13-3 Memory unit 4, 14 OR circuit 5, 6-0 to 6-3, 16 -0 to 16-1 Counter 15 AND circuit.

Claims (2)

[Claims] 1. A performance monitor for an information processing apparatus comprising a memory device comprising a plurality of memory units that can operate independently at the same time, and one or more arithmetic processing devices, wherein the memory from the arithmetic processing devices is a memory device. Memory access control means for controlling an access request to the device to be sent to the corresponding memory unit, and counting means corresponding to the arithmetic processing device, which advances when a request signal is sent to one of the memory units. A performance monitor of an information processing apparatus, comprising: 2. The performance monitor for an information processing apparatus according to claim 1, further comprising: counting means corresponding to the memory unit, which advances when a request signal is sent to the memory unit.