JPH0773342B2 - Video signal processing circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit suitable for use in a video camera which performs digital video signal processing.

[0002]

2. Description of the Related Art Conventionally, a video camera which digitally performs video signal processing is composed of a plurality of digital ICs, field memories, etc., as shown in P237-241 of Nikkei Electronics 1992.2.3 (NO.546). It has functions such as electronic zoom and image stabilization.

On the other hand, as a device for reducing noise contained in a video signal, there is a cyclic noise reducer as shown in FIG. This noise reducer removes noise that has no correlation in the time axis direction, and normally controls K in the range of 1>K> 0 according to the movement, and particularly in a still image, the coefficient K of the multiplier is set. By bringing the value closer to 0, a large noise reduction effect can be obtained.

Although it is desirable to provide the noise reducer as described above also in the video signal processing circuit of the video camera, an expensive frame memory or field memory is required, which causes a cost increase.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and in a video camera having a digital signal processing circuit, a cyclic noise reducer is configured without separately providing an expensive field memory. This provides a video signal signal processing circuit that can obtain high image quality at low cost.

[0006]

According to the present invention, a memory for storing at least one field of an output obtained by AD-converting a CCD output, and a memory control circuit for controlling a read position of the memory according to an instructed zoom magnification, In a video signal processing circuit including an interpolation circuit for interpolating the memory output with an interpolation coefficient according to the zoom magnification, the memory is also used as a memory forming a cyclic noise reducer. Is.

The present invention relates to a memory for storing at least one field of an output obtained by AD converting a CCD output,
A motion vector detection circuit for detecting a motion vector from the D conversion output, and a memory control circuit for controlling the read position of the memory according to the motion vector specified based on the output of the motion vector detection circuit and / or the instructed zoom magnification. And a video signal processing circuit including an interpolation circuit for interpolating the memory output with an interpolation coefficient according to the zoom magnification, wherein the memory is also used as a memory forming a cyclic noise reducer. It is a processing circuit.

[0008]

According to the present invention, the read position of the memory is controlled by the memory control circuit according to the instructed zoom magnification, and there is no correlation in the time axis direction of the video signal as a part of the cyclic noise reducer. It acts to remove noise.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of a video signal processing circuit of a video camera according to this embodiment. In the figure, 1 is C in which a predetermined mosaic color filter is arranged on the image pickup surface.
A CD (solid-state image sensor) 2 is an A / D converter that converts this CCD output into a 10-bit digital signal.

Reference numeral 3 denotes an image stabilization IC, which is roughly divided into a noise reduce circuit 31, a motion vector detection circuit 32, and a memory control circuit 33. The noise reduce circuit 31 removes noise having no correlation in the time axis direction from the output of the A / D converter 2, and constitutes a cyclic noise reducer as shown in FIG. 2 together with the field memory F outside the IC. The coefficient K of the multiplier of the noise reduce circuit 31 is controlled in the range of 0 <K <1 according to the amount of movement of the image detected by the first microcomputer described later.

Reference numeral 34 is a compression circuit for compressing the output of the 10-bit noise reduce circuit 31 into 8-bit data and supplying it to the 8-bit field memory F. Reference numeral 35 is 10-bit data of 8-bit data read from the field memory F. The decompression circuit decompresses the bit and supplies it to the noise reduce circuit 31. The field memory F is originally used for electronic zoom and camera shake correction as described later.

However, when the electronic zoom and camera shake correction functions are operating, the noise reduce circuit 3
Since the data correlation between the input of 1 and the output of the field memory F is lost, it is necessary to stop the operation of the noise reducer. Therefore, in this embodiment, the noise reduce circuit 3
A selector 37 for selecting and outputting one output and the output of the expansion circuit 35 is provided, and the expansion circuit output is selected and the coefficient K of the noise reduce circuit is set to 1 during the electronic zoom or camera shake correction operation. Control to stop the operation of the circuit.

On the other hand, a part of the output of the A / D converter 2 is input to the motion vector detection circuit 32. The motion vector detection circuit 32 detects a motion vector for every four detection blocks by the well-known representative point matching method, and supplies it to the first microcomputer 4. The first microcomputer 4 specifies one motion vector from the motion vectors for each detection block.

At the time of camera shake correction, electronic zoom is performed at a predetermined zoom magnification (1.2 times), and the read start position from the field memory F is controlled according to this motion vector to cut out the image. To control camera shake.

Next, the memory control circuit 33 will be described.

The memory control circuit 33 controls writing in the field memory F according to the write start address from the first microcomputer 4. Further, the read start address is controlled according to the motion vector and / or the instructed zoom magnification (1 to 4 times), and the read pulse corresponding to the zoom magnification is generated to control the duplicated reading of the same data.

The memory control circuit 33 also calculates an interpolation coefficient to be supplied to an interpolation circuit, which will be described later, according to the zoom magnification. That is, the memory control circuit 33 controls the writing and reading of the field memory F and controls the interpolation circuit to perform zoom control.

Further, during zooming, the color order of the signals from the field memory F differs from the CCD output. Since the YC separation circuit described later does not operate in this state, the memory control circuit 33 creates a color order identification signal indicating the color order based on the read pulse and supplies it to the YC separation circuit.

Next, reference numeral 36 is a synchronizing signal generating circuit which generates horizontal and vertical synchronizing signals based on a clock and a start pulse and supplies them to the motion vector detecting circuit 32 and the memory control circuit 33.

Reference numeral 5 is a digital signal processing IC for digitally processing the output of the image stabilization IC 3.

Reference numeral 501 denotes an interpolation circuit to which the output of the noise reduce circuit 31 is supplied, which performs data interpolation in the horizontal and vertical directions according to the interpolation coefficient corresponding to the zoom magnification and two color signals and a luminance signal Y. Further, horizontal and vertical aperture signals AP which are contour correction signals are generated.

The two color signals are Y / C separation circuit 502.
Is supplied to the RGB matrix circuit 503 and is separated into the color signals Cr and Cb and the low-frequency luminance signal YL.
It is a B color signal. This RGB color signal is sent to the γ correction circuit 50.
.Gamma.-correction is performed in step 4, and then the color difference matrix circuit 505 performs R-
It is converted into Y and BY color difference signals. Further, this color difference signal is processed by the color signal processing circuit 506, modulated into an NTSC color signal, and output.

On the other hand, the luminance signal Y of the output of the interpolation circuit
Is added with the aperture signal AP by the aperture adding circuit 507 and is then γ corrected by the γ correction circuit 508. Further, this luminance signal is processed by the luminance signal processing circuit 509,
The sync addition circuit 510 adds a sync signal based on the output of the sync signal generation circuit 36 and outputs the sync signal.

The output of the color signal processing circuit 506 and the output of the synchronization adding circuit 510 are the D / A converter 7 and the output, respectively.
At 8, it is converted into an analog color signal and a luminance signal.

Regarding each block of the signal processing circuit described above, Japanese Patent Application No. 3-150 previously filed by the applicant of the present application.
Since it is described in detail in No. 365, detailed description is omitted.

Next, AF (autofocus) and AE
(Auto iris) and AWB (auto white balance) will be described.

One of the brightness outputs from the interpolation circuit 501 before the addition of the aperture signal is supplied to the AF integration circuit 512 after the high frequency component of the brightness signal is extracted by the HPF 511. The AF integration circuit 512 digitally integrates in a field cycle for each integration area obtained by dividing the imaging area into a plurality of areas. Then, the integrated value is subjected to predetermined arithmetic processing by the second microcomputer 6 which can communicate with the first microcomputer 4, and is supplied to a focus motor (not shown) as an AF control output.

The luminance output from the interpolation circuit 501 is further extracted by the LPF 513 in the low-frequency component of the luminance signal, and thereafter, is similarly integrated by the AE integration circuit 514. And
This integrated value is subjected to predetermined arithmetic processing by the second microcomputer 6 and supplied as an AE control output to an iris motor (not shown).

Further, either the RGB signal from the RGB matrix circuit 503 or the color difference signal (RG, BG) from the color difference matrix circuit 505 is selected by the selector 515, and the HPF 516 selects the high frequency range of the color signal. After the components are extracted, they are similarly digitally integrated by the AWB integrating circuit 517. Then, the integrated value is subjected to predetermined arithmetic processing by the second microcomputer 6 and supplied to the RGB matrix circuit 503 as an AWB control output.
Controls the coefficients of this circuit.

As described above, since AF, AE, and AWB are detected using the output after camera shake correction, the integrated result does not fluctuate due to camera shake and can be accurately controlled.

Further, since AF and AE are detected using the luminance signal before γ correction and before the addition of the aperture, that is, before the non-linear processing, accurate detection can be performed.

It should be noted that the selector 515 can select either one by setting the second microcomputer 6.

The RGB signals are selected so that the same color signal is obtained for each field before being selected by the selector 515, and the same color signal is integrated for one field period by the integrating circuit in the subsequent stage. It is made possible.
Similarly, the color difference signals are selected so that the same signal can be obtained for each field.

[0035]

As described above, according to the present invention, in a video camera having an electronic zoom function and a camera shake correction function, a recursive noise reducer can be configured without separately providing an expensive field memory. A video camera with high image quality can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal processing circuit of a video camera according to an embodiment of the present invention.

FIG. 2 is a block diagram of a general cyclic noise reducer.

[Explanation of symbols]

 3 IC for image stabilization 31 Noise reduce circuit 32 Motion vector detection circuit 33 Memory control circuit F field memory 5 Digital signal processing IC 501 Interpolation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Okino 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (72) Inventor Toshiya Iinuma 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Incorporated (72) Inventor Masao Takuma 2-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Akio Kobayashi 2-18-2 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. ( 72) Inventor Seiji Kawakami 2-18, Keihan Hondori, Moriguchi-shi, Osaka, Sanyo Electric Co., Ltd. (72) Inventor Toru Asaed 2--18, Keihan Hondori, Moriguchi, Osaka (56) Reference Document JP-A-2-25175 (JP, A)

Claims (3)

[Claims] 1. A memory for storing at least one field of an output obtained by AD-converting a CCD output, a memory control circuit for controlling a read position of the memory according to an instructed zoom magnification, and an interpolation coefficient according to the zoom magnification. According to the video signal processing circuit including the interpolation circuit for interpolating the memory output, the video signal processing circuit is characterized in that the memory is also used as a memory forming a cyclic noise reducer. 2. A memory for storing at least one field of an output obtained by AD-converting a CCD output, and a motion vector detection circuit for detecting a motion vector from the AD-converted output,
A memory control circuit for controlling the read position of the memory according to a motion vector specified based on the output of the motion vector detection circuit and / or a zoom magnification designated, and the memory output by an interpolation coefficient according to the zoom magnification. A video signal processing circuit provided with an interpolation circuit for interpolating, wherein the memory is also used as a memory forming a cyclic noise reducer. 3. A selection circuit for selecting and outputting the noise reducer output and the memory output, and selecting the memory output during an electronic zoom or camera shake correction operation. 2. The video signal processing circuit according to 2.