JPH077383B2 - Waiting circuit - Google Patents

Description

The present invention relates to a queuing circuit for controlling the start of binary operation and processing such as addition and subtraction in a data flow type computer.

[Conventional technology]

The data flow type computer has an architecture in which a destination calculation (processing) module and a tag indicating the processing content are added to the data, and the data is taken into the calculation (processing) module according to the tag and the calculation (processing) is performed. Has become. Therefore, the binomial operation module is composed of a waiting circuit 20 and a binomial operation circuit 30, as shown in FIG.

In this binomial calculation module 30, FIG. 4 (a), (b)
As shown in, processing is performed according to two normal operation methods, that is, a binary operation and a constant operation. In a normal binomial operation, as shown in FIG. 4 (a), when two pieces of pair data Ai and Bi are input, an operation is performed every time pair data is prepared, and the result Ci is output. , The previously entered data Ai (or
Bi) is kept waiting in the waiting circuit 20 until the other data Bi (or Ai) is input.

On the other hand, in the constant operation, every time Ai is input, the operation with the constants B1 to Bn stored in advance in the waiting circuit 20 is performed, and as a result, Ci is output. In this case, the constant is stored once. For example, it can be used repeatedly.

A general block diagram of the waiting circuit 20 is shown in FIG. Tag 101 is a waiting circuit together with data 100
Entered in 20. This tab 101 is converted by the tag conversion unit 1 into a pair data name 103 and a pair flag 102 indicating which data name of the pair data (when Ai and Bi are pair data, a flag indicating whether it is Ai or Bi). To be done. Based on the pair data name 103 and the pair flag 102, the read / write control unit 2 determines whether or not the data to be paired with the input data 100 has already been input and stored in the waiting memory 10.
That is, when the data to be paired is not yet input, the read / write control unit 2 outputs the write request signal 104. The write request signal 104 causes the multiplexer 7 to output the write counter value 107 which is the output of the write counter 5. The adder 8 adds the base address 105 and the write counter value 107, outputs the write address 110 of the waiting memory 10, and stores the data 100 in the waiting memory.

Conversely, when the data to be paired is already input, the read / write control unit 2 outputs the read request signal 104.
The read request signal 104 causes the read count value 106 output from the read counter 4 from the multiplexer 7.
Is output. The adder 8 adds the base address 105 from the base address unit 3 and the read count value 106 from the read pointer 4 and outputs the read address 110 of the queuing memory 10 to obtain a pair data of the data 100.
Outputs 113. In the read / write operation of this waiting memory, the read counter or the write counter is incremented by +1.

The read count value 106, the write count value 107, and the maximum number of words (the number of words in the waiting memory assigned to the pair data name) output from the maximum word number section 6 are compared by the comparator 9.
The write counter and the read counter cycle from 0 to the maximum number of words. If the write count value catches up with the read count value, an error occurs due to memory overflow.

In the circuit of this configuration, since the allocation of the waiting memory 10 is fixed for each pair data name, the waiting memory 10
Is not used efficiently, and if a program is set up so that only one of the paired data is continuously input, overflow of the waiting memory 10 is likely to occur.

In order to improve this point, the circuit shown in the block diagram of FIG. 5 has been conventionally considered. The basic operation of this circuit is the second
Since it is the same as the general circuit in the figure, only the differences will be described here. Comparing the circuit of FIG. 5 with the circuit of FIG.
Instead of the base address unit 3, the maximum word number unit 6 and the comparator 9, an address conversion unit 11 and an address control unit 12 are used.

The address conversion unit 11 sets an address in which the upper bit 114 of the read count value 106 or the write count value 107 output from the multiplexer 7 is the lower bit and the pair data name 103 is the upper bit, and the queuing memory 10 is used for each appropriate number of words. It has an address translation table that translates to block address 117 when blocking to. The queuing memory 10 is accessed by an address having the block address 117 as the upper bit and the lower bit 116 of the read cant value or the write count value output from the multiplexer 7 as the lower bit. This allows the queuing memory to be managed block by block. The address control unit 12 is the waiting memory 10
In order to grasp the block usage status of the block, a block management table having a block address and a usage status flag of the block is provided.

With such a configuration, the pair data can be efficiently acquired in the queuing memory 10 as much as necessary. That is, each time the upper bit of the write count value input to the address controller 12 is incremented, the address controller 12 address converter 11
Writes the block address of an empty block to the address conversion table of, and acquires the queuing memory by changing the flag of the usage status of the block to unused, and conversely, it is used every time the upper bit of the read count value is incremented. Change the status flag from used to unused,
release.

[Problems to be solved by the invention]

The queuing circuit configured so that the conventional queuing memory described above can be used efficiently has the following problems. First of all, since a block of the waiting memory is allocated for each pair of data, it is not possible to perform a constant operation with the data of the same block as a constant of a different pair of data names. Then, in the block management table in the address control unit. Since the queuing memory is managed in block units, it takes time to search the table when acquiring and releasing the queuing memory, and the processing speed decreases. Furthermore, when the upper bit of the write count value is counted up, a block is allocated to the pair data, so it is necessary to allocate one block to all the pair data names as an initial process. Also, the queuing memory is allocated and waste occurs.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems, to provide a queuing circuit in which constants to be used can be freely specified, processing speed is improved, and efficient use is possible.

[Means for solving problems]

The queuing circuit of the present invention generates a queuing memory for temporarily storing previously arrived data for adjusting the timing of paired data to be processed, and a high-order bit and a low-order bit of a read address and a write address of the queuing memory, respectively. A read counter and a write counter, a tag conversion unit that converts a tag attached to the pair data into a pair data name and its flag, the pair data name or constant name, and the upper bits of the read counter or write counter. An address translation unit that translates into a block address of the queuing memory, a block address first-in first-out unit that supplies the block address to the address translation unit and stores the block address released by this address translation unit, and each pair data name Constant name during constant calculation as address Table to output the constant name to the address conversion unit, a constant bias unit that specifies a constant bias value that defines the start point of the address range corresponding to the constant name, and an address range corresponding to the constant name A cyclic address part for designating a cyclic address for defining the end point of the block, and a comparing means for controlling the read counter by instructing a storage range of a constant in the waiting memory from the cyclic address and a constant bias value. Read / write of the waiting memory is performed by an address and the lower bit of the read counter or the write counter, and an address from the address corresponding to the bias value of the waiting memory to the address corresponding to the cyclic address can be used as a constant. Is characterized by.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In this embodiment, the tag conversion unit 1, the read / write control unit 2, the constant control unit
13, cyclic address unit 14, constant bias unit 15, read counter 4, write counter 5, adder 16, comparator 17, multiplexer 7, waiting memory 10, address conversion unit 11, block address first-in first-out circuit (FIFO) 19, FIFO It is composed of the control unit 18.

The tag conversion unit 1 converts the tag 101 into a pair data name 103 and a pair flag 102, and the read / write control unit 2 has already stored one of the pair data from the input pair data name 103 and pair flag 102 in the waiting memory. Determine if there is
If it is stored, a read request to the waiting memory 10 is output, and if not, a write request to the waiting memory 10 is output as a read / write control signal 104. The constant control unit 13 prepares a constant name table in which an 8-bit constant name is written with each pair data name 103 as an address, thereby converting into a pair data name 118 of constant data. In this case, when it is not a constant operation or when a constant is stored in the pair data name 103, the pair data name 103 is output as it is as the pair data name 118.

In the case of a normal binary operation that is not a constant operation, when the read / write control signal 104 is a write request, the block address 110 converted by the address conversion unit 11 is the upper bit and the lower bit of the write count value 107 is the lower bit. Write the data 100 in the waiting memory 10 at the address to be set. At this time, when all the lower bits of the write count value 107 are “0”, the block address is written from the block address FIFO 19 into the address conversion table of the address conversion unit 11.

With the same normal binary operation, when the read / write control signal 104 is a read request, the address conversion unit is the same as the write request.
The queuing memory 10 is read at an address in which the block address 110 converted in 11 is the upper bit and the lower bit 116 of the read counter value 121 is the lower bit, and the pair data 113 of the data 100 is output. At this time, when all the lower bits of the read count value 106 are "1", the block address which is no longer needed by the address conversion unit 11 is returned to the block address FIFO 19. The control of the block address FIFO 19 and the address conversion unit 11 is performed by the FIFO control unit 18.

The cyclic address unit 4 outputs a cyclic address that is freely set from a cyclic address table that stores cyclic addresses with each pair data name as an address. Further, the constant bias unit 15 outputs a constant bias value freely set for each pair data name from a constant bias table storing constant bias values with each pair beta name as an address.

In constant calculation, the read count value of the read counter 4 is 10
Add the constant bias value 120 of the constant bias unit 15 to the value of 6
Add by 16 to generate element 121 of the read address,
This value is compared by the comparator 17 and incremented until the cyclic address value 119 of the cyclic address unit 14 is reached. When it becomes equal to the cyclic address value 119, the read count value is reset to "0", and the increment is repeated up to the cyclic address value 119. That is, element 121 of the read address
Circulates between the constant bias value 120 and the cyclic address value 119. Further, by converting the pair data name in the constant control unit 13, the constant stored in the waiting memory 10 can be used as other pair data.

The relationship among these constants, cyclic address, and constant bias is as shown in FIG. 6 as an example. Waiting memory
This waiting memory 10 shows the part where 10 constants (... 0000 to 0011 ...) are stored and its address (... 10 to 21 ...).
The upper bit of the address of is the range * 1 determined by the constant name 118, and the constant of addresses _{10 to} n is 0000 to 000m (B10 to
Equivalent to m).

When a part of the constants in this range * 1 is cyclically used, the constant bias specifies the address (12) storing the constant B ₁₂ and the cyclic address specifies the address (18) storing the constant B _18. Therefore, the constants B _{12 to} B ₁₈ (0002 to 00
08) is used cyclically every time the pair data Ai is input.

With this configuration, the specific range * 1 of the waiting memory 10 can be arbitrarily decomposed and used for various constant operations.

〔The invention's effect〕

As described above, according to the present invention, the pair data name converted by the constant control unit, the constant to be used in the cyclic address unit and the constant bias unit can be freely specified, and further, the lower bit of the write counter or the read counter can be specified. Depending on the value of, a new block is supplied from the block address FIFO to the address translation unit, or the block address FIFO is sent from the address translation unit.
Since the blocks are returned unnecessarily, it is possible to supply and release the blocks within one clock, and it is not necessary to allocate one block to each pair data name as initial processing. There is an effect that it can be used efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of a conventional waiting circuit, and FIG. 3 is a block diagram of a general binary operation module, FIG. 4 (a), (B) is a data flow diagram for explaining ordinary binary operation and constant operation in the binary operation processing method, FIG. 5 is a block diagram in which the conventional waiting circuit is improved, and FIG. 6 is the embodiment of FIG. FIG. 3 is a configuration diagram of a queuing memory showing a relationship among a constant, a cyclic address and a constant bias. 1 ... Tag conversion unit, 2 ... Read / write control unit, 3 ...
Base address part, 4 ... Read counter, 5 ... Write counter, 6 ... Maximum word count part, 7 ... Multiplexer, 8,16 ... Adder, 9,17 ... Comparator, 10 ... Waiting memory, 11 …… Address converter, 12 …… Address controller,
13 ... Constant control unit, 14 ... Circular address unit, 15 ... Constant bias unit, 18 ... FIFO control unit, 19 ... Block address FIFO, 20 ... Waiting circuit, 30 ... Binary operation circuit, 40 …
… Binary operation module, 100 …… data, 101 …… tag,
102 …… Pair flag, 103 …… Pair data name, 110 …… Block address.

Claims (1)

[Claims] 1. A queuing memory for temporarily storing previously arrived data for synchronizing the timing of paired data to be processed, and a read counter for generating upper and lower bits of a read address and a write address of the queuing memory, respectively. Obi write counter, a tag conversion unit for converting a tag attached to the pair data to a pair data name and its flag, the pair data name or constant name and the upper bit of the read counter or write counter, the waiting memory Address conversion unit for converting to the block address, a block address first-in first-out unit that supplies the block address to the address conversion unit and stores the block address released by this address conversion unit, and each pair data name as an address Is it a constant name table during constant calculation? A constant control unit that outputs the constant name to the address conversion unit, a constant bias unit that specifies a constant bias value that defines the starting point of the address range that corresponds to the constant name, and an end point of the address range that corresponds to the constant name. A cyclic address part for designating a cyclic address for determining a constant address, and a comparing means for instructing a storage range of a constant in the waiting memory from the cyclic address and a constant bias value to control the read counter. The read / write of the waiting memory is performed by the lower bit of the read counter or the write counter, and the address from the address corresponding to the bias value of the waiting memory to the address corresponding to the cyclic address can be used as a constant. Waiting circuit to be.