JPH077384B2 - Parallel cross-correlator - Google Patents
Parallel cross-correlatorInfo
- Publication number
- JPH077384B2 JPH077384B2 JP62236194A JP23619487A JPH077384B2 JP H077384 B2 JPH077384 B2 JP H077384B2 JP 62236194 A JP62236194 A JP 62236194A JP 23619487 A JP23619487 A JP 23619487A JP H077384 B2 JPH077384 B2 JP H077384B2
- Authority
- JP
- Japan
- Prior art keywords
- multiplexer
- input
- output
- correlator
- reference signal
- Prior art date
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- Expired - Lifetime
Links
- 230000002596 correlated effect Effects 0.000 claims description 2
- 238000004364 calculation method Methods 0.000 description 13
- 230000010354 integration Effects 0.000 description 5
- 230000000875 corresponding effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000013139 quantization Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Description
【発明の詳細な説明】 （１）発明の属する技術分野 本発明は、計算時間の短い相互相関器に関するものであ
る。Description: TECHNICAL FIELD The present invention relates to a cross-correlator having a short calculation time.
（２）従来の技術 通常、相互相関を計算する場合は信号をディジタル化し
た後、ディジタル信号処理技術を用いて計算する場合が
多い。相関を計算する信号が既知の場合、ディジタル信
号処理技術を用いた相互相関器は計算時間を理論的には
０にすることが可能であるが、実際の装置では、ディジ
タル信号処理素子の処理遅延のためアナログ方式のスラ
イディング相関器に比較して計算時間が長い。このた
め、高速の信号処理を必要とする用途には、適用できな
い。また高い信号対雑音比（以下「S/N」と略記す
る。）を必要とする場合には量子化ビット数は量子化雑
音を低減するため多くする必要がある。これが計算速度
の低下とハードウェアコストの上昇をもたらす。(2) Conventional Technique In general, when calculating the cross-correlation, it is often the case that the signal is digitized and then calculated using a digital signal processing technique. When the signal for which the correlation is calculated is known, the cross-correlator using the digital signal processing technique can theoretically reduce the calculation time to 0. However, in an actual device, the processing delay of the digital signal processing element is used. Therefore, the calculation time is longer than that of the analog sliding correlator. Therefore, it cannot be applied to applications requiring high-speed signal processing. When a high signal-to-noise ratio (hereinafter abbreviated as “S / N”) is required, the number of quantization bits needs to be increased to reduce quantization noise. This causes a decrease in calculation speed and an increase in hardware cost.
一方、スライディング相関方式の相互相関器はその構成
要素の中に積分器があるため、そと積分時間よりも計算
時間を短くすることは理論的にできない。しかし相関器
を並列に複数用いることより計算時間を短縮することが
可能である。この場合具体的にどのように相関器を配置
し、どの信号をどの相関器に入出力するかが装置実現の
鍵となる。On the other hand, since the sliding correlation type cross-correlator has an integrator among its constituent elements, it is theoretically impossible to make the calculation time shorter than the integration time. However, it is possible to reduce the calculation time by using multiple correlators in parallel. In this case, how the correlators are specifically arranged and which signal is input to and output from which correlator are the key to device realization.
第１図は通常のスライディング相関器のブロック図であ
って、１は相関器入力信号、２はスライディングする参
照信号を発生する参照信号発生器、３は乗算器、４は積
分器である。この相関器では参照信号のスライディング
に伴い参照信号の１周期にわたる相互相関値が積分器４
から出力される。参照信号と相関のある成分を雑音とと
もに含む入力信号と、参照信号との間の相互相関をとる
場合などは、参照信号のスライディング速度を低下させ
るとともに、積分器４の積分時間を長くすることにより
相関器出力の雑音を低減できる。しかしこの場合、積分
時間を長くしたため計算時間は長くなる。また入力信号
の状態変化が激しいとき、スライディング１周期ごとの
標本化では相互相関値の変化が激しいため正確の相互相
関値を得られない場合がある。FIG. 1 is a block diagram of a conventional sliding correlator, in which 1 is a correlator input signal, 2 is a reference signal generator for generating a sliding reference signal, 3 is a multiplier, and 4 is an integrator. In this correlator, the cross-correlation value over one period of the reference signal is changed by the integrator 4 as the reference signal is sliding.
Is output from. When cross-correlating an input signal including a component having a correlation with the reference signal together with noise and the reference signal, the sliding speed of the reference signal is decreased and the integration time of the integrator 4 is increased. The noise of the correlator output can be reduced. However, in this case, the calculation time becomes longer because the integration time is made longer. Further, when the state of the input signal changes drastically, the sampling of each sliding cycle may cause a drastic change in the cross-correlation value, so that an accurate cross-correlation value may not be obtained.
（３）発明の目的 本発明ではこれらの欠点を除去し、計算時間が短く、従
来のスライディング相関器の出力信号と同一形式の出力
を有する相関器を提供することにある。(3) Object of the invention It is an object of the present invention to eliminate these drawbacks, provide a correlator having a short calculation time and an output of the same type as the output signal of a conventional sliding correlator.
上記目的を達成するために、本発明に係る並列相互相関
器は、参照信号を発生する参照信号発生手段（例えば参
照信号発生器11）と、前記参照信号発生手段からの参照
信号を夫々異なる遅延時間だけ遅延させる複数の遅延手
段（例えば４段の遅延素子500）と、各遅延手段から各
々出力されるＮ個の参照信号の出力先を、参照信号発生
手段からの信号がＮ回スライディングする間に「Ｎ−
１」回だけ切替えるＮ個の切替手段（例えば２進アップ
カウンタ1000、第１マルチプレクサ100、第２マルチプ
レクサ200、第３マルチプレクサ300、第４マルチプレク
サ400）と、各切替手段によって切替えられたＮ個の参
照信号夫々に対応して設けられた、一方の入力端子に参
照信号を、他方の入力端子に被相関信号たる相関器入力
信号を受けるＮ個の相関手段（例えば第１相関器600、
第２相関器700、第３相関器800、第４相関器900）と、
各相関手段からの信号を前記参照信号発生手段からの信
号がＮ回スライディングする間にＮ回の切替を行う相関
出力切替手段（例えば第11マルチプレクサ1100、２進ア
ップカウンタ1120）と、を備え、前記相関出力切替手段
からの信号を相関器出力として得るものとした。In order to achieve the above object, a parallel cross-correlator according to the present invention includes a reference signal generating means for generating a reference signal (for example, a reference signal generator 11) and a reference signal from the reference signal generating means with different delays. While the signal from the reference signal generating means is sliding N times, a plurality of delaying means (for example, four stages of delay elements 500) for delaying by time and output destinations of N reference signals respectively output from each delaying means. "N-
N switching means (for example, binary up-counter 1000, first multiplexer 100, second multiplexer 200, third multiplexer 300, fourth multiplexer 400) that switch only 1 "times, and N switching means that are switched by each switching means. N correlating means (for example, a first correlator 600, which is provided corresponding to each reference signal) receives a reference signal at one input terminal and a correlator input signal that is a correlated signal at the other input terminal.
A second correlator 700, a third correlator 800, a fourth correlator 900),
Correlation output switching means (for example, eleventh multiplexer 1100, binary up counter 1120) that switches the signal from each correlation means N times while the signal from the reference signal generation means slides N times, The signal from the correlation output switching means is obtained as a correlator output.
（４）発明の構成及び作用 以下、第２図によって本発明を詳細に説明する。説明の
都合上、相関器数ＮをＮ＝４としているが本発明ではＮ
の値を任意に大きくすることが可能である。第２図は本
発明の一実施例を示す概念構成図であって、10は相関器
入力信号、11はスライディングする参照信号を発生する
参照信号発生器、100はマルチプレクサ１、101はマルチ
プレクサ１の第１入力、102はマルチプレクサ１の第２
入力、103はマルチプレクサ１の第３入力、104はマルチ
プレクサ１の第４入力、105はマルチプレクサ１の出
力、106はマルチプレクサ１の切替え制御信号入力、200
はマルチプレクサ２、201はマルチプレクサ２の第１入
力、202はマルチプレクサ２の第２入力、203はマルチプ
レクサ２の第３入力、204はマルチプレクサ２の第４入
力、205はマルチプレクサ２の出力、206はマルチプレク
サ２の切り替え制御信号入力、300はマルチプレクサ
３、301はマルチプレクサ３の第１入力、302はマルチプ
レクサ３の第２入力、303はマルチプレクサ３の第３入
力、304はマルチプレクサ３の第４入力、305はマルチプ
レクサ３の出力、306はマルチプレクサ３の切替え制御
信号入力、400はマルチプレクサ４、401はマルチプレク
サ４の第１入力、402はマルチプレクサ４の第２入力、4
03はマルチプレクサ４の第３入力、404はマルチプレク
サ４の第４入力、405はマルチプレクサ４の出力、406は
マルチプレクサ４の切替え制御信号入力、500は４段の
遅延素子、501は遅延素子の１段目出力、502は遅延素子
の２段目出力、503は遅延素子の３段目出力、504は遅延
素子の４段目出力、600は相関器１、601は乗算器、602
は積分器、700は相関器２、701は乗算器、702は積分
器、800は相関器３、801は乗算器、802は積分器、900は
相関器４、901は乗算器、902は積分器、1000は相関器入
力切替えマルチプレクサ制御信号発生用２ビット２進ア
ップカウンタ１、1010は２進アップカウンタ１クロック
入力、1020は２進アップカウンタ１出力、1100は積分器
出力切替えマルチプレクサ11、1110は２進アップカウン
タ２出力、1120は積分器出力切り替えマルチプレクサ制
御信号発生用２ビット２進アップカウンタ２、1130は２
進アップカウンタ２クロック入力、1200は並列相互相関
器出力である。(4) Structure and Action of the Invention The present invention will be described in detail below with reference to FIG. For convenience of explanation, the number of correlators N is N = 4, but in the present invention N
The value of can be arbitrarily increased. FIG. 2 is a conceptual block diagram showing an embodiment of the present invention, in which 10 is a correlator input signal, 11 is a reference signal generator for generating a sliding reference signal, 100 is a multiplexer 1 and 101 is a multiplexer 1. The first input, 102 is the second of the multiplexer 1
Input 103 is the third input of the multiplexer 1, 104 is the fourth input of the multiplexer 1, 105 is the output of the multiplexer 1, 106 is the switching control signal input of the multiplexer 1, 200
Is a multiplexer 2, 201 is a first input of the multiplexer 2, 202 is a second input of the multiplexer 2, 203 is a third input of the multiplexer 2, 204 is a fourth input of the multiplexer 2, 205 is an output of the multiplexer 2, 206 is a multiplexer 2 is a switching control signal input, 300 is a multiplexer 3, 301 is a first input of the multiplexer 3, 302 is a second input of the multiplexer 3, 303 is a third input of the multiplexer 3, 304 is a fourth input of the multiplexer 3, and 305 is Output of multiplexer 3, 306 is input of switching control signal of multiplexer 3, 400 is multiplexer 4, 401 is first input of multiplexer 4, 402 is second input of multiplexer 4, 4
03 is the third input of the multiplexer 4, 404 is the fourth input of the multiplexer 4, 405 is the output of the multiplexer 4, 406 is the switching control signal input of the multiplexer 4, 500 is a delay element of four stages, 501 is one stage of the delay element The second output of the delay element, 502 the second output of the delay element, 503 the third output of the delay element, 504 the fourth output of the delay element, 600 the correlator 1, 601 the multiplier, 602
Is an integrator, 700 is a correlator 2, 701 is a multiplier, 702 is an integrator, 800 is a correlator 3, 801 is a multiplier, 802 is an integrator, 900 is a correlator 4, 901 is a multiplier, and 902 is an integrator. , 1000 is a 2-bit binary up counter 1 for generating a correlator input switching multiplexer control signal, 1010 is a binary up counter 1 clock input, 1020 is a binary up counter 1 output, and 1100 is an integrator output switching multiplexer 11, 1110. Is a binary up counter 2 output, 1120 is a 2-bit binary up counter 2 for generating an integrator output switching multiplexer control signal, and 1130 is 2
Advance up counter 2 clock input, 1200 is parallel cross-correlator output.
マルチプレクサ１、マルチプレクサ２、マルチプレクサ
３、マルチプレクサ４及び、マルチプレクサ10はそれぞ
れ４入力１出力で、マルチプレクサ切替え制御信号が２
進で「00」のときマルチプレクサの第１入力がマルチプ
レクサから出力され、「01」のとき第２入力が、「10」
のとき第３入力が、「11」のとき第４入力がそれぞれ出
力される。The multiplexer 1, the multiplexer 2, the multiplexer 3, the multiplexer 4, and the multiplexer 10 each have 4 inputs and 1 output, and the multiplexer switching control signal is 2
When the number is "00", the first input of the multiplexer is output from the multiplexer, and when the number is "01", the second input is "10".
, The third input is output, and when “11”, the fourth input is output.
４段の遅延素子500と、マルチプレクサ100、200、300、
400間は、遅延素子の１段目出力501とマルチプレクサ入
力101、204、303、402を、遅延素子の２段目出力502と
マルチプレクサ入力102、201、304、403を、遅延素子の
３段目出力503とマルチプレクサ入力103、202、301、40
4を、遅延素子の４段目出力504とマルチプレクサ入力10
4、203、302、401を、接続する。ここで、参照信号発生
器11では参照信号のスライディングを参照信号に参照信
号の一部を周期的に割り込ませることにより実現するも
のとする。4 stages of delay elements 500 and multiplexers 100, 200, 300,
Between 400, the first stage output 501 of the delay element and the multiplexer inputs 101, 204, 303, 402, the second stage output 502 of the delay element and the multiplexer inputs 102, 201, 304, 403, the third stage of the delay element Output 503 and multiplexer inputs 103, 202, 301, 40
4 is the fourth stage output 504 of the delay element and the multiplexer input 10
Connect 4, 203, 302 and 401. Here, it is assumed that the reference signal generator 11 realizes sliding of the reference signal by periodically interrupting a part of the reference signal into the reference signal.
４回の参照信号の割り込みに対し、２進アップカウンタ
１クロック入力1010の３回のパルス入力と、２進アップ
カウンタ２クロック入力1130の４回のパルス入力によ
り、並列相互相関器出力1200から信号を得る場合、参照
信号発生器11の４回の参照信号の割り込みに対しマルチ
プレクサ出力105、205、305、405には参照信号が１回割
り込まれた信号と等価な信号が出力される。このため、
この１回の割り込み周期に同期して積分器602、702、80
2、902の積分とリセットを位相をずらして繰り返すこと
により各相関器600、700、800、900は１回の参照信号の
割り込みによる相関と等価な動作を並列に行う。さら
に、参照信号の４回の割り込みに対応し、各相関器の積
分器のリセット直前の値を積分器出力切替えマルチプレ
クサ1100により出力できるよう、２進アップカウンタ２
出力1110の切替え速度と位相を２進アップカウンタ２ク
ロック入力1130により調整することにより、参照信号の
４回の割り込みに対応した速度で参照信号の１回の割り
込みに対応した相互相関の計算値が並列相互相関器出力
1200より得られる。In response to four reference signal interrupts, a signal is output from the parallel cross-correlator output 1200 by three pulse inputs of the binary up counter 1 clock input 1010 and four pulse inputs of the binary up counter 2 clock input 1130. In order to obtain the above, the multiplexer output 105, 205, 305, 405 outputs a signal equivalent to the signal interrupted once when the reference signal generator 11 interrupts the reference signal four times. For this reason,
The integrators 602, 702, 80 are synchronized with this one interrupt cycle.
Each of the correlators 600, 700, 800, 900 performs the operation equivalent to the correlation by the interruption of the reference signal once in parallel by repeating the integration and reset of 2, 902 while shifting the phase. Furthermore, the binary up counter 2 is provided so that the value immediately before the resetting of the integrator of each correlator can be output by the integrator output switching multiplexer 1100 in response to the four interruptions of the reference signal.
By adjusting the switching speed and phase of the output 1110 by the binary up counter 2 clock input 1130, the calculated value of the cross-correlation corresponding to one interrupt of the reference signal can be obtained at the speed corresponding to four interrupts of the reference signal. Parallel cross-correlator output
Obtained from 1200.
本発明による並列相互相関器では、相関器の段数ＮをＫ
倍にすると計算時間を同一に保ったまま参照信号の割り
込み回数を1/K、すなわち相互相関の計算長をＫ倍にす
ることができる。また逆に相互相関の計算長を同一に保
てば等価的に計算時間を1/K倍にすることができる。In the parallel cross-correlator according to the present invention, the number N of correlators is K
If it is doubled, the number of reference signal interrupts can be 1 / K, that is, the cross-correlation calculation length can be increased K times while maintaining the same calculation time. On the contrary, if the calculation length of the cross-correlation is kept the same, the calculation time can be equivalently increased by 1 / K.
なお、相関器の段数がＮのときはＮ回の参照信号の割り
込みに対し、２進アップカウンタ１クロック入力1010の
クロックパルスをＮ−１回、２進アップカウンタ２クロ
ック入力1030のクロックパルスをＮ回、各相関器の積分
器の積分とリセットを１回とすることにより、Ｎ回の割
り込みに対応した速度で並列相互相関器出力1200が得ら
れる。また、マルチプレクサと相関器間の結線の変更に
より２進アップカウンタ１と２進アップカウンタ２をダ
ウンカウンタに置き換えることができる。When the number of stages of the correlator is N, the clock pulse of the binary up-counter 1 clock input 1010 is N-1 times and the clock pulse of the binary up-counter 2 clock input 1030 is received N times for the interruption of the reference signal. By performing the integration and reset of the integrator of each correlator N times once, the parallel cross-correlator output 1200 can be obtained at a speed corresponding to N interrupts. Further, the binary up counter 1 and the binary up counter 2 can be replaced with down counters by changing the connection between the multiplexer and the correlator.
（５）発明の効果 以上述べたように、本発明よる並列相互相関器では、そ
の相互相関信号の出力形式が通常のスライディング相関
器とほぼ同様である。このため従来まで用いられていた
スライディング相関器を本発明による並列相互相関器に
簡単に置き換えることができる。また相関器の段数Ｎは
必要に応じて任意に大きくできるなど、相互相関器の設
計・構成する場合の自由度が高い。(5) Effects of the Invention As described above, in the parallel cross-correlator according to the present invention, the output form of the cross-correlation signal is almost the same as that of a normal sliding correlator. Therefore, the sliding correlator used until now can be easily replaced by the parallel cross correlator according to the present invention. Further, the number of stages N of the correlators can be arbitrarily increased as required, and thus the degree of freedom in designing and configuring the cross correlators is high.
本発明によれば、相互相関の計算時間を必要に応じて任
意かつ大幅に低減できるため、相互相関器の一種であ
る、スペクトルアナライザ、レーダー、相関受信機等の
測定器、通信機等に広く応用することにより高性能な装
置を実現でき、その効果は大なるものである。According to the present invention, the calculation time of cross-correlation can be arbitrarily and significantly reduced as necessary, and therefore, it is widely used in spectrum analyzers, radars, measuring instruments such as correlation receivers, communication devices, etc. By applying it, a high-performance device can be realized, and its effect is great.
第１図は通常のスライディング相関器のブロック図であ
って、１は相関器入力信号、２はスライディングする参
照信号を発生する参照信号発生器、３は乗算器、４は積
分器である。 第２図は本発明の一実施例を示す概念構成図である。図
中の10は相関器入力信号、11はスライディングする参照
信号を発生する参照信号発生器、100はマルチプレクサ
１、101はマルチプレクサ１の第１入力、102はマルチプ
レクサ１の第２入力、103はマルチプレクサ１の第３入
力、104はマルチプレクサ１の第４入力、105はマルチプ
レクサ１の出力、106はマルチプレクサ１の切替え制御
信号入力、200はマルチプレクサ２、201はマルチプレク
サ２の第１入力、202はマルチプレクサ２の第２入力、2
03はマルチプレクサ２の第３入力、204はマルチプレク
サ２の第４入力、205はマルチプレクサ２の出力、206は
マルチプレクサ２の切り替え制御信号入力、300はマル
チプレクサ３、301はマルチプレクサ３の第１入力、302
はマルチプレクサ３の第２入力、303はマルチプレクサ
３の第３入力、304はマルチプレクサ３の第４入力、305
はマルチプレクサ３の出力、306はマルチプレクサ３の
切替え制御信号入力、400はマルチプレクサ４、401はマ
ルチプレクサ４の第１入力、402はマルチプレクサ４の
第２入力、403はマルチプレクサ４の第３入力、404はマ
ルチプレクサ４の第４入力、405はマルチプレクサ４の
出力、406はマルチプレクサ４の切替え制御信号入力、5
00は４段の遅延素子、501は遅延素子の１段目出力、502
は遅延素子の２段目出力、503は遅延素子の３段目出
力、504は遅延素子の４段目出力、600は相関器１、601
は乗算器、602は積分器、700は相関器２、701は乗算
器、702は積分器、800は相関器３、801は乗算器、802は
積分器、900は相関器４、901は乗算器、902は積分器、1
000は相関器入力切替えマルチプレクサ制御信号発生用
２ビット２進アップカウンタ１、1010は２進アップカウ
ンタ１クロック入力、1020は２進アップカウンタ１出
力、1100は積分器出力切り替えマルチプレクサ11、1110
は２進アップカウンタ２出力、1120は積分器出力切替え
マルチプレクサ制御信号発生用２ビット２進アップカウ
ンタ２、1130は２進アップカウンタ２クロック入力、12
00は並列相互相関器出力である。 マルチプレクサ１、マルチプレクサ２、マルチプレクサ
３、マルチプレクサ４及び、マルチプレクサ10はそれぞ
れ４入力１出力で、マルチプレクサ切り替え制御信号が
２進で「00」のときマルチプレクサの第１入力がマルチ
プレクサから出力され、「01」のとき第２入力が、「1
0」のとき第３入力が、「11」のとき第４入力がそれぞ
れ出力される。FIG. 1 is a block diagram of a conventional sliding correlator, in which 1 is a correlator input signal, 2 is a reference signal generator for generating a sliding reference signal, 3 is a multiplier, and 4 is an integrator. FIG. 2 is a conceptual block diagram showing an embodiment of the present invention. In the figure, 10 is a correlator input signal, 11 is a reference signal generator for generating a sliding reference signal, 100 is a multiplexer 1, 101 is a first input of the multiplexer 1, 102 is a second input of the multiplexer 1, and 103 is a multiplexer. 1 is a third input, 104 is a fourth input of the multiplexer 1, 105 is an output of the multiplexer 1, 106 is a switching control signal input of the multiplexer 1, 200 is a multiplexer 2, 201 is a first input of the multiplexer 2, 202 is a multiplexer 2 2nd input of 2
03 is the third input of the multiplexer 2, 204 is the fourth input of the multiplexer 2, 205 is the output of the multiplexer 2, 206 is the switching control signal input of the multiplexer 2, 300 is the multiplexer 3, 301 is the first input of the multiplexer 3, 302
Is the second input of the multiplexer 3, 303 is the third input of the multiplexer 3, 304 is the fourth input of the multiplexer 3, 305
Is an output of the multiplexer 3, 306 is a switching control signal input of the multiplexer 3, 400 is a multiplexer 4, 401 is a first input of the multiplexer 4, 402 is a second input of the multiplexer 4, 403 is a third input of the multiplexer 4, and 404 is A fourth input of the multiplexer 4, 405 is an output of the multiplexer 4, 406 is a switching control signal input of the multiplexer 4, 5
00 is a 4-stage delay element, 501 is the first stage output of the delay element, 502
Is the second output of the delay element, 503 is the third output of the delay element, 504 is the fourth output of the delay element, 600 is the correlator 1, 601
Is a multiplier, 602 is an integrator, 700 is a correlator 2, 701 is a multiplier, 702 is an integrator, 800 is a correlator 3, 801 is a multiplier, 802 is an integrator, 900 is a correlator 4, and 901 is a multiplier. Vessel, 902 is integrator, 1
000 is a 2-bit binary up counter 1 for generating a correlator input switching multiplexer control signal, 1010 is a binary up counter 1 clock input, 1020 is a binary up counter 1 output, and 1100 is an integrator output switching multiplexer 11, 1110.
Is a binary up counter 2 output, 1120 is a 2-bit binary up counter 2 for generating an integrator output switching multiplexer control signal, 1130 is a binary up counter 2 clock input, 12
00 is the parallel cross-correlator output. The multiplexer 1, the multiplexer 2, the multiplexer 3, the multiplexer 4, and the multiplexer 10 each have 4 inputs and 1 output, and when the multiplexer switching control signal is "00" in binary, the first input of the multiplexer is output from the multiplexer and "01". When the second input is "1
When it is "0", the third input is output, and when it is "11", the fourth input is output.
Claims (1)
時間だけ遅延させる複数の遅延手段と、 各遅延手段から各々出力されるＮ個の参照信号の出力先
を、参照信号発生手段からの信号がＮ回スライディング
する間に「Ｎ−１」回だけ切替えるＮ個の切替手段と、 各切替手段によって切替えられたＮ個の参照信号夫々に
対応して設けられた、一方の入力端子に参照信号を、他
方の入力端子に被相関信号たる相関器入力信号を受ける
Ｎ個の相関手段と、 各相関手段からの信号を前記参照信号発生手段からの信
号がＮ回スライディングする間にＮ回の切替を行う相関
出力切替手段と、 を備え、前記相関出力切替手段からの信号を相関器出力
として得る並列相互相関器。1. A reference signal generating means for generating a reference signal, a plurality of delay means for delaying the reference signals from the reference signal generating means by different delay times, respectively, and N number of output signals from each delay means. The output destination of the reference signal is switched to N switching means for switching “N−1” times while the signal from the reference signal generating means is sliding N times, and N reference signals switched by each switching means. Correspondingly provided N reference means for receiving the reference signal at one input terminal and the other input terminal for receiving the correlator input signal as the correlated signal, and the reference signal generating means for the signals from the respective correlation means. And a correlation output switching means for switching N times while the signal from is sliding N times, and a signal from the correlation output switching means is obtained as a correlator output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62236194A JPH077384B2 (en) | 1987-09-22 | 1987-09-22 | Parallel cross-correlator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62236194A JPH077384B2 (en) | 1987-09-22 | 1987-09-22 | Parallel cross-correlator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01125668A JPH01125668A (en) | 1989-05-18 |
| JPH077384B2 true JPH077384B2 (en) | 1995-01-30 |
Family
ID=16997170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62236194A Expired - Lifetime JPH077384B2 (en) | 1987-09-22 | 1987-09-22 | Parallel cross-correlator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077384B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3377451B2 (en) * | 1998-08-26 | 2003-02-17 | シャープ株式会社 | Matched filter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5999835A (en) * | 1982-11-29 | 1984-06-08 | Nec Corp | Synchronizing device of spread frequency communication by frequency hopping |
-
1987
- 1987-09-22 JP JP62236194A patent/JPH077384B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01125668A (en) | 1989-05-18 |
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