JPH077396A - Clock duty variable circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To configure a duty variable circuit with a wide operating frequency and a simple circuit regardless of the input clock size. [Composition] FF1 is set at the rising edge of the input clock, and its output is converted into a ramp voltage by the integrating circuit 3 and when it exceeds the set value of the comparator 3, when it exceeds the set value, the FF1 is reset by the output of the comparator 3 and the pulse width is Configure to get. Also, a part of the output of FF1 is D by LPF4.
The voltage is converted into a C voltage, and the differential amplifier circuit 5 takes a difference from the reference voltage Vr (adjustable), and the time constant of the integrating circuit 2 is changed by the difference output. A diode 6 is provided between the output side of the FF1 and the output of the integrating circuit 2, and when the lamp voltage exceeds the set number of the comparator 3, the output of the FF1 becomes low level and the diode 6 is discharged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock duty variable circuit used when changing a clock width in a digital electronic device.

[0002]

2. Description of the Related Art A conventional circuit of this type is shown in FIG.
It is composed of a PF 11, an amplifier circuit 12, and a comparator 13. As shown in the waveform diagram of FIG. 5, the input clock is set to LPF.
A sine wave or a waveform corresponding to the sine wave is generated by 11, and the duty of the output clock is changed by the comparison voltage (slice voltage) by the comparator 13 after being amplified by the amplifier circuit 12 to a predetermined level. For example, the comparison voltage is V / 2 to V /
By changing to 4, the pulse width of the output can be changed from T / 2 to 3 / 4T.

[0003]

With such a configuration, the duty of the output changes depending on the size of the input and the duty ratio, and as a countermeasure, the comparison voltage of the comparator is reset or the AGC is added to the amplifier circuit. It was necessary to keep the output level constant over time. Also, L
Since the PF needs to attenuate the harmonic component, it has to be changed depending on the cutoff frequency.

[0004]

In order to eliminate these drawbacks, the present invention takes an output obtained by adding an input clock to a flip-flop circuit (hereinafter referred to as FF) and outputs a part of the output. Is input to the LPF and the integrating circuit. The lamp output of the integrating circuit is input to the positive terminal side of the diode in which the negative terminal is connected to the comparator and the FF output. This diode cooperates with the integrating circuit to form a discharge path. The output of the comparator is F
In addition to the clear terminal of F, reset. The output of the LPF is input to the differential amplifier circuit, and the output is configured to change the resistance of the integrating circuit to adjust the duty. Hereinafter, embodiments will be described in detail with reference to the drawings.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an embodiment, and FIGS. 2 and 3 are time charts of operations when the duty ratios of input clocks are different. In FIG. 1, 1 is FF, 2 is an integrating circuit, 3 is a comparator, 4 is an LPF, and 5 is a reference voltage Vr.
Is a differential amplifier circuit, 6 is a diode.

To operate this, the clock (a) from the input terminal 7 is input to the clock input terminal CK of the FF1 and the output is taken out from the Q terminal. The FF1 operates at the rising edge or the falling edge of the clock, but for convenience of explanation, the FF1 will be unified at the rising edge. The output becomes high level H at the first rising (b).

When the output becomes H, the capacitor (not shown) of the integrating circuit 2 starts to be charged and its voltage becomes higher. When the voltage becomes higher than the set reference voltage of the comparator 3, the output of the comparator 3 becomes low level L (d).

Next, since the CLR terminal of the FF becomes L, it is reset and the output becomes L. When the output becomes L, the charge stored in the capacitor of the integrating circuit 2 is discharged through the diode 6, and the voltage becomes almost 0 (c). Then, at the next rising edge of the clock, the output becomes H again, and the above operation is repeated. In this case, the output of LPF4 is the DC component of the output of FF1. The DC component changes depending on the duty, and when the duty is 50%, FF1
The power supply voltage is about 1/2.

When the other input terminal of the differential amplifier circuit 5 is set to the above voltage (about 1/2 of the power supply voltage of FF1) (e), when the output of FF1 changes its duty from 50% duty. The output of the differential amplifier circuit 5 changes greatly. When the duty becomes small, the time constant of the integrating circuit is made large, and the operation of increasing the duty is delayed by delaying the time when the FF1 changes from H to L. The opposite is true when the duty increases. As a result, the output duty of the FF1 becomes constant at 50%.

As a method of changing the time constant of the integrating circuit 2 by the output voltage of the differential amplifying circuit 5, the output of the differential amplifying circuit 5 is connected to the gate of the FET and the resistance value R between the drain and the source is changed. The circuit may be configured so that the resistance value R is changed according to the output voltage of the dynamic amplification circuit 5 and becomes the R of the time constant CR of the integration circuit 2 or a function thereof.

When the duty is set to 25%, the voltage at the other input terminal of the differential amplifier circuit 5 may be set to approximately 1/4 of the power supply voltage of the FF1 (FIG. 3). That is, the duty ratio may be applied to the other input end of the differential amplifier circuit 5 with a voltage having a duty ratio substantially equal to the power supply voltage of the FF1. That is, the input duty ratio and the input level are not affected, and the LPF4 is
Since only the DC component of F1 needs to be output, its cutoff frequency can be set with almost no effect on its input frequency, and the circuit can often be a simple CR stage. Therefore, the operating frequency range can be widened.

Further, even if the setting level of the comparator 3 is controlled by the output of the differential amplifier circuit 5, the same operation can be performed.

[0013]

As described above, since the circuit can be constructed with a simple circuit and the operating frequency can be wide, the range of application is wide. Therefore, there is an advantage that it becomes small in size and low in cost by mass-producing it as an IC.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a time chart of an example of the present invention.

FIG. 3 is a time chart of an example of the present invention.

FIG. 4 is a configuration diagram of a conventional example.

FIG. 4 is a time chart of a conventional example.

[Explanation of symbols]

 1 Flip-flop circuit 2 Integration circuit 3 Comparator 4 LPF 5 Differential amplifier circuit 6 Diode 7 Input terminal 8 Output terminal

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[Procedure amendment]

[Submission date] March 23, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a time chart of an example of the present invention.

FIG. 3 is a time chart of an example of the present invention.

FIG. 4 is a configuration diagram of a conventional example.

FIG. 5 is a time chart of a conventional example.

[Explanation of Codes] 1 flip-flop circuit 2 integration circuit 3 comparator 4 LPF 5 differential amplifier circuit 6 diode 7 input terminal 8 output terminal

Claims (1)

[Claims] 1. An output of a flip-flop circuit (1) for inputting and setting a clock is supplied to an output terminal (8), and the output is input to a negative terminal of a diode (6) and an integrating circuit (2), respectively. Then, the output of the integration circuit (2) is applied to the positive terminal of the diode (6) and the comparator (3), and the flip-flop circuit () is output by a signal output when the set value is exceeded in the comparator (3). 1) is configured to be reset, further, the output of the flip-flop circuit (1) is converted into DC by the LPF (4), and the differential output between this and the reference voltage Vr of the differential amplifier circuit (5) The clock duty variable circuit is configured to control the time constant of the integration circuit or the set value of the comparator (3).