JPH077774B2 - Method for manufacturing compound semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a compound semiconductor device having a refractory metal electrode, and more particularly to a refractory metal electrode suitable for wiring formation.

[Conventional technology]

The GaAs MESFET, which is the basic element of the GaAs IC, uses a refractory metal gate electrode as described in Nikkei Microdevice July 1986, p65-p84, and uses this as a mask for ion implantation of an n ⁺ layer. High performance has been realized by the self-aligned MESFET. As a refractory metal gate electrode of self-aligned MESFET, Schottky characteristics do not deteriorate even when high temperature annealing is performed. Refractory metals containing tungsten such as titanium tungsten (TiW) are used. When the n ⁺ layer is formed by the self-alignment technique, the gate electrode must have a vertical cross-sectional shape because the n ⁺ layer is ion-implanted using these refractory metal gate electrodes as a mask. This is because if the gate electrode has a trapezoidal cross section, for example, when ion implantation is performed on the n ⁺ layer, the ion is implanted through the lower portion of the gate metal taper, and therefore the gate metal and the high-concentration n ⁺ layer are directly implanted. This is because the reverse breakdown voltage of the Schottky electrode is significantly deteriorated due to the contact. To process vertical cross sections of refractory metals including tungsten, use NF ₃ or S for example.
Reactive ion etching technology using fluorine-based gases such as F ₆ and CF ₄ is used.

[Problems to be Solved by the Invention]

In the above-mentioned conventional technology, all the gate electrode cross sections are processed vertically, and the covering property of the wiring metal in the case of forming the wiring for riding on the refractory metal gate electrode is not considered. There was a problem of breaking the wire.

An object of the present invention is to improve the reverse breakdown voltage of the Schottky characteristic by processing the gate electrode cross section of the part formed in self-alignment with the n ⁺ layer at the same time as the gate metal cross section of the part where the wiring metal rides on the gate electrode. Is to form a taper shape to improve the coverage of the wiring metal and prevent disconnection at this riding portion.

[Means for Solving the Problems]

The above-mentioned purpose is that the portion where the cross section of the gate electrode is processed vertically is composed of the high melting point metal containing tungsten as the gate electrode material, while the portion of the gate electrode material on which the wiring metal rides is formed on the high melting point metal containing tungsten. After forming a structure in which at least one thin film of silicon, silicon dioxide, phosphorus glass, boron glass, or silicon nitride is laminated, these both parts are made of a fluorine-based material such as NF ₃ , CF ₄ , or SF ₆ by using a photoresist as a mask. This can be achieved by dry etching using the above gas.

[Action]

FIG. 1 shows a diagram for explaining the present invention. FIG. 1 (a) is a sectional view and FIG. 1 (b) is a plan view. After the tungsten silicide 2 is deposited on the entire surface of the compound semiconductor substrate 1, a thin silicon film 3 is laminated on a part of the tungsten silicide 2. At this time, the film thickness of the tungsten silicide 2 is free, but is usually selected to be 100 nm to 1 μm. The thickness of the thin silicon film 3 may be 1 nm or more, but 10 to 50 nm is effective.
After forming the above laminated structure, an organic photoresist pattern 4 is formed for forming a gate metal pattern. Using the organic photoresist pattern 4 as a mask, the silicon thin film 3 and the tungsten silicide 2 are subjected to reactive ion etching with a fluorine-based gas. For example, pressure of 5 Pa in the reaction tank of a parallel plate type reactive ion etching device.
NF ₃ gas is introduced, a high frequency of 13.56 MHz is applied to a counter electrode having a diameter of 50 cm, and discharge is performed at a power of 300 W, the silicon film 3 and the tungsten silicide 2 can be etched. 2 (a) and 2 (b) show the cross-sectional shape of the tungsten silicide processed by the above method. FIG. 2 (a) shows a processed sectional view of the AA ′ portion shown in FIG. 1 (b), and FIG. 2 (b) shows a processed sectional view of the BB ′ portion shown in FIG. 1 (b). Show. In the AA ′ cross section in which the silicon thin film 3 is stacked on the tungsten silicide 2, the cross section of the tungsten silicide 2 is tapered as shown in FIG. 2 (a). On the other hand, the silicon thin film 3 is not stacked on the tungsten silicide 2B
In the B'section, the section of the tungsten silicide 2 is processed almost vertically as shown in FIG. 2 (b). Generally, the processed cross section becomes vertical due to reactive ion etching. (1) Anisotropic etching occurs because ions are accelerated in the vertical direction and enter the substrate by the negative self-bias voltage due to plasma discharge. (2) Various reactive gas active species generated by plasma discharge decompose the organic photoresist, and at the same time, a polymer (a thin film-like product of the photoresist and the reactive gas) is successively formed on the sidewall of the processed section of the tungsten silicide, and The cause is considered to be anisotropic etching to prevent etching. When the silicon thin film 3 is stacked on the tungsten silicide 2 as shown in FIG. 2 (a), it becomes impossible to form a polymer on the side wall portion which causes the above anisotropic etching, so that the lateral etching is performed. It is considered that the taper is processed because the speed increases and the etching becomes isotropic. However, at present, this detailed mechanism has not been clarified. According to the experiment, it is a very local effect that the tungsten silicide 2 has a tapered cross section because the silicon film 3 is laminated. That is, 1 μm from the silicon laminated part
In the portions separated by the distance described above, the effect of preventing polymer formation disappears, and the cross section of the tungsten silicide 2 becomes vertical. The present invention utilizes such a phenomenon, and as shown in FIG. 1 (b), the cross section of the gate portion BB 'of the heat-resistant gate metal is processed vertically, and the cross section of the wiring connection portion AA' is separated by only about 10 μm. Is to be processed into a taper shape. This makes it possible to eliminate disconnection of the wiring metal in the wiring portion without deteriorating the Schottky reverse breakdown voltage of the self-aligned heat-resistant gate electrode.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 3, 4, and 5. The present embodiment will be described only by using a GaAs substrate, but the contents of the present invention are also effective for other compound semiconductors such as InP, GaAlAs, InAlAsP, InGaAs.

Example 1. GaAa MESFE according to the present invention is shown in FIGS. 3 (a) to 3 (j).
A procedure for forming an integrated circuit element using T is shown. First, in FIG. 3A, the channel active layer 6 is formed on the surface of the semi-insulating GaAs substrate 1 by the ion implantation method and the cap film activation annealing method. Cap layer 5 is CVD (chemical vapor deposition method, C hemical V apor D eposition) thick formed by method
This is a 200 nm SiO ₂ film. The channel active layer 6 is formed by implanting Si ⁺ ions with 2 to 6 × 10 ¹² ions / cm ² at an accelerating voltage of 75 KeV and annealing in hydrogen at 800 ° C. for 20 minutes by a cap annealing method. Next, in FIG. 3B, after removing the cap film 5, the tungsten silicide WS is sputtered.
ix2 and the silicon thin film 3 are laminated. WSix composition ratio is x
0.4 is suitable and the film thickness may be 100 nm to 1 μm, but 300 to 500 nm is optimal for sufficiently reducing the resistance and suitable for the planar process. The silicon thin film 3 is conveniently sputter deposited subsequent to WSix with silicon as the target. The sputtering conditions at this time are: substrate temperature is room temperature to 450 ° C, discharge gas is Ar, and pressure is 5 mT.
The orr and discharge power may be 0.5 W / cm ² at a high frequency of 13.56 MHz. The film thickness of the silicon thin film 3 may be 1 nm or more, but it is suitable to be 10 nm to 50 nm considering that it is suitable for a planar process and has excellent process controllability. Next, the process moves to FIG. 3 (c). The silicon thin film 3 is removed by a usual photolithography technique leaving a predetermined portion. To remove this silicon thin film, a normal reactive ion etching technique using a fluorine-based gas such as NF ₃ , CF ₄ or SF ₆ is used. However, in reactive ion etching using a fluorine-based gas, WSix is simultaneously etched with silicon. Therefore, when reactive ion etching the silicon thin film 3, it is necessary to remove only the silicon layer by time control. is there. Next, in FIG. 3D, an organic photoresist 4 is deposited on the portion where the gate electrode is to be formed. Next, in FIG. 3E, the WSix 2 is processed by reactive dry etching using a fluorine-based gas with the organic photoresist 4 as a mask. NF ₃ with a pressure of 5 Pa was used as the reaction gas, and the discharge was performed at a high frequency of 13.56 MHz, using an electrode with a diameter of 100 cm.
Apply 00W. In this case, the negative DC self-bias voltage applied to the wafer is 65V. The tungsten silicide in the portion where the silicon thin film 3 is not laminated is processed to have a vertical sectional shape, but the sectional shape of the portion where the silicon thin film is laminated (portions D and E in FIG. 3 (e)) is It is processed into a taper shape. In FIG. 3 (f), photoresist 7
Using the mask as a mask, Si ⁺ ions 8 are implanted. At this time, the accelerating voltage is 100 KV and the implantation amount is 3 × 10 ¹³ pieces / cm ² . Next, the process moves to FIG. 3 (g). After depositing the surface protection film 9 on the entire surface, anneal in hydrogen at 800 ° C. for 15 minutes,
The high concentration active layer 10 is activated. Surface protective film is SiH ₄ and N ₂ O
As a raw material gas, a 300 nm thick SiO ₂ film deposited by a plasma chemical vapor deposition method is suitable. Then, the process moves to FIG. 3 (h). After forming a resist pattern 11 having an opening in a portion where an ohmic electrode is formed by photolithography, the surface protection film 9 is etched by reactive ion etching. As the etching gas, CHF ₃ + C ₂ F ₆ is preferably used at a pressure of 60 mTorr. Next, moving to FIG. 3I, an AuGe (60 nm) / Ni (10 nm) / Au (200 nm) ohmic electrode 12 is deposited on the entire surface. The thickness of the ohmic electrode is
The lift-off of the next process is easy, so 250 ~ 3
It is preferably set to 00 nm. Next, the photoresist 11 is removed with a photoresist removing agent, and the unnecessary portion of the ohmic electrode is removed by the lift-off method to complete the process as shown in FIG. 3 (j). Since the tungsten silicide 2 is processed into a tapered shape in the portions indicated by D and E in FIG. 3 (j),
The ohmic electrodes 12 that are wired up and connected are connected without breaking. Figure 4 shows the GaAs MESFE described in Figure 3.
The top view of the integrated circuit using T is shown. The sectional view of FIG. 3 shows the CC ′ section of FIG. In FIG. 4, the gate electrode of the MESFET indicated by the symbol T1 and the drain electrode of the MESFET indicated by the symbol T2 are connected through the tapered connecting portion D. Further, the FET of T2 has a drain and a gate short-circuited through a tapered connecting portion E. According to this embodiment, since the cross-section of the high-melting point gate metal is processed into a taper shape at the place where the high-melting point gate metal is directly connected to the ohmic electrode, there is no disconnection at the stepped-on portion. Also, the silicon thin film 3 with a thickness of 1 nm to 50 nm is 800 °
Since it is polycrystallized by the high temperature annealing and its resistance becomes low, electrical connection is also good. Further, it is effective to use a silicon thin film doped with phosphorus or boron to reduce the electric resistance. In this embodiment, the case of using tungsten silicide as the high melting point gate metal has been described.
Other than that, the same effect can be obtained by using tungsten bolite (WBx), tungsten nitride (WNx), tungsten aluminum (WAlx), and titanium tungsten (TiW). Also, instead of the silicon thin film 3, SiO ₂ , phosphorus glass, boron phosphorus glass, or silicon nitride has the same effect. However, when these insulating films are used, it is necessary to first process the insulating films in the step of FIG. 3 (e) and then process the refractory gate metal, and FIG. 3 (i). In this step, these insulating films must be removed by etching before the ohmic electrode 12 is deposited.

It will be described using a MESFET of Example 2. LDD (L ightly D opped D rain) structure. The manufacturing process is shown in FIG.
The steps shown in FIGS. 3 (e) and 3 (g) to 3 (j) are completely the same, and therefore will be omitted. That is, after moving to FIG. 5 (a) after FIG. 3 (e), SiO ₂ 13 is deposited to a thickness of 300 nm on the entire surface. Next, as shown in Fig. 5 (b), CHF with a pressure of 60 mTorr
SiO ₂ 13 is anisotropically dry-etched using ₃ + C ₂ F ₆ gas to form a sidewall 14 on the side surface of the tungsten silicide 2. The side wall 14 is formed only in the portion where the cross-sectional shape of the tungsten silicide 2 is vertical, and is not formed in the tapered portion because the silicon thin films 3 are laminated. Next, move to FIG. 5 (c). Using the photoresist 7 as a mask, Si ⁺ ions 8 are ion-implanted. The acceleration voltage at this time is 100 KV and the implantation amount is 5 × 10 ¹³ pieces / cm ² . Side wall
In the portion where 14 is formed, the side wall separates the gate metal 2 and the high-concentration active layer 10 by about 0.3 μm, so that the reverse breakdown voltage of Schottky is improved. The following steps are the same as in FIG. In the present embodiment, the reverse breakdown voltage of the Schottky electrode can be improved by the LDD structure, and at the same time, since the cross-sectional shape of the gate is tapered at the portion where the ohmic electrode rides on the gate electrode, the wiring is not broken, which is preferable. is there.

〔The invention's effect〕

According to the present invention, since the cross-sectional shape of the required portion of the high melting point gate metal can be controlled to be tapered or vertical, the reverse breakdown voltage of the Schottky characteristic can be kept sufficiently high without disconnecting the ohmic electrode and the gate electrode. Can be connected.

[Brief description of drawings]

1 (a), 2 (a) and 2 (b) are sectional views for explaining the essential points of the present invention, FIG. 1 (b) is a plan view, and FIG. 3 is an illustration of the present invention. FIG. 4 is a plan view of the GaAs integrated circuit according to the first embodiment, FIG. 4 is a plan view of the GaAs integrated circuit shown in FIG. 3, and FIG. 5 is a schematic view of the GaAs integrated circuit according to the second embodiment of the present invention. FIG. DESCRIPTION OF SYMBOLS 1 ... GaAs substrate, 2 ... Tungsten silicide, 3 ... Silicon thin film, 4,7,11 ... Organic photoresist, 5 ... SiO ₂ surface protective film, 6 ... Channel active layer, 8 ... Si ion, 9 ... Cap film, 10 … High concentration active layer, 12… Ohmic electrode, 13…
SiO ₂ film, 14 ... Side wall.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 29/41 29/812 (72) Inventor Hiroshi Yanagisawa 1-280 Higashi Koigokubo, Kokubunji, Tokyo Hitachi Central In-house Examiner Kunio Matsumoto (56) References JP 62-54966 (JP, A) JP 61-87380 (JP, A)

Claims (1)

[Claims] 1. A step of depositing a first layer made of a refractory metal containing at least tungsten on a compound semiconductor substrate, and silicon, silicon dioxide, phosphorus glass, boron phosphorus glass, or nitride on a part of the first layer. A step of laminating a second layer formed of at least one kind of thin film of silicon, and a portion where the first layer and the second layer are laminated and a portion of only the first layer using a resist as a mask Dry etching is performed using a fluorine-based gas, and the processed cross-sectional shape of the first layer in the portion where the first layer and the second layer are laminated is processed into a tapered shape, and only the first layer is processed. The step of processing the processed cross-sectional shape of the first layer closer to the vertical than the taper, and electrically connecting to the first layer and connecting the first layer to the compound semiconductor substrate side. Is on the opposite side Method of manufacturing a compound semiconductor device, characterized in that it comprises a step of forming a et first of said tapered working portion through which extends on the compound semiconductor substrate interconnection layers.