JPH077813B2 - Ceramic package - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] By forming an input / output terminal, a semiconductor chip, and a mounting portion on the same substrate and fitting them into a copper block (housing), deterioration of characteristics due to a package shift is prevented. Achieve cost reduction and ground impedance reduction.

[Industrial application field]

The present invention relates to a ceramic package, and more particularly, to an improvement of a super high frequency ceramic package on which an FET chip or the like is mounted.

[Conventional technology]

Ultra-high frequency ceramic packages (hereinafter simply referred to as ceramic packages) that incorporate FET chips, etc. have used a thick film metallized surface on the outside of the ceramic substrate as the ground conductor, but the structure of the ground conductor increases as the operating frequency increases. Has been improved, the metallized surface has been replaced with a metal block substrate (housing), and a package with reduced ground impedance has been developed. This type of package consists of three structures, a metal block substrate, a ceramic with laminated input and output terminals.

The above-mentioned package is shown in FIG. 2, where FIG. 2 (a) is a plan view of the package, and FIGS. 2 (b) and 2 (c) are cross-sections taken along line BB and line CC of FIG. In the figure, in the figure,
31 is a copper block (metal block base), 32a and 32b are ceramic bodies, 33 is a ground block, 34 is an input terminal, 35 is an output terminal, 36 is a metallized layer, 37 is a semiconductor chip (hereinafter simply referred to as a chip), 38 is The gate wire, 39 and 41 are source wires, 40 is a drain wire, and 42 is a laminated portion. The illustrated package has a copper block 31 and two ceramic bodies 32a and 32b as main components.

[Problems to be solved by the invention]

The present inventor has found the following three problems with the package described above.

When the ceramic bodies 32a and 32b are fitted together, there is a positional deviation between the input terminals and the output terminals as shown in the plan view of FIG. 3, which causes variations in FET characteristics and performance degradation.

Since the ground block is formed of a small metal piece for grounding, the grounding impedance is relatively high and the number of assembly steps is increased.

Since the number of parts is large, it is necessary to use a positioning jig for assembly, which increases the manufacturing cost.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a package in which the displacement of input / output terminals is eliminated and the ground block is made to reduce the ground impedance, and the number of constituent parts is reduced. And

[Means for solving problems]

FIG. 1A is a plan view of an embodiment of the present invention, and FIGS. 1B and 1C are sectional views taken along line BB and CC in FIG. 1A. In the figure, 11 is a copper block, 12 is a ceramic substrate, 13 is an input terminal, 14 is an output terminal, 15 is a gate wire, 16 and 18 are source wires, 17 is a drain wire, 19 is F
An ET chip, 20 is a metallization layer for mounting a FET chip, 21 is a metallization layer provided on the ceramic body 12, and 22 is a laminating portion.

In FIG. 1, the metallized layer 2 on which the FET chip 19 is mounted
0 and laminating section 22 are provided, and input terminal 13 and output terminal 14
The ceramic substrate 12 on which is formed is H-shaped, and the concave portion 12a of the ceramic substrate 12 and the convex portion 11a of the copper block are fitted to each other.

[Action]

In the above-mentioned ceramic package, the ground is taken by the copper block 11, so the ground impedance is small, and the two large parts are the copper block 11 and the ceramic substrate 12, so the assembly process is small and the cost is reduced.

Embodiments Embodiments of the present invention will be described below in detail with reference to the drawings.

Referring again to FIG. 1, the ceramic substrate 12 has a metallized layer 20 for mounting a semiconductor chip, for example, an FET chip 19, and an input terminal portion having a laminating portion 22 (a portion where the input terminal 13 is formed). An output terminal portion (a portion having the output terminal 14) is formed. The metallization layer 20 for mounting the FET chip is also gold-plated like the metallization layer 21 of the input / output terminals. The ceramic substrate 12 is H-shaped and provides a recess 12a in the central portion. With such a configuration, the input terminal 13 and the output terminal 14 are aligned on the same line as the FET mounted on the metallized layer 20, and the positional displacement of the input / output terminals and the positional displacement of the FET chip 19 are eliminated. , The conventional problems described with reference to FIG. 3 are solved. The FET chip 19 is connected to the input terminal 13 by the gate wire 15 and connected to the output terminal 14 by the drain and wire 17,
It is connected to the copper block 11 by source wires 16 and 18.

As described above, the ceramic substrate 12 has an H-shaped structure in which the concave portion 12a is formed. The concave portion 12a and the convex portion 11a of the copper block 11 are fitted to each other and, for example, they are bonded with silver solder. Thus, the conventional three-component number is reduced to two, and the positioning of the copper block 11 and the ceramic substrate 12 does not require a conventional positioning jig, thereby reducing the package and the manufacturing cost.

Regarding the electrical connection, conventionally, an earth block made of a small metal piece was used for earthing, but in the embodiment of the present invention, since the source wires 16 and 18 are connected to the copper block 11,
Reduce the ground impedance.

〔The invention's effect〕

As described above, according to the present invention, the input / output terminals and the FET chip mounting metallization layer are formed on the same ceramic substrate, the ground block is provided in a part of the copper block, and the component is composed of the copper block and the ceramic substrate. By setting the number of points to two, the conventional three problems can be solved, and while the reliability of the ceramic package is improved, the manufacturing cost thereof can be reduced.

[Brief description of drawings]

1 (a) is a plan view of an embodiment of the present invention, FIGS. 1 (b) and 1 (c) are cross-sectional views taken along line BB and CC of FIG. 1 (a), and FIG. 2 (a). ) Is a plan view of the conventional example, (b) and (c) of FIG. 3 are cross-sectional views taken along line BB and CC of FIG. 3 (a), and FIG. 3 is a plan view showing problems of the conventional example. It is a figure. In FIG. 1, 11 is a copper block, 11a is a convex part of the copper block, 12 is a ceramic substrate, 12a is a concave part of the ceramic substrate, 13 is an input terminal, 14 is an output terminal, 15 is a gate wire, 16 is a source wire, Reference numeral 17 is a drain wire, 18 is a source wire, 19 is a FET chip, 20 is a metallized layer for mounting the FET chip, 21 is a metallized layer, and 22 is a laminated portion.

Claims (1)

[Claims] 1. A package for mounting a semiconductor chip (19) for ultra high frequencies, wherein an input terminal (13) and an output terminal (14) are provided on both sides of an H-shaped ceramic substrate (12) having a recess (12a). ) Is provided, the semiconductor chip (19) is bonded onto the metallized layer (20) of the ceramic substrate (12), and the gate wire (15) and the drain wire (17) are respectively input terminal parts. And the output terminal part, and the concave part (12a) of the ceramic substrate and the convex part (11a) of the copper block (11) are fitted and bonded together, and the source wires (16) and (18) are made of the copper block. A ceramic package characterized by being connected to (11).