JPH0778848A - Semiconductor device mounting method - Google Patents
Semiconductor device mounting methodInfo
- Publication number
- JPH0778848A JPH0778848A JP5221934A JP22193493A JPH0778848A JP H0778848 A JPH0778848 A JP H0778848A JP 5221934 A JP5221934 A JP 5221934A JP 22193493 A JP22193493 A JP 22193493A JP H0778848 A JPH0778848 A JP H0778848A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- strain rate
- deformation
- solder bump
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】バンプの再溶融工程を必要とせず、従来より格
段に生産性を向上可能なバンプ接合式の半導体チップの
実装方法を提供する。
【構成及び効果】本発明の半導体チップの実装方法は、
はんだバンプの変形速度を10μm/sec以下とする
ことを特徴としている。このようにすれば、はんだ溶融
工程を追加することなしに良好な接合強度が得られるこ
とがわかった。好適な態様において、前記はんだバンプ
の変形速度は1〜3μm/sec以下とされる。このよ
うにすれば、はんだ溶融工程を追加することなしにそれ
とほとんど遜色が無い接合強度が得られることがわかっ
た。好適な態様において、歪み速度をεt 、変形抵抗を
σ、比例定数をk、歪み速度依存指数をm、σ=k×ε
t m とする場合に、mが0.3以上の範囲で前記圧接を
実施すれば、溶融はんだ並みの接合強度が得られること
がわかった。
(57) [Abstract] [Purpose] To provide a bump bonding type semiconductor chip mounting method which does not require a step of remelting bumps and can remarkably improve productivity. [Structure and Effect] The semiconductor chip mounting method of the present invention is
It is characterized in that the deformation rate of the solder bumps is set to 10 μm / sec or less. It was found that good bonding strength can be obtained without adding a solder melting step. In a preferred aspect, the deformation rate of the solder bumps is 1 to 3 μm / sec or less. It has been found that this makes it possible to obtain a bonding strength almost comparable to that without adding a solder melting step. In a preferred embodiment, the strain rate is ε t , the deformation resistance is σ, the proportional constant is k, the strain rate dependent exponent is m, and σ = k × ε.
It has been found that, when t m is set, if the pressure welding is performed within a range of m of 0.3 or more, a bonding strength comparable to that of molten solder can be obtained.
Description
【0001】[0001]
【産業上の利用分野】この発明は、半導体装置のうち、
フェイスダウンで実装されるフリップチップICの実装
方法に関するものである。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device,
The present invention relates to a method of mounting a flip-chip IC mounted face down.
【0002】[0002]
【従来の技術】従来、フリップチップICのフェイスダ
ウン実装方法として、半導体チップの接続電極表面に形
成されたはんだバンプを配線基板の接続電極にその融点
未満の温度条件下で直接に圧接し、はんだバンプを塑性
変形して配線基板の接続電極と接合する方法が知られて
いる。2. Description of the Related Art Conventionally, as a face-down mounting method of a flip chip IC, a solder bump formed on the surface of a connecting electrode of a semiconductor chip is directly pressure-contacted to a connecting electrode of a wiring board under a temperature condition below its melting point, and soldering is performed. A method is known in which a bump is plastically deformed and bonded to a connection electrode of a wiring board.
【0003】[0003]
【発明が解決しようとする課題】しかしながら上記実装
方法では、はんだバンプの接合強度が溶融はんだ(はん
だリフロー)方式に比べて劣るので、接合後、はんだバ
ンプの再溶融工程を必要となる問題があった。本発明は
上記問題に鑑みなされたものであり、バンプの再溶融工
程を必要とせず、従来より格段に生産性を向上可能なバ
ンプ接合式の半導体チップの実装方法を提供すること
を、その目的としている。However, in the above mounting method, the bonding strength of the solder bumps is inferior to that of the molten solder (solder reflow) method, so that there is a problem that a remelting step of the solder bumps is required after the bonding. It was The present invention has been made in view of the above problems, and an object thereof is to provide a bump bonding type semiconductor chip mounting method that does not require a step of remelting bumps and can significantly improve productivity as compared with the conventional method. I am trying.
【0004】[0004]
【課題を解決するための手段】本発明の半導体チップの
実装方法は、半導体チップの接続電極表面に形成された
はんだバンプを配線基板の接続電極にその融点未満の温
度条件下で圧接し、前記はんだバンプを塑性変形して前
記配線基板の接続電極と合金接合する半導体装置の実装
方法において、前記はんだバンプの変形速度を10μm
/sec以下とすることを特徴とする。According to the method of mounting a semiconductor chip of the present invention, a solder bump formed on a surface of a connection electrode of a semiconductor chip is pressed against a connection electrode of a wiring board under a temperature condition below its melting point, In a method of mounting a semiconductor device in which a solder bump is plastically deformed to be alloy-bonded to a connection electrode of the wiring board, the solder bump has a deformation speed of 10 μm.
/ Sec or less.
【0005】好適な態様において、前記はんだバンプの
変形速度は1〜3μm/sec以下とされる。好適な態
様において、はんだバンプのSnとPbとの比率は30
〜70重量部対70〜30重量部とされる。好適な態様
において、はんだバンプはSnを61〜65wt%含む
共晶性はんだとされる。In a preferred mode, the deformation rate of the solder bumps is 1 to 3 μm / sec or less. In a preferred aspect, the ratio of Sn to Pb of the solder bump is 30.
˜70 parts by weight to 70 to 30 parts by weight. In a preferred embodiment, the solder bump is a eutectic solder containing 61 to 65 wt% Sn.
【0006】好適な態様において、歪み速度をεt 、変
形抵抗をσ、比例定数をk、歪み速度依存指数をm、σ
=k×εt m とし、その歪み速度依存指数mが0.3以
上の範囲で前記圧接を実施する。In a preferred embodiment, the strain rate is ε t , the deformation resistance is σ, the proportional constant is k, the strain rate dependent exponent is m, σ
= K × ε t m, and the pressure welding is performed in a range where the strain rate dependence index m is 0.3 or more.
【0007】[0007]
【作用及び発明の効果】第一発明の半導体チップの実装
方法は、はんだバンプの変形速度を10μm/sec以
下とすることを特徴としている。このようにすれば、は
んだ溶融工程を追加することなしに良好な接合強度が得
られることがわかった。The operation and effect of the invention The semiconductor chip mounting method of the first invention is characterized in that the deformation rate of the solder bumps is 10 μm / sec or less. It was found that good bonding strength can be obtained without adding a solder melting step.
【0008】好適な態様において、前記はんだバンプの
変形速度は1〜3μm/sec以下とされる。このよう
にすれば、はんだ溶融工程を追加することなしにそれと
ほとんど遜色が無い接合強度が得られることがわかっ
た。好適な態様において、はんだバンプのSnとPbと
の比率は30〜70重量部対70〜30重量部とされ
る。In a preferred mode, the deformation rate of the solder bumps is 1 to 3 μm / sec or less. It has been found that this makes it possible to obtain a bonding strength almost comparable to that without adding a solder melting step. In a preferred embodiment, the ratio of Sn to Pb of the solder bump is 30 to 70 parts by weight to 70 to 30 parts by weight.
【0009】実験によれば、この組成範囲のはんだは、
後述する歪み速度依存指数mが0.3以上となるので、
共晶はんだと同様に良好な接合強度が得られることがわ
かった。好適な態様において、はんだバンプはSnを6
1〜65wt%含む共晶性はんだとされる。According to experiments, solder having this composition range is
Since the strain rate dependence index m described later becomes 0.3 or more,
It was found that good joint strength can be obtained as with eutectic solder. In a preferred embodiment, the solder bump contains Sn of 6
The eutectic solder contains 1 to 65 wt%.
【0010】実験によれば、この組成範囲のはんだは、
後述する歪み速度依存指数mが0.3以上となるので、
共晶はんだと同様に良好な接合強度が得られることがわ
かった。好適な態様において、歪み速度をεt 、変形抵
抗をσ、比例定数をk、歪み速度依存指数をm、σ=k
×εt m とする場合に、その歪み速度依存指数mが0.
3以上の範囲で前記圧接を実施する。Experiments have shown that solders in this composition range
Since the strain rate dependence index m described later becomes 0.3 or more,
It was found that good joint strength can be obtained as with eutectic solder. In a preferred embodiment, the strain rate is ε t , the deformation resistance is σ, the proportional constant is k, the strain rate dependent exponent is m, and σ = k.
X ε t m , the strain rate dependence index m is 0.
The pressure welding is performed within a range of 3 or more.
【0011】この意味を説明すると、はんだバンプの接
合強度を溶融(合金)レベルに接近させるには、接合面
の一部ではなく全面において良好な接合を実現する必要
がある。歪み速度εt と変形抵抗σとの間には、σ=k
×εt m の関係が成立し、はんだのような超塑性材料で
はmが通常の金属より大きい。mが大きいということ
は、次のことを意味している。すなわち、局部的に大き
な外力により歪み速度εtが大きくなっている部位の変
形抵抗σは大きいのでこの部位は変形しにくく、一方、
局部的に小さい外力により歪み速度εt が小さくなって
いる部位の変形抵抗σは小さいのでこの部位は変形し易
い。つまり、小外力印加部位は変形し易く、大外力印加
部位は変形しにくい。To explain this meaning, in order to bring the bonding strength of the solder bump close to the melting (alloy) level, it is necessary to realize good bonding not on a part of the bonding surface but on the entire surface. Between the strain rate ε t and the deformation resistance σ, σ = k
The relationship of × ε t m is established, and m is larger than ordinary metal in superplastic materials such as solder. The fact that m is large means the following. That is, since the deformation resistance σ of the portion where the strain rate ε t is large due to a large external force locally is large, this portion is difficult to deform, while
Since the deformation resistance σ of the part where the strain rate ε t is small due to the locally small external force is small, this part is easily deformed. That is, the small external force application site is easily deformed, and the large external force application site is not easily deformed.
【0012】もし、これが上記とは異なって、小外力印
加部位も大外力印加部位も同じ変形し易さとすれば、局
部的に大きな外力が印加されている部位の歪み速度εt
は大きいのでこの部分の変形量は大きく、局部的に小さ
い外力が印加されている部位の歪み速度εt は小さいの
でこの部分の変形量は小さく、結果的に、大外力印加部
位が集中的に変形し、小外力印加部位の変形量が不足
し、はんだバンプで言えばその部位の接合強度が不足す
ることになる。特にはんだバンプは半球形状をを有して
おり、外力が均一に印加されない形状であるので、mが
小さいと接合全面にわたって良好に変形することが難し
い。If this is different from the above and if it is easy to deform both the small external force applying portion and the large external force applying portion, the strain rate ε t of the portion to which a large external force is locally applied is ε t.
Is large, the amount of deformation of this part is large, and the strain rate ε t of the part where a small external force is locally applied is small, so the amount of deformation of this part is small. It deforms, and the amount of deformation of the portion to which the small external force is applied is insufficient, and in terms of the solder bump, the joining strength of that portion is insufficient. In particular, since the solder bump has a hemispherical shape and the external force is not uniformly applied, it is difficult to deform well over the entire bonding surface when m is small.
【0013】実験結果によれば、はんだバンプでは、歪
み速度依存指数mが0.3以上あれば、溶融はんだ並み
の接合強度が得られることがわかった。According to the experimental results, it has been found that the solder bump can obtain a bonding strength comparable to that of the molten solder if the strain rate dependence index m is 0.3 or more.
【0014】[0014]
【実施例】以下、この発明を具体化した一実施例を図面
に従って説明する。本実施例装置は、ガラス基板(液晶
表示装置)上に半導体チップを搭載するCOG(Chi
p On Glass)製品であり、図1にガラス基板
1上にICチップ2が直接ボンディングされた状態を示
し、図2にボンディング前の、図3にボンディング後の
ICチップ2の要部を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The device of this embodiment is a COG (Chi) device in which a semiconductor chip is mounted on a glass substrate (liquid crystal display device).
FIG. 1 shows a state in which the IC chip 2 is directly bonded on the glass substrate 1, FIG. 2 shows a state before the bonding, and FIG. 3 shows a main part of the IC chip 2 after the bonding.
【0015】ICチップ2の表面にはチップ側接続電極
としてアルミ電極3が形成され、その表面はパッシベー
ション層4にて覆われている。又、アルミ電極3の一部
が露出され、この露出部分において、アルミ電極3上に
はクロムやチタンよりなるバリアメタル5が形成されて
いる。そのバリアメタル5上には銅バンプ6が配置さ
れ、銅バンプ6の表面にはハンダ7が配置されている。
このハンダ7としては、Pbー63Sn(共晶ハンダ)
が用いられており、このハンダの融点は183℃であ
る。製造工程としては、バリアメタル5を蒸着後、銅及
びハンダの連続メッキを行い、さらに、不回折雰囲気炉
中250℃にてリフローすることにより電極先端部を半
球状とすればよい。An aluminum electrode 3 is formed as a chip-side connection electrode on the surface of the IC chip 2, and the surface thereof is covered with a passivation layer 4. A part of the aluminum electrode 3 is exposed, and a barrier metal 5 made of chromium or titanium is formed on the aluminum electrode 3 in this exposed part. Copper bumps 6 are arranged on the barrier metal 5, and solders 7 are arranged on the surfaces of the copper bumps 6.
As this solder 7, Pb-63Sn (eutectic solder)
Is used, and the melting point of this solder is 183 ° C. In the manufacturing process, after vapor deposition of the barrier metal 5, continuous plating of copper and solder is performed, and further, reflowing is performed at 250 ° C. in a non-diffraction atmosphere furnace so that the electrode tip portion has a hemispherical shape.
【0016】ボンディング前のガラス基板(配線基板)
1を図4(平面図)に示す。ガラス基板1には、チップ
側接続端子としての導電パタ−ン10が形成されてい
る。導電パタ−ン10は三層構造をなし、ソーダガラス
上にITO(インジウム・スズ・オキサイド)層11と
ニッケル層12と金層13とが順に積層されている。こ
の積層構造は、ITO/Ni/Auを蒸着,メッキ似て
形成される。ここで、表面の金層13は、配線母材とし
てのITO層11とニッケル層12の酸化防止材となっ
ている。Glass substrate (wiring substrate) before bonding
1 is shown in FIG. 4 (plan view). A conductive pattern 10 is formed on the glass substrate 1 as a chip-side connection terminal. The conductive pattern 10 has a three-layer structure, and an ITO (indium tin oxide) layer 11, a nickel layer 12, and a gold layer 13 are sequentially laminated on a soda glass. This laminated structure is formed by vapor deposition of ITO / Ni / Au, similar to plating. Here, the gold layer 13 on the surface serves as an antioxidant for the ITO layer 11 and the nickel layer 12 as the wiring base material.
【0017】そして、ボンディングの際には、ガラス基
板1を所定位置に置き、吸着ヘッドによりICチップ2
をガラス基板1の上方に搬送し、位置合わせを行う。そ
して、ICチップ2をガラス基板1上に載置する。その
後、ダングステン(W)製の加熱ヘッドにてICチップ
2の裏面(図1、2の上面)から1つのバンプ当たり必
要な荷重をかけるとともに、加熱ヘッドの温度を120
〜175℃にして10〜30秒間保持する。つまり、ハ
ンダ7の融点の183℃よりも低い温度で、ICチップ
2とガラス基板1との間を加圧してハンダ7を塑性変形
させながら接合する。At the time of bonding, the glass substrate 1 is placed at a predetermined position, and the IC chip 2 is attached by the suction head.
Is transported to above the glass substrate 1 and is aligned. Then, the IC chip 2 is placed on the glass substrate 1. After that, a necessary load is applied to each bump from the back surface of the IC chip 2 (upper surface of FIGS. 1 and 2) with a heating head made of Dangsten (W), and the temperature of the heating head is set to 120 ° C.
Bring to ~ 175 ° C and hold for 10-30 seconds. That is, at a temperature lower than 183 ° C., which is the melting point of the solder 7, pressure is applied between the IC chip 2 and the glass substrate 1 to join the solder 7 while plastically deforming it.
【0018】このとき、加熱温度がハンダ7の融点以下
なのでハンダ7は溶融していないが柔らかくなってお
り、接合部は変形し面接触となっている。又、この加圧
してハンダ7を塑性変形させながら接合させる時にハン
ダ7の表面が先送りされ、新鮮なハンダが露出されて接
合界面が作られる。そして、導電パタ−ン10でのAu
(金)は接合部近傍のハンダ7中にほぼ拡散しており、
ニッケルも界面のSn粒子に少量拡散していることがE
DX分析法による断面分析で確認した。At this time, since the heating temperature is not higher than the melting point of the solder 7, the solder 7 is not melted but is soft, and the joint is deformed and comes into surface contact. Further, when the solder 7 is joined while being plastically deformed under pressure, the surface of the solder 7 is advanced, and fresh solder is exposed to form a joint interface. Then, Au in the conductive pattern 10
(Gold) is almost diffused in the solder 7 near the joint,
Nickel also diffused in a small amount into the Sn particles at the interface E
It was confirmed by cross-sectional analysis by the DX analysis method.
【0019】さらに、端子数や端子サイズに応じて加熱
ヘッドによる加圧力を調整することにより接続面積、ハ
ンダバンプ形状を容易に調整することができる。尚、局
部加熱は、加熱ヘッドによらずに、レーザをバンプ部分
に照射することにより行ってもよい。ここで、前述の接
合条件について詳細に説明する。Further, the connection area and the solder bump shape can be easily adjusted by adjusting the pressure applied by the heating head according to the number of terminals and the terminal size. The local heating may be performed by irradiating the bump portion with a laser instead of using the heating head. Here, the above-mentioned joining conditions will be described in detail.
【0020】加熱時間(10〜30秒)は、加熱ヘッド
から基板側へ熱伝導が行われるに十分な時間であり、か
つ、生産性を確保するための上限の時間である。図5に
上記はんだバンプ7の変形速度(μm/sec)を種々
変化させた場合の接合強度の変化を示す。ただし、はん
だバンプ7の直径は約250μm、その厚さ(変形後)
は最大で約40μm、銅バンプ6の厚さは最大で約30
μmとした。The heating time (10 to 30 seconds) is a time sufficient for heat conduction from the heating head to the substrate side, and is an upper limit time for ensuring productivity. FIG. 5 shows changes in the bonding strength when the deformation speed (μm / sec) of the solder bump 7 is variously changed. However, the diameter of the solder bump 7 is about 250 μm, and its thickness (after deformation)
Is about 40 μm at maximum, and the thickness of copper bump 6 is about 30 at maximum.
μm.
【0021】接合装置としては、ミスズFA株式会社製
のフリップチップマウンタ(機種名フリップチップマウ
ンタ(特注品))を用い、同時に44個のはんだバンプ
7を接合した。変形速度の制御はフリップチップマウン
タの下降速度を制御して実施し、各変形速度毎に40
回、試験した。図5からわかるように、平均変形速度が
10μm(歪み速度εt 換算10-1(1/sec))で
のバンプ電極7一個当たりの接合強度は80g重が得ら
れ、3μm(歪み速度εt 換算3×10-1(1/se
c))でのバンプ電極7一個当たりの接合強度は85g
重得られ、1μm(歪み速度εt 換算×10-2(1/s
ec))でのバンプ電極7一個当たりの接合強度は88
g重得られた。A flip chip mounter (model name: flip chip mounter (custom-made product)) manufactured by Miss FA Co. was used as a joining device, and 44 solder bumps 7 were joined at the same time. The deformation speed is controlled by controlling the descending speed of the flip chip mounter, and the deformation speed is controlled at 40% for each deformation speed.
Tested once. As can be seen from FIG. 5, the bonding strength per bump electrode 7 is 80 g when the average deformation rate is 10 μm (strain rate ε t conversion 10 −1 (1 / sec)), and 3 μm (strain rate ε t Conversion 3 × 10 -1 (1 / se
The bonding strength per bump electrode 7 in c)) is 85 g.
1 μm (strain rate ε t conversion × 10 -2 (1 / s
ec)), the bonding strength per bump electrode 7 is 88.
g weight was obtained.
【0022】次に、はんだバンプ7のSnとPbとの組
成を30〜70重量部対70〜30重量部の範囲で変更
して同じ試験を実施した。その結果、図5とほぼ同じ特
性が得られた。すなわち、平均変形速度を10μm以下
とした場合に従来の変形速度(30〜50μm/s)に
比較して格段に良好な接合強度が得られ、平均変形速度
を1〜3μmとした場合に、溶融はんだにほとんど匹敵
する接合強度が達成できた。特にその内、はんだバンプ
をSnを61〜65wt%含む共晶性はんだとすると、
後述する歪み速度依存指数mが大きくなるので、良好な
接合強度が得られた。Next, the same test was carried out by changing the composition of Sn and Pb of the solder bump 7 in the range of 30 to 70 parts by weight to 70 to 30 parts by weight. As a result, almost the same characteristics as in FIG. 5 were obtained. That is, when the average deformation rate is set to 10 μm or less, significantly better bonding strength is obtained as compared with the conventional deformation rate (30 to 50 μm / s), and when the average deformation rate is set to 1 to 3 μm, melting A joint strength almost equal to that of solder was achieved. In particular, if the solder bump is made of eutectic solder containing 61 to 65 wt% of Sn,
Since the strain rate dependence index m described later becomes large, good bonding strength was obtained.
【0023】次に、上記した共晶はんだの歪み速度εt
と変形抵抗σとの関係を調べた。図6にその結果を示
す。試験には、島津株式会社製の引っ張り試験機(機種
名サーボパルサー(特注品))を用い、板状試験品の断
面積は20mm2 とした。歪み速度εt は、実験式σ=
kεt m で決まり、εt を変化させた時のσを測定し
た。Next, the strain rate ε t of the eutectic solder described above
And the deformation resistance σ were investigated. The results are shown in FIG. For the test, a tensile tester manufactured by Shimadzu Corporation (model name: servo pulser (custom-made product)) was used, and the cross-sectional area of the plate-shaped test product was 20 mm 2 . The strain rate ε t is empirical formula σ =
It was determined by k ε t m , and σ was measured when ε t was changed.
【0024】図6からわかるように、歪み速度εt が1
×10-1(1/sec)までは歪み速度依存指数mは
0.3以上であり、歪み速度εt の増大に連れて変形抵
抗σが増大する領域であり、上述したよう原理により印
加外力が各部で異なっても均一な変形を可能である。そ
して超塑性をしめすはんだでも歪み速度εt が3(1/
sec)以上、特に6(1/sec)以上になると、歪
み速度εt の増加にもかかわらず変形抵抗σは増加せ
ず、この部位だけが局部的に変形してしまい、全面的な
塑性変形により接合強度が低下してしまうことが推定で
きる。As can be seen from FIG. 6, the strain rate ε t is 1
The strain rate dependence exponent m is 0.3 or more up to × 10 −1 (1 / sec), which is a region where the deformation resistance σ increases as the strain rate ε t increases. Even if each part is different, uniform deformation is possible. Even with solder exhibiting superplasticity, the strain rate ε t is 3 (1 /
sec) or more, especially 6 (1 / sec) or more, the deformation resistance σ does not increase despite the increase of the strain rate ε t , and only this part locally deforms, and the entire plastic deformation occurs. Therefore, it can be estimated that the bonding strength is reduced.
【0025】なお上記実施例では導電パタ−ン10(配
線材)をAu/Ni/ITOとしたが、Au,Ni,S
n,Ag,AgーPd,AgーPt,Cuなどハンダが
付くものであればよく、又、ハンダとしてPbー63S
n以外の組成のハンダを使用してもよく、要は、少なく
ともスズを含む低融点金属であればよい。さらに、前記
実施例では銅バンプ6(突起電極)上にハンダ7を設け
たが、特に突起電極を設ける必要はなく、ハンダボール
をチップ2と基板1との間に供給する方法でもよい。金
層13は省略可能である。ニッケル層12の代わりには
んだバンプ7と合金可能な金属を採用することも可能で
ある。In the above embodiment, the conductive pattern 10 (wiring material) is Au / Ni / ITO, but Au, Ni, S
Any material such as n, Ag, Ag-Pd, Ag-Pt, Cu that can be soldered may be used, and Pb-63S as the solder.
Solder having a composition other than n may be used, and the point is that it is a low melting point metal containing at least tin. Furthermore, although the solder 7 is provided on the copper bumps 6 (projection electrodes) in the above-described embodiment, it is not necessary to provide the projection electrodes in particular, and a method of supplying solder balls between the chip 2 and the substrate 1 may be used. The gold layer 13 can be omitted. Instead of the nickel layer 12, it is also possible to adopt a metal that can be alloyed with the solder bump 7.
【図1】本実施例のボンディング部分(端子部分)の拡
大図である。FIG. 1 is an enlarged view of a bonding portion (terminal portion) of this embodiment.
【図2】ボンディング後の状態を示す図である。FIG. 2 is a diagram showing a state after bonding.
【図3】ボンディング前のICチップの端子部分を示す
図である。FIG. 3 is a diagram showing a terminal portion of an IC chip before bonding.
【図4】ボンディング前のガラス基板の端子部分を示す
図である。FIG. 4 is a diagram showing a terminal portion of a glass substrate before bonding.
【図5】変形速度と接合強度との関係の測定結果を示す
図である。FIG. 5 is a diagram showing a measurement result of a relationship between a deformation rate and a bonding strength.
【図6】歪み速度と変形抵抗との関係の測定結果を示す
図である。FIG. 6 is a diagram showing measurement results of the relationship between strain rate and deformation resistance.
1 ガラス基板(配線基板) 2 半導体チップ 3 アルミ電極(半導体チップの接続電極) 7 はんだバンプ 10 導電パタ−ン(配線基板の接続電極) 1 Glass substrate (wiring substrate) 2 Semiconductor chip 3 Aluminum electrode (semiconductor chip connection electrode) 7 Solder bump 10 Conductive pattern (wiring substrate connection electrode)
Claims (5)
はんだバンプを配線基板の接続電極にその融点未満の温
度条件下で圧接し、前記はんだバンプを塑性変形して前
記配線基板の接続電極と合金接合する半導体装置の実装
方法において、 前記はんだバンプの変形速度を10μm/sec以下と
することを特徴とする半導体装置の実装方法。1. A solder bump formed on the surface of a connection electrode of a semiconductor chip is pressed against a connection electrode of a wiring board under a temperature condition below its melting point, and the solder bump is plastically deformed to form a connection electrode of the wiring board. A method of mounting a semiconductor device, which comprises alloy bonding, characterized in that a deformation speed of the solder bump is 10 μm / sec or less.
/sec以下とすることを特徴とする半導体装置の実装
方法。2. The deformation rate of the solder bumps is 1 to 3 μm.
/ Sec or less, a method of mounting a semiconductor device.
30〜70重量部対70〜30重量部とされる請求項1
記載の半導体装置の実装方法。3. The ratio of Sn to Pb of the solder bump is 30 to 70 parts by weight to 70 to 30 parts by weight.
A method for mounting a semiconductor device as described above.
%含む共晶性はんだとされる。4. The solder bump contains 61 to 65 wt% Sn.
% Eutectic solder.
形抵抗をσ、比例定数をk、歪み速度依存指数をm、σ
=k×εt m とし、その歪み速度依存指数mが0.3以
上となる範囲で前記圧接を実施する請求項1記載の半導
体装置の実装方法。5. In a preferred embodiment, the strain rate is ε t , the deformation resistance is σ, the proportional constant is k, the strain rate dependent exponent is m, σ.
= A k × ε t m, a mounting method of a semiconductor device according to claim 1, wherein the strain rate dependence exponent m is implementing said pressure within an amount of 0.3 or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22193493A JP3308060B2 (en) | 1993-09-07 | 1993-09-07 | Semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22193493A JP3308060B2 (en) | 1993-09-07 | 1993-09-07 | Semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0778848A true JPH0778848A (en) | 1995-03-20 |
| JP3308060B2 JP3308060B2 (en) | 2002-07-29 |
Family
ID=16774454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22193493A Expired - Fee Related JP3308060B2 (en) | 1993-09-07 | 1993-09-07 | Semiconductor device mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3308060B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0821407A3 (en) * | 1996-02-23 | 1998-03-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor devices having protruding contacts and method for making the same |
-
1993
- 1993-09-07 JP JP22193493A patent/JP3308060B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0821407A3 (en) * | 1996-02-23 | 1998-03-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor devices having protruding contacts and method for making the same |
| US5952718A (en) * | 1996-02-23 | 1999-09-14 | Matsushita Electric Industrial Co., Ltd. | Semiconductor devices having protruding contacts |
| US6107120A (en) * | 1996-02-23 | 2000-08-22 | Matsushita Electric Indsutrial Co., Ltd. | Method of making semiconductor devices having protruding contacts |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3308060B2 (en) | 2002-07-29 |
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