JPH0779018A - Semiconductor light-emitting device - Google Patents

Abstract

PURPOSE:To obtain a light-emitting diode which has a high luminance and the excellent stability of attachment. CONSTITUTION:An annular trench 17 is provided on the main surface of the p-type region 13 side of a semiconductor substrate composed of the p-type region 13 and an n-type region 12 composed of an n-type substrate 11 and an epitaxial layer and the center part and the circumferential part of the p-type region 12 are electrically separated from each other to increase the current density of the center part. An insulating film 23 of the trench 17 functions as a light reflective film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device such as a GaP light emitting diode.

[0002]

2. Description of the Related Art As a GaP light emitting diode chip structure suitable for mounting with an n-type semiconductor substrate side, that is, a side provided with a cathode electrode as an upper surface, the applicant of the present application has previously filed Japanese Patent Application No.
No. 52884 proposes a semiconductor light emitting device as shown in FIG. This semiconductor light emitting device has an n-type GaP substrate 1a.
And an n-type semiconductor region 1b consisting of an epitaxial growth layer, a p-type semiconductor region 2 and ap ⁺ type semiconductor region 3. n
The pn junction 4a between the type region 1b and the p-type region 2 extends parallel to the main surface, but the pn junction 4b between the n-type region 1b and the p ⁺ type region 3 extends from the bottom surface of the chip. It is extending away. An insulating film 5 is formed on the lower surface of the chip, and the anode electrode 6 is connected to the p-type semiconductor region 2 through the central opening. The anode electrode 6 extends on the insulating film 5 in order to surely achieve the connection to the conductive support 7, and is fixed to the support 7 by the solder 8. A cathode electrode 9 is annularly provided on the upper surface of the chip, and a window region 10 for taking out light is formed. This light emitting element has the advantage that the solder 8 does not adhere to the pn junction and that the current density in the central region of the pn junction is increased to achieve high brightness.

[0003]

By the way, recently, it is required to further increase the brightness of the light emitting element. In order to meet this demand, the applicant of the present application tried to improve the current density in the central region by reducing the chip area of the light emitting device having the structure shown in FIG. However, not only is it difficult to stably fix it to the support, but also the expected high brightness is achieved due to diffusion of light in the peripheral direction (lateral direction) and light shielding by the cathode electrode 9. There wasn't.

Therefore, an object of the present invention is to provide a semiconductor light emitting device which can be stably attached to a support and which can achieve high brightness.

[0005]

According to the present invention for achieving the above object, a first semiconductor region of a first conductivity type is formed adjacent to a first semiconductor region so as to form a pn junction. A semiconductor substrate having a second semiconductor region of the second conductivity type, a first electrode connected to the first semiconductor region on one main surface of the semiconductor substrate, and the other main surface of the semiconductor substrate. A second electrode connected to the second semiconductor region, and a second main surface of the semiconductor substrate is opened in a semiconductor light-emitting element configured to connect the second electrode to a support. An insulating film is provided to cover the second semiconductor region, the opening is disposed in a central portion of the second semiconductor region, and the second electrode is provided with the second electrode through the opening.
Of the second semiconductor region and an electrical isolation region is provided between the central portion and the peripheral portion of the second semiconductor region. The present invention relates to a semiconductor light emitting device. It is desirable that the isolation region is a groove as described in claim 2. Further, it is desirable to provide a third semiconductor region as described in claim 3. Further, as described in claim 4, it is desirable that the first electrode is formed in an annular shape so as to surround the opening of the insulating film when seen in a plan view.

[0006]

The operation and effect of the present invention, the electric isolation region between the central portion and the peripheral portion of the second semiconductor region has a function of limiting the spread of the electric current to the peripheral portion, and the electric current of the central portion is reduced. It contributes to the improvement of density and achieves high brightness.
Further, since the peripheral portion of the second semiconductor region has a function as an attachment region to the support through the insulating film and the second electrode, stable attachment to the support becomes possible. According to the invention of claim 2, the electrical isolation region can be easily obtained by the groove. According to the third aspect of the present invention, the position of the pn junction exposed on the side surface of the semiconductor substrate can be moved away from the support, and the fixing to the support becomes easy. According to the invention of claim 4, it is possible to favorably extract the light.

[0007]

EXAMPLE Next, a green GaP according to an example of the present invention
A light emitting device, that is, a green light emitting diode (LED) and a method for manufacturing the same will be described with reference to FIGS. First,
As shown in FIG. 1, an n-type GaP semiconductor region 12 is formed on a n-type GaP (gallium / phosphorus) semiconductor substrate (hereinafter referred to as an n-type substrate) 11 by a liquid phase epitaxial growth method,
Further, a semiconductor wafer 14 having a p-type GaP semiconductor region 13 formed thereon by an epitaxial growth method is prepared. The n-type semiconductor region 12 forming the pn junction 15 is doped with nitrogen in addition to Te (tellurium) as a conductivity type determining impurity, and the p-type semiconductor region 13 is Zn (zinc) as a conductivity type determining impurity. Besides, it is doped with nitrogen. Further, the thickness of the n-type and p-type semiconductor regions 12 and 13 is significantly smaller than that of the n-type substrate 11. The n-type substrate 11 and the n-type semiconductor region 12 function as a first semiconductor region, and the p-type semiconductor region 13 functions as a second semiconductor region.

Next, as shown in FIG. 2, dicing is performed from the surface of the wafer 14 on the p-type semiconductor region 13 side to form a relatively deep first groove 16 and a shallower second groove 17. . The first and second grooves 16 and 17 are formed in an annular shape as shown in FIG. 8, and the first groove 16 is the second groove 17
Siege. Areas 18, 19 partitioned by the first groove 16
Etc. are each one element.

Next, the wafer 14 shown in FIG. 2 is etched to form the first and second grooves 16 and 1 as shown in FIG.
The side wall of 7 is inclined to widen its opening width. Each of the first and second trenches 16 and 17 is formed so as to reach the n-type semiconductor region 12 beyond the pn junction 15. The first
The second grooves 16 and 17 may be formed deeper than the pn junction 15 in the etching process of FIG. In the present embodiment, the second groove 17 is also formed to a depth exceeding the pn junction 15, but the second groove 17 is not necessarily formed in the pn junction.
It does not need to be formed deeper than the junction 15 and may reach the pn junction 15 so that the p-type semiconductor region 13 can be separated. It is also possible to omit the dicing step of FIG. 2 and obtain the wafer of FIG. 3 only by etching.

Next, a mask diagram (not shown) is formed on the surface of the p-type semiconductor region 13 surrounded by the second groove 17, and p-type impurities are selectively introduced into the upper surface side of the wafer 14. Figure 4
As shown in, the p ⁺ type semiconductor region 20 is formed as the p type third semiconductor region. The p ⁺ type semiconductor region 20 having an impurity concentration higher than that of the p type semiconductor region 13 is a pn junction of the n type and p type semiconductor regions 12 and 13 exposed in the first and second trenches 16 and 17 in FIG. And a new pn junction 21 is formed between it and the n-type semiconductor region 12. When an inversion layer is formed on the substrate 11 as a result of impurity diffusion without forming a mask on the substrate 11 side, the inversion layer is removed by polishing or etching. Further, p ⁺ -type semiconductor region 20 after the formation over the entire surface of the wafer top surface, the p-type p ⁺ -type semiconductor region 20 formed in the p-type semiconductor region 13 surrounded by a second trench 17 is removed by etching the semiconductor The region 13 may be exposed on the upper surface of the wafer.

Next, a silicon oxide film is formed on the entire upper surface of the wafer 14 and then selectively etched.
As shown in FIG. 5, an insulating film 23 having an opening 22 for exposing the surface of the central portion of the p-type semiconductor region 13 surrounded by the second groove 17 is formed.

Next, Au (gold) is formed on the entire upper surface of the wafer 14.
An anode electrode (second electrode) which is vacuum-deposited to make ohmic contact with the p-type semiconductor region 13 through the opening 22.
24 is formed. Further, Au is vacuum-deposited on the lower surface of the wafer 14 to form a cathode electrode (first electrode) 25 which makes ohmic contact with the substrate 11. Cathode electrode 2
5 is formed in a plane annular shape on the lower surface of the wafer 14, and surrounds the ohmic contact surface 26 of the anode electrode 24 and the p-type semiconductor region 13 with a space therebetween as seen in a plan view. In the present embodiment, the cathode electrode 25 is connected to the second groove 17
Is facing. Later, the line L along the first groove 16
By cutting and separating the wafer 14 with, the individualized light emitting diode chips shown in FIG. 7 are completed. Figure 3 on the chip
The inclined side surface portion 16a corresponding to the first groove 16 and the groove 17a corresponding to the second groove 17 are formed.

FIG. 7 shows that the light emitting diode chip formed in this embodiment is fixed to the support 27 with solder 28 with the side on which the cathode electrode 25 is provided facing up.

The light emitting diode chip of this embodiment has the following effects. (1) The second groove 17 divides the pn junction 15,
Only the region of the pn junction 15 surrounded by the second groove 17 serves as a current path. As a result, the current density on the center side of the pn junction 15 can be increased and the brightness can be increased. (2) Since the light-reflecting insulating film 23 made of a silicon oxide film in the inclined groove 17 functions as a reflecting film, p
The light generated on the center side of the n-junction 15 can be efficiently guided to the window region 29 above the element by reflection here. (3) The area of the pn junction 15 is reduced without reducing the plane size of the semiconductor substrate (chip) including the n-type substrate 11, the n-type semiconductor region 12, the p-type semiconductor region 13, and the p ⁺ -type semiconductor region 20 so much. Because it is possible, pn that emits a large amount of light
The window region 29 can be provided in a relatively large area above the center of the joint 15. Therefore, the light can be efficiently extracted to the outside. (4) Since the protruding portion between the first groove 16 and the second groove 17 functions as a support leg of the element, the contact area between the p-type region 13 and the anode electrode 24 is small, but the element is stable. The sex is improving. In addition, the effects of the above items (1) to (3) are combined to achieve high brightness.

[0015]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) The p ⁺ type semiconductor region 20 may be omitted from the chip of FIG. 7 to form the structure shown in FIG. The p ⁺ type semiconductor region 20 is preferably formed in order to reduce the leakage current that does not contribute to light emission, but it is not necessarily provided.
In FIG. 11, the same parts as those in FIG. 7 are designated by the same reference numerals. (2) The opening 22 and the window region 29 can be circular. (3) The solder 28 can be another conductive bonding material. (4) A light-reflecting insulating layer can be formed so as to fill the groove 17.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a wafer for manufacturing a light emitting diode according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a wafer having first and second grooves formed therein.

3 is a cross-sectional view showing the wafer after etching the groove of FIG.

FIG. 4 is a cross-sectional view showing a wafer having ap ⁺ type semiconductor region formed therein.

FIG. 5 is a cross-sectional view showing a wafer on which an insulating film is formed.

FIG. 6 is a cross-sectional view showing a wafer on which a cathode electrode and an anode electrode are formed.

FIG. 7 is a cross-sectional view showing a state in which a light emitting diode is fixed to a support.

FIG. 8 is a plan view of the wafer of FIG.

9 is a plan view of the light emitting diode of FIG. 7 viewed from the anode side.

FIG. 10 is a cross-sectional view showing a state in which a conventional light emitting diode is attached to a support.

FIG. 11 is a cross-sectional view showing a state in which a light emitting diode of a modified example is attached to a support.

[Explanation of symbols]

 12 n-type semiconductor region 13 p-type semiconductor region 16 first groove 17 second groove 23 insulating film 24 anode electrode 25 cathode electrode

Claims (4)

[Claims] 1. A first semiconductor region of a first conductivity type and pn
A semiconductor base having a second semiconductor region of a second conductivity type adjacent to the first semiconductor region so as to form a junction; and a first semiconductor region on one main surface of the semiconductor base. A second electrode connected to the second semiconductor region on the other main surface of the semiconductor substrate, and the second electrode is connected to a support. In the semiconductor light emitting device described above, an insulating film that covers the other main surface of the semiconductor substrate with an opening is provided, the opening is arranged in a central portion of the second semiconductor region, and the second electrode is provided. Is connected to the second semiconductor region through the opening and is also provided on the insulating film. The electrical isolation region is provided between the central portion and the peripheral portion of the second semiconductor region. Is provided Semiconductor light-emitting element. 2. The electrical isolation region is a groove extending from the other main surface of the semiconductor substrate toward the one main surface, and the groove is formed so as to reach the first semiconductor region. The semiconductor light emitting device according to claim 1, wherein: 3. A third semiconductor region having the same second conductivity type as the second semiconductor region and having an impurity concentration higher than that of the second semiconductor region is the other main portion of the semiconductor substrate. The third region is provided in a peripheral region other than the central region of the surface and extends to the one main surface side of the semiconductor substrate from the peripheral edge of the pn junction surface between the first semiconductor region and the second semiconductor region. The semiconductor light emitting device according to claim 1 or 2, wherein the semiconductor region extends. 4. The semiconductor light emitting device according to claim 1, wherein the first electrode is formed in an annular shape so as to surround the opening when seen in a plan perspective manner.